void __led_init(led_id_t mask, int state)
{
bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~(PF8));
bfin_write_PORTG_FER(bfin_read_PORTG_FER() & ~(PG11 | PG12));
bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() & ~(PF8));
bfin_write_PORTGIO_INEN(bfin_read_PORTGIO_INEN() & ~(PG11 | PG12));
bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | (PF8));
bfin_write_PORTGIO_DIR(bfin_read_PORTGIO_DIR() | (PG11 | PG12));
}
void board_reset(void)
{
/* workaround for weak pull ups on ssel */
if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~PF10);
bfin_write_PORTFIO_SET(PF10);
udelay(1);
}
}
int post_key_pressed(void)
{
int i, n;
unsigned short value;
bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~PF5);
bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() & ~PF5);
bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() | PF5);
SSYNC();
post_out_buff("########Press SW10 to enter Memory POST########: 3\0");
for (i = 0; i < KEY_LOOP; i++) {
value = bfin_read_PORTFIO() & PF5;
if (bfin_read_UART0_RBR() == 0x0D) {
value = 0;
goto key_pressed;
}
if (value != 0)
goto key_pressed;
for (n = 0; n < KEY_DELAY; n++)
asm("nop");
}
post_out_buff("\b2\0");
for (i = 0; i < KEY_LOOP; i++) {
value = bfin_read_PORTFIO() & PF5;
if (bfin_read_UART0_RBR() == 0x0D) {
value = 0;
goto key_pressed;
}
if (value != 0)
goto key_pressed;
for (n = 0; n < KEY_DELAY; n++)
asm("nop");
}
post_out_buff("\b1\0");
for (i = 0; i < KEY_LOOP; i++) {
value = bfin_read_PORTFIO() & PF5;
if (bfin_read_UART0_RBR() == 0x0D) {
value = 0;
goto key_pressed;
}
if (value != 0)
goto key_pressed;
for (n = 0; n < KEY_DELAY; n++)
asm("nop");
}
key_pressed:
post_out_buff("\b0");
post_out_buff("\n\r\0");
if (value == 0)
return 0;
post_out_buff("Hotkey has been pressed, Enter POST . . . . . .\n\r\0");
return 1;
}
int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
if (argc != 3) {
show_usage:
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
}
/* parse the behavior */
ulong port_cmd = 0;
switch (argv[1][0]) {
case 'i': break;
case 's': port_cmd = (PORTFIO_SET - PORTFIO); break;
case 'c': port_cmd = (PORTFIO_CLEAR - PORTFIO); break;
case 't': port_cmd = (PORTFIO_TOGGLE - PORTFIO); break;
default: goto show_usage;
}
/* parse the pin with format: [p]<fgh><#> */
const char *str_pin = argv[2];
/* grab the [p]<fgh> portion */
ulong port_base;
if (*str_pin == 'p') ++str_pin;
switch (*str_pin) {
case 'f': port_base = PORTFIO; break;
case 'g': port_base = PORTGIO; break;
case 'h': port_base = PORTHIO; break;
default: goto show_usage;
}
/* grab the <#> portion */
ulong pin = simple_strtoul(str_pin+1, NULL, 10);
ulong pin_mask = (1 << pin);
if (pin > 15)
goto show_usage;
/* finally, let's do it: set direction and exec command */
switch (*str_pin) {
case 'f': bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~pin_mask); break;
case 'g': bfin_write_PORTG_FER(bfin_read_PORTG_FER() & ~pin_mask); break;
case 'h': bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~pin_mask); break;
}
ulong port_dir = port_base + (PORTFIO_DIR - PORTFIO);
if (argv[1][0] == 'i')
bfin_write16(port_dir, bfin_read16(port_dir) & ~pin_mask);
else {
bfin_write16(port_dir, bfin_read16(port_dir) | pin_mask);
bfin_write16(port_base + port_cmd, pin_mask);
}
printf("gpio: pin %li on port %c has been %c\n", pin, *str_pin, argv[1][0]);
return 0;
}
void post_init_uart(int sclk)
{
int divisor;
for (divisor = 0; sclk > 0; divisor++)
sclk -= 57600 * 16;
bfin_write_PORTF_FER(0x000F);
bfin_write_PORTH_FER(0xFFFF);
bfin_write_UART_GCTL(0x00);
bfin_write_UART_LCR(0x83);
SSYNC();
bfin_write_UART_DLL(divisor & 0xFF);
SSYNC();
bfin_write_UART_DLH((divisor >> 8) & 0xFF);
SSYNC();
bfin_write_UART_LCR(0x03);
SSYNC();
bfin_write_UART_GCTL(0x01);
SSYNC();
}
void bfspi_reset(int reset_bit) {
PRINTK("toggle reset\n");
#if (defined(CONFIG_BF533) || defined(CONFIG_BF532))
PRINTK("set reset to PF%d\n",reset_bit);
bfin_write_FIO_DIR(bfin_read_FIO_DIR() | (1<<reset_bit));
__builtin_bfin_ssync();
bfin_write_FIO_FLAG_C((1<<reset_bit));
__builtin_bfin_ssync();
udelay(100);
bfin_write_FIO_FLAG_S((1<<reset_bit));
__builtin_bfin_ssync();
#endif
#if (defined(CONFIG_BF536) || defined(CONFIG_BF537))
if (reset_bit == 1) {
PRINTK("set reset to PF10\n");
bfin_write_PORTF_FER(bfin_read_PORTF_FER() & 0xFBFF);
__builtin_bfin_ssync();
bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | 0x0400);
__builtin_bfin_ssync();
bfin_write_PORTFIO_CLEAR(1<<10);
__builtin_bfin_ssync();
udelay(100);
bfin_write_PORTFIO_SET(1<<10);
__builtin_bfin_ssync();
} else if (reset_bit == 2) {
PRINTK("Error: cannot set reset to PJ11\n");
} else if (reset_bit == 3) {
PRINTK("Error: cannot set reset to PJ10\n");
} else if (reset_bit == 4) {
PRINTK("set reset to PF6\n");
bfin_write_PORTF_FER(bfin_read_PORTF_FER() & 0xFFBF);
__builtin_bfin_ssync();
bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | 0x0040);
__builtin_bfin_ssync();
bfin_write_PORTFIO_CLEAR(1<<6);
__builtin_bfin_ssync();
udelay(100);
bfin_write_PORTFIO_SET(1<<6);
__builtin_bfin_ssync();
} else if (reset_bit == 5) {
PRINTK("set reset to PF5\n");
bfin_write_PORTF_FER(bfin_read_PORTF_FER() & 0xFFDF);
__builtin_bfin_ssync();
bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | 0x0020);
__builtin_bfin_ssync();
bfin_write_PORTFIO_CLEAR(1<<5);
__builtin_bfin_ssync();
udelay(100);
bfin_write_PORTFIO_SET(1<<5);
__builtin_bfin_ssync();
} else if (reset_bit == 6) {
PRINTK("set reset to PF4\n");
bfin_write_PORTF_FER(bfin_read_PORTF_FER() & 0xFFEF);
__builtin_bfin_ssync();
bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | 0x0010);
__builtin_bfin_ssync();
bfin_write_PORTFIO_CLEAR(1<<4);
__builtin_bfin_ssync();
udelay(100);
bfin_write_PORTFIO_SET(1<<4);
__builtin_bfin_ssync();
} else if (reset_bit == 7) {
PRINTK("Error: cannot set reset to PJ5\n");
} else if (reset_bit == 8) {
PRINTK("Using PF8 for reset...\n");
bfin_write_PORTF_FER(bfin_read_PORTF_FER() & 0xFEFF);
__builtin_bfin_ssync();
bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | 0x0100);
__builtin_bfin_ssync();
bfin_write_PORTFIO_CLEAR(1<<8);
__builtin_bfin_ssync();
udelay(100);
bfin_write_PORTFIO_SET(1<<8);
} else if ( reset_bit == 9 ) {
PRINTK("Using PF9 for reset...\n");
bfin_write_PORTF_FER(bfin_read_PORTF_FER() & 0xFDFF);
__builtin_bfin_ssync();
bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | 0x0200);
__builtin_bfin_ssync();
bfin_write_PORTFIO_CLEAR(1<<9);
__builtin_bfin_ssync();
udelay(100);
bfin_write_PORTFIO_SET(1<<9);
}
#endif
/*
p24 3050 data sheet, allow 1ms for PLL lock, with
less than 1ms (1000us) I found register 2 would have
a value of 0 rather than 3, indicating a bad reset.
*/
udelay(1000);
}
void bfspi_hardware_init(int baud, u16 new_chip_select_mask)
{
u16 ctl_reg, flag;
int cs, bit;
if (baud < 4) {
printk("\nkern>>baud = %d may mean SPI clock too fast for Si labs 3050"
"consider baud == 4 or greater", baud);
}
PRINTK("\nkern>> bfspi_spi_init\n");
PRINTK("kern>> new_chip_select_mask = 0x%04x\n", new_chip_select_mask);
#if (defined(CONFIG_BF533) || defined(CONFIG_BF532))
PRINTK("kern>> FIOD_DIR = 0x%04x\n", bfin_read_FIO_DIR());
#endif
#if (defined(CONFIG_BF536) || defined(CONFIG_BF537))
PRINTK(" FIOD_DIR = 0x%04x\n", bfin_read_PORTFIO_DIR());
#endif
/* grab SPISEL/GPIO pins for SPI, keep level of SPISEL pins H */
chip_select_mask |= new_chip_select_mask;
flag = 0xff00 | (chip_select_mask & 0xff);
/* set up chip selects greater than PF7 */
if (chip_select_mask & 0xff00) {
#if (defined(CONFIG_BF533) || defined(CONFIG_BF532))
bfin_write_FIO_DIR(bfin_read_FIO_DIR() | (chip_select_mask & 0xff00));
#endif
#if (defined(CONFIG_BF536) || defined(CONFIG_BF537))
bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | (chip_select_mask & 0xff00));
#endif
__builtin_bfin_ssync();
}
#if (defined(CONFIG_BF533) || defined(CONFIG_BF532))
PRINTK("kern>> After FIOD_DIR = 0x%04x\n", bfin_read_FIO_DIR());
#endif
#if (defined(CONFIG_BF536) || defined(CONFIG_BF537))
PRINTK(" After FIOD_DIR = 0x%04x\n",bfin_read_PORTFIO_DIR());
/* we need to work thru each bit in mask and set the MUX regs */
for(bit=0; bit<8; bit++) {
if (chip_select_mask & (1<<bit)) {
PRINTK("SPI CS bit: %d enabled\n", bit);
cs = bit;
if (cs == 1) {
PRINTK("set for chip select 1\n");
bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3c00);
__builtin_bfin_ssync();
} else if (cs == 2 || cs == 3) {
PRINTK("set for chip select 2\n");
bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PJSE_SPI);
__builtin_bfin_ssync();
bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3800);
__builtin_bfin_ssync();
} else if (cs == 4) {
bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS4E_SPI);
__builtin_bfin_ssync();
bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3840);
__builtin_bfin_ssync();
} else if (cs == 5) {
bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS5E_SPI);
__builtin_bfin_ssync();
bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3820);
__builtin_bfin_ssync();
} else if (cs == 6) {
bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS6E_SPI);
__builtin_bfin_ssync();
bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3810);
__builtin_bfin_ssync();
} else if (cs == 7) {
bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PJCE_SPI);
__builtin_bfin_ssync();
bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3800);
__builtin_bfin_ssync();
}
}
}
#endif
/* note TIMOD = 00 - reading SPI_RDBR kicks off transfer */
//Undefines flags lets patch it for now. BFSI is kind of obsolate.
//Will be replaced in teh future
ctl_reg = 0xD004; //0101 1100 0000 0100 SPE | MSTR | CPOL | CPHA | SZ;
ctl_reg |= (spimode << 10);
bfin_write_SPI_FLG(flag);
bfin_write_SPI_BAUD(baud);
bfin_write_SPI_CTL(ctl_reg);
}
static void spi_portmux(struct spi_slave *slave)
{
#if defined(__ADSPBF51x__)
#define SET_MUX(port, mux, func) port##_mux = ((port##_mux & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_##func)
u16 f_mux = bfin_read_PORTF_MUX();
u16 f_fer = bfin_read_PORTF_FER();
u16 g_mux = bfin_read_PORTG_MUX();
u16 g_fer = bfin_read_PORTG_FER();
u16 h_mux = bfin_read_PORTH_MUX();
u16 h_fer = bfin_read_PORTH_FER();
switch (slave->bus) {
case 0:
/* set SCK/MISO/MOSI */
SET_MUX(g, 7, 1);
g_fer |= PG12 | PG13 | PG14;
switch (slave->cs) {
case 1: SET_MUX(f, 2, 1); f_fer |= PF7; break;
case 2: /* see G above */ g_fer |= PG15; break;
case 3: SET_MUX(h, 1, 3); f_fer |= PH4; break;
case 4: /* no muxing */ h_fer |= PH8; break;
case 5: SET_MUX(g, 1, 3); h_fer |= PG3; break;
case 6: /* no muxing */ break;
case 7: /* no muxing */ break;
}
case 1:
/* set SCK/MISO/MOSI */
SET_MUX(h, 0, 2);
h_fer |= PH1 | PH2 | PH3;
switch (slave->cs) {
case 1: SET_MUX(h, 2, 3); h_fer |= PH6; break;
case 2: SET_MUX(f, 0, 3); f_fer |= PF0; break;
case 3: SET_MUX(g, 0, 3); g_fer |= PG0; break;
case 4: SET_MUX(f, 3, 3); f_fer |= PF8; break;
case 5: SET_MUX(g, 6, 3); h_fer |= PG11; break;
case 6: /* no muxing */ break;
case 7: /* no muxing */ break;
}
}
bfin_write_PORTF_MUX(f_mux);
bfin_write_PORTF_FER(f_fer);
bfin_write_PORTG_MUX(g_mux);
bfin_write_PORTG_FER(g_fer);
bfin_write_PORTH_MUX(h_mux);
bfin_write_PORTH_FER(h_fer);
#elif defined(__ADSPBF52x__)
#define SET_MUX(port, mux, func) port##_mux = ((port##_mux & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_##func)
u16 f_mux = bfin_read_PORTF_MUX();
u16 f_fer = bfin_read_PORTF_FER();
u16 g_mux = bfin_read_PORTG_MUX();
u16 g_fer = bfin_read_PORTG_FER();
u16 h_mux = bfin_read_PORTH_MUX();
u16 h_fer = bfin_read_PORTH_FER();
/* set SCK/MISO/MOSI */
SET_MUX(g, 0, 3);
g_fer |= PG2 | PG3 | PG4;
switch (slave->cs) {
case 1: /* see G above */ g_fer |= PG1; break;
case 2: SET_MUX(f, 4, 3); f_fer |= PF12; break;
case 3: SET_MUX(f, 4, 3); f_fer |= PF13; break;
case 4: SET_MUX(h, 1, 1); h_fer |= PH8; break;
case 5: SET_MUX(h, 2, 1); h_fer |= PH9; break;
case 6: SET_MUX(f, 1, 3); f_fer |= PF9; break;
case 7: SET_MUX(f, 2, 3); f_fer |= PF10; break;
}
bfin_write_PORTF_MUX(f_mux);
bfin_write_PORTF_FER(f_fer);
bfin_write_PORTG_MUX(g_mux);
bfin_write_PORTG_FER(g_fer);
bfin_write_PORTH_MUX(h_mux);
bfin_write_PORTH_FER(h_fer);
#elif defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__)
u16 mux = bfin_read_PORT_MUX();
u16 f_fer = bfin_read_PORTF_FER();
/* set SCK/MISO/MOSI */
f_fer |= PF11 | PF12 | PF13;
switch (slave->cs) {
case 1: f_fer |= PF10; break;
case 2: mux |= PJSE; break;
case 3: mux |= PJSE; break;
case 4: mux |= PFS4E; f_fer |= PF6; break;
case 5: mux |= PFS5E; f_fer |= PF5; break;
case 6: mux |= PFS6E; f_fer |= PF4; break;
case 7: mux |= PJCE_SPI; break;
}
bfin_write_PORT_MUX(mux);
bfin_write_PORTF_FER(f_fer);
#elif defined(__ADSPBF538__) || defined(__ADSPBF539__)
u16 fer, pins;
if (slave->bus == 1)
pins = PD0 | PD1 | PD2 | (slave->cs == 1 ? PD4 : 0);
else if (slave->bus == 2)
pins = PD5 | PD6 | PD7 | (slave->cs == 1 ? PD9 : 0);
else
pins = 0;
if (pins) {
fer = bfin_read_PORTDIO_FER();
fer &= ~pins;
bfin_write_PORTDIO_FER(fer);
}
#elif defined(__ADSPBF54x__)
#define DO_MUX(port, pin) \
mux = ((mux & ~PORT_x_MUX_##pin##_MASK) | PORT_x_MUX_##pin##_FUNC_1); \
fer |= P##port##pin;
u32 mux;
u16 fer;
switch (slave->bus) {
case 0:
mux = bfin_read_PORTE_MUX();
fer = bfin_read_PORTE_FER();
/* set SCK/MISO/MOSI */
DO_MUX(E, 0);
DO_MUX(E, 1);
DO_MUX(E, 2);
switch (slave->cs) {
case 1: DO_MUX(E, 4); break;
case 2: DO_MUX(E, 5); break;
case 3: DO_MUX(E, 6); break;
}
bfin_write_PORTE_MUX(mux);
bfin_write_PORTE_FER(fer);
break;
case 1:
mux = bfin_read_PORTG_MUX();
fer = bfin_read_PORTG_FER();
/* set SCK/MISO/MOSI */
DO_MUX(G, 8);
DO_MUX(G, 9);
DO_MUX(G, 10);
switch (slave->cs) {
case 1: DO_MUX(G, 5); break;
case 2: DO_MUX(G, 6); break;
case 3: DO_MUX(G, 7); break;
}
bfin_write_PORTG_MUX(mux);
bfin_write_PORTG_FER(fer);
break;
case 2:
mux = bfin_read_PORTB_MUX();
fer = bfin_read_PORTB_FER();
/* set SCK/MISO/MOSI */
DO_MUX(B, 12);
DO_MUX(B, 13);
DO_MUX(B, 14);
switch (slave->cs) {
case 1: DO_MUX(B, 9); break;
case 2: DO_MUX(B, 10); break;
case 3: DO_MUX(B, 11); break;
}
bfin_write_PORTB_MUX(mux);
bfin_write_PORTB_FER(fer);
break;
}
#endif
}
