void
SH3dev::pfc_dump()
{
DPRINTF((TEXT("<<<Pin Function Controller>>>\n")));
DPRINTF((TEXT("[control]\n")));
#define DUMP_PFC_REG(x) \
DPRINTF((TEXT("P%SCR :"), #x)); \
bitdisp(_reg_read_2(SH3_P##x##CR))
DUMP_PFC_REG(A);
DUMP_PFC_REG(B);
DUMP_PFC_REG(C);
DUMP_PFC_REG(D);
DUMP_PFC_REG(E);
DUMP_PFC_REG(F);
DUMP_PFC_REG(G);
DUMP_PFC_REG(H);
DUMP_PFC_REG(J);
DUMP_PFC_REG(K);
DUMP_PFC_REG(L);
#undef DUMP_PFC_REG
DPRINTF((TEXT("SCPCR :")));
bitdisp(_reg_read_2(SH3_SCPCR));
DPRINTF((TEXT("\n[data]\n")));
#define DUMP_IOPORT_REG(x) \
DPRINTF((TEXT("P%SDR :"), #x)); \
bitdisp(_reg_read_1(SH3_P##x##DR))
DUMP_IOPORT_REG(A);
DUMP_IOPORT_REG(B);
DUMP_IOPORT_REG(C);
DUMP_IOPORT_REG(D);
DUMP_IOPORT_REG(E);
DUMP_IOPORT_REG(F);
DUMP_IOPORT_REG(G);
DUMP_IOPORT_REG(H);
DUMP_IOPORT_REG(J);
DUMP_IOPORT_REG(K);
DUMP_IOPORT_REG(L);
#undef DUMP_IOPORT_REG
DPRINTF((TEXT("SCPDR :")));
bitdisp(_reg_read_1(SH3_SCPDR));
}
void
SH4dev::hd64465_dump()
{
DPRINTF((TEXT("<<<HD64465>>>\n")));
if (_reg_read_2(HD64465_SDIDR) != 0x8122) {
DPRINTF((TEXT("not found.\n")));
return;
}
DPRINTF((TEXT("SMSCR: "))); // standby
bitdisp(_reg_read_2(HD64465_SMSCR));
DPRINTF((TEXT("SPCCR: "))); // clock
bitdisp(_reg_read_2(HD64465_SPCCR));
DPRINTF((TEXT("\nNIRR: "))); // request
bitdisp(_reg_read_2(HD64465_NIRR));
DPRINTF((TEXT("NIMR: "))); // mask
bitdisp(_reg_read_2(HD64465_NIMR));
DPRINTF((TEXT("NITR: "))); // trigger
bitdisp(_reg_read_2(HD64465_NITR));
#if 0 // monitoring HD64465 interrupt request.
suspendIntr();
while (1)
bitdisp(_reg_read_2(HD64465_NIRR));
/* NOTREACHED */
#endif
}
void
SH3dev::icu_control()
{
const char *sense_select[] = {
"falling edge",
"raising edge",
"low level",
"reserved",
};
uint16_t r;
// PINT0-15
DPRINTF((TEXT("PINT enable(on |) :")));
bitdisp(_reg_read_2(SH3_PINTER));
DPRINTF((TEXT("PINT detect(high |):")));
bitdisp(_reg_read_2(SH3_ICR2));
// NMI
r = _reg_read_2(SH3_ICR0);
DPRINTF((TEXT("NMI(%S %S-edge),"),
r & SH3_ICR0_NMIL ? "High" : "Low",
r & SH3_ICR0_NMIE ? "raising" : "falling"));
r = _reg_read_2(SH3_ICR1);
DPRINTF((TEXT(" %S maskable,"), r & SH3_ICR1_MAI ? "" : "never"));
DPRINTF((TEXT(" SR.BL %S\n"),
r & SH3_ICR1_BLMSK ? "ignored" : "maskable"));
// IRQ0-5
DPRINTF((TEXT("IRQ[3:0]pin : %S mode\n"),
r & SH3_ICR1_IRQLVL ? "IRL 15level" : "IRQ[0:3]"));
if (r & SH3_ICR1_IRQLVL) {
DPRINTF((TEXT("IRLS[0:3] %S\n"),
r & SH3_ICR1_IRLSEN ? "enabled" : "disabled"));
}
// sense select
for (int i = 5; i >= 0; i--) {
DPRINTF((TEXT("IRQ[%d] %S\n"), i,
sense_select [
(r >>(i * 2)) & SH3_SENSE_SELECT_MASK]));
}
}
// INTC
void
SH4dev::icu_dump()
{
#define ON(x, c) ((x) & (c) ? check[1] : check[0])
#define _(n) DPRINTF((TEXT("%S %S "), #n, ON(r, SH4_ICR_ ## n)))
static const char *check[] = { "[_]", "[x]" };
u_int16_t r;
super::icu_dump_priority(_ipr_table);
r = _reg_read_2(SH4_ICR);
DPRINTF((TEXT("ICR: ")));
_(NMIL);
_(MAI);
_(NMIB);
_(NMIE);
_(IRLM);
DPRINTF((TEXT("0x%04x\n"), r));
#if 0 // monitoring SH4 interrupt request.
// disable SH3 internal devices interrupt.
suspendIntr();
_reg_write_2(SH4_IPRA, 0);
_reg_write_2(SH4_IPRB, 0);
_reg_write_2(SH4_IPRC, 0);
// _reg_write_2(SH4_IPRD, 0); SH7709S only.
resumeIntr(0); // all interrupts enable.
while (1) {
DPRINTF((TEXT("%04x ", _reg_read_2(HD64465_NIRR))));
bitdisp(_reg_read_4(SH4_INTEVT));
}
/* NOTREACHED */
#endif
#undef _
#undef ON
}
void
SH3dev::hd64461_dump(platid_t &platform)
{
uint16_t r16;
uint8_t r8;
#define MATCH(p) \
platid_match(&platform, &platid_mask_MACH_##p)
DPRINTF((TEXT("<<<HD64461>>>\n")));
if (!MATCH(HP_LX) &&
!MATCH(HP_JORNADA_6XX) &&
!MATCH(HITACHI_PERSONA_HPW230JC)) {
DPRINTF((TEXT("don't exist.")));
return;
}
#if 0
DPRINTF((TEXT("frame buffer test start\n")));
uint8_t *fb = reinterpret_cast<uint8_t *>(HD64461_FBBASE);
for (int i = 0; i < 320 * 240 * 2 / 8; i++)
*fb++ = 0xff;
DPRINTF((TEXT("frame buffer test end\n")));
#endif
// System
DPRINTF((TEXT("STBCR (System Control Register)\n")));
r16 = _reg_read_2(HD64461_SYSSTBCR_REG16);
bitdisp(r16);
#define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSTBCR_##m, #m)
DBG_BIT_PRINT(r16, CKIO_STBY);
DBG_BIT_PRINT(r16, SAFECKE_IST);
DBG_BIT_PRINT(r16, SLCKE_IST);
DBG_BIT_PRINT(r16, SAFECKE_OST);
DBG_BIT_PRINT(r16, SLCKE_OST);
DBG_BIT_PRINT(r16, SMIAST);
DBG_BIT_PRINT(r16, SLCDST);
DBG_BIT_PRINT(r16, SPC0ST);
DBG_BIT_PRINT(r16, SPC1ST);
DBG_BIT_PRINT(r16, SAFEST);
DBG_BIT_PRINT(r16, STM0ST);
DBG_BIT_PRINT(r16, STM1ST);
DBG_BIT_PRINT(r16, SIRST);
DBG_BIT_PRINT(r16, SURTSD);
#undef DBG_BIT_PRINT
DPRINTF((TEXT("\n")));
DPRINTF((TEXT("SYSCR (System Configuration Register)\n")));
r16 = _reg_read_2(HD64461_SYSSYSCR_REG16);
bitdisp(r16);
#define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSYSCR_##m, #m)
DBG_BIT_PRINT(r16, SCPU_BUS_IGAT);
DBG_BIT_PRINT(r16, SPTA_IR);
DBG_BIT_PRINT(r16, SPTA_TM);
DBG_BIT_PRINT(r16, SPTB_UR);
DBG_BIT_PRINT(r16, WAIT_CTL_SEL);
DBG_BIT_PRINT(r16, SMODE1);
DBG_BIT_PRINT(r16, SMODE0);
#undef DBG_BIT_PRINT
DPRINTF((TEXT("\n")));
DPRINTF((TEXT("SCPUCR (CPU Data Bus Control Register)\n")));
r16 = _reg_read_2(HD64461_SYSSCPUCR_REG16);
bitdisp(r16);
#define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_SYSSCPUCR_##m, #m)
DBG_BIT_PRINT(r16, SPDSTOF);
DBG_BIT_PRINT(r16, SPDSTIG);
DBG_BIT_PRINT(r16, SPCSTOF);
DBG_BIT_PRINT(r16, SPCSTIG);
DBG_BIT_PRINT(r16, SPBSTOF);
DBG_BIT_PRINT(r16, SPBSTIG);
DBG_BIT_PRINT(r16, SPASTOF);
DBG_BIT_PRINT(r16, SPASTIG);
DBG_BIT_PRINT(r16, SLCDSTIG);
DBG_BIT_PRINT(r16, SCPU_CS56_EP);
DBG_BIT_PRINT(r16, SCPU_CMD_EP);
DBG_BIT_PRINT(r16, SCPU_ADDR_EP);
DBG_BIT_PRINT(r16, SCPDPU);
DBG_BIT_PRINT(r16, SCPU_A2319_EP);
#undef DBG_BIT_PRINT
DPRINTF((TEXT("\n")));
DPRINTF((TEXT("\n")));
// INTC
DPRINTF((TEXT("NIRR (Interrupt Request Register)\n")));
r16 = _reg_read_2(HD64461_INTCNIRR_REG16);
bitdisp(r16);
#define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_INTCNIRR_##m, #m)
DBG_BIT_PRINT(r16, PCC0R);
DBG_BIT_PRINT(r16, PCC1R);
DBG_BIT_PRINT(r16, AFER);
DBG_BIT_PRINT(r16, GPIOR);
DBG_BIT_PRINT(r16, TMU0R);
DBG_BIT_PRINT(r16, TMU1R);
DBG_BIT_PRINT(r16, IRDAR);
DBG_BIT_PRINT(r16, UARTR);
#undef DBG_BIT_PRINT
DPRINTF((TEXT("\n")));
DPRINTF((TEXT("NIMR (Interrupt Mask Register)\n")));
r16 = _reg_read_2(HD64461_INTCNIMR_REG16);
bitdisp(r16);
#define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_INTCNIMR_##m, #m)
DBG_BIT_PRINT(r16, PCC0M);
DBG_BIT_PRINT(r16, PCC1M);
DBG_BIT_PRINT(r16, AFEM);
DBG_BIT_PRINT(r16, GPIOM);
DBG_BIT_PRINT(r16, TMU0M);
DBG_BIT_PRINT(r16, TMU1M);
DBG_BIT_PRINT(r16, IRDAM);
DBG_BIT_PRINT(r16, UARTM);
#undef DBG_BIT_PRINT
DPRINTF((TEXT("\n")));
DPRINTF((TEXT("\n")));
// PCMCIA
// PCC0
DPRINTF((TEXT("[PCC0 memory and I/O card (SH3 Area 6)]\n")));
DPRINTF((TEXT("PCC0 Interface Status Register\n")));
r8 = _reg_read_1(HD64461_PCC0ISR_REG8);
bitdisp(r8);
#define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0ISR_##m, #m)
DBG_BIT_PRINT(r8, P0READY);
DBG_BIT_PRINT(r8, P0MWP);
DBG_BIT_PRINT(r8, P0VS2);
DBG_BIT_PRINT(r8, P0VS1);
DBG_BIT_PRINT(r8, P0CD2);
DBG_BIT_PRINT(r8, P0CD1);
DBG_BIT_PRINT(r8, P0BVD2);
DBG_BIT_PRINT(r8, P0BVD1);
#undef DBG_BIT_PRINT
DPRINTF((TEXT("\n")));
DPRINTF((TEXT("PCC0 General Control Register\n")));
r8 = _reg_read_1(HD64461_PCC0GCR_REG8);
bitdisp(r8);
#define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0GCR_##m, #m)
DBG_BIT_PRINT(r8, P0DRVE);
DBG_BIT_PRINT(r8, P0PCCR);
DBG_BIT_PRINT(r8, P0PCCT);
DBG_BIT_PRINT(r8, P0VCC0);
DBG_BIT_PRINT(r8, P0MMOD);
DBG_BIT_PRINT(r8, P0PA25);
DBG_BIT_PRINT(r8, P0PA24);
DBG_BIT_PRINT(r8, P0REG);
#undef DBG_BIT_PRINT
DPRINTF((TEXT("\n")));
DPRINTF((TEXT("PCC0 Card Status Change Register\n")));
r8 = _reg_read_1(HD64461_PCC0CSCR_REG8);
bitdisp(r8);
#define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0CSCR_##m, #m)
DBG_BIT_PRINT(r8, P0SCDI);
DBG_BIT_PRINT(r8, P0IREQ);
DBG_BIT_PRINT(r8, P0SC);
DBG_BIT_PRINT(r8, P0CDC);
DBG_BIT_PRINT(r8, P0RC);
DBG_BIT_PRINT(r8, P0BW);
DBG_BIT_PRINT(r8, P0BD);
#undef DBG_BIT_PRINT
DPRINTF((TEXT("\n")));
DPRINTF((TEXT("PCC0 Card Status Change Interrupt Enable Register\n")));
r8 = _reg_read_1(HD64461_PCC0CSCIER_REG8);
bitdisp(r8);
#define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0CSCIER_##m, #m)
DBG_BIT_PRINT(r8, P0CRE);
DBG_BIT_PRINT(r8, P0SCE);
DBG_BIT_PRINT(r8, P0CDE);
DBG_BIT_PRINT(r8, P0RE);
DBG_BIT_PRINT(r8, P0BWE);
DBG_BIT_PRINT(r8, P0BDE);
#undef DBG_BIT_PRINT
DPRINTF((TEXT("\ninterrupt type: ")));
switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) {
case HD64461_PCC0CSCIER_P0IREQE_NONE:
DPRINTF((TEXT("none\n")));
break;
case HD64461_PCC0CSCIER_P0IREQE_LEVEL:
DPRINTF((TEXT("level\n")));
break;
case HD64461_PCC0CSCIER_P0IREQE_FEDGE:
DPRINTF((TEXT("falling edge\n")));
break;
case HD64461_PCC0CSCIER_P0IREQE_REDGE:
DPRINTF((TEXT("rising edge\n")));
break;
}
DPRINTF((TEXT("PCC0 Software Control Register\n")));
r8 = _reg_read_1(HD64461_PCC0SCR_REG8);
bitdisp(r8);
#define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC0SCR_##m, #m)
DBG_BIT_PRINT(r8, P0VCC1);
DBG_BIT_PRINT(r8, P0SWP);
#undef DBG_BIT_PRINT
DPRINTF((TEXT("\n")));
// PCC1
DPRINTF((TEXT("[PCC1 memory card only (SH3 Area 5)]\n")));
DPRINTF((TEXT("PCC1 Interface Status Register\n")));
r8 = _reg_read_1(HD64461_PCC1ISR_REG8);
bitdisp(r8);
#define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1ISR_##m, #m)
DBG_BIT_PRINT(r8, P1READY);
DBG_BIT_PRINT(r8, P1MWP);
DBG_BIT_PRINT(r8, P1VS2);
DBG_BIT_PRINT(r8, P1VS1);
DBG_BIT_PRINT(r8, P1CD2);
DBG_BIT_PRINT(r8, P1CD1);
DBG_BIT_PRINT(r8, P1BVD2);
DBG_BIT_PRINT(r8, P1BVD1);
#undef DBG_BIT_PRINT
DPRINTF((TEXT("\n")));
DPRINTF((TEXT("PCC1 General Contorol Register\n")));
r8 = _reg_read_1(HD64461_PCC1GCR_REG8);
bitdisp(r8);
#define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1GCR_##m, #m)
DBG_BIT_PRINT(r8, P1DRVE);
DBG_BIT_PRINT(r8, P1PCCR);
DBG_BIT_PRINT(r8, P1VCC0);
DBG_BIT_PRINT(r8, P1MMOD);
DBG_BIT_PRINT(r8, P1PA25);
DBG_BIT_PRINT(r8, P1PA24);
DBG_BIT_PRINT(r8, P1REG);
#undef DBG_BIT_PRINT
DPRINTF((TEXT("\n")));
DPRINTF((TEXT("PCC1 Card Status Change Register\n")));
r8 = _reg_read_1(HD64461_PCC1CSCR_REG8);
bitdisp(r8);
#define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1CSCR_##m, #m)
DBG_BIT_PRINT(r8, P1SCDI);
DBG_BIT_PRINT(r8, P1CDC);
DBG_BIT_PRINT(r8, P1RC);
DBG_BIT_PRINT(r8, P1BW);
DBG_BIT_PRINT(r8, P1BD);
#undef DBG_BIT_PRINT
DPRINTF((TEXT("\n")));
DPRINTF((TEXT("PCC1 Card Status Change Interrupt Enable Register\n")));
r8 = _reg_read_1(HD64461_PCC1CSCIER_REG8);
bitdisp(r8);
#define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1CSCIER_##m, #m)
DBG_BIT_PRINT(r8, P1CRE);
DBG_BIT_PRINT(r8, P1CDE);
DBG_BIT_PRINT(r8, P1RE);
DBG_BIT_PRINT(r8, P1BWE);
DBG_BIT_PRINT(r8, P1BDE);
#undef DBG_BIT_PRINT
DPRINTF((TEXT("\n")));
DPRINTF((TEXT("PCC1 Software Control Register\n")));
r8 = _reg_read_1(HD64461_PCC1SCR_REG8);
bitdisp(r8);
#define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCC1SCR_##m, #m)
DBG_BIT_PRINT(r8, P1VCC1);
DBG_BIT_PRINT(r8, P1SWP);
#undef DBG_BIT_PRINT
DPRINTF((TEXT("\n")));
// General Control
DPRINTF((TEXT("[General Control]\n")));
DPRINTF((TEXT("PCC0 Output pins Control Register\n")));
r8 = _reg_read_1(HD64461_PCCP0OCR_REG8);
bitdisp(r8);
#define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCP0OCR_##m, #m)
DBG_BIT_PRINT(r8, P0DEPLUP);
DBG_BIT_PRINT(r8, P0AEPLUP);
#undef DBG_BIT_PRINT
DPRINTF((TEXT("\n")));
DPRINTF((TEXT("PCC1 Output pins Control Register\n")));
r8 = _reg_read_1(HD64461_PCCP1OCR_REG8);
bitdisp(r8);
#define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCP1OCR_##m, #m)
DBG_BIT_PRINT(r8, P1RST8MA);
DBG_BIT_PRINT(r8, P1RST4MA);
DBG_BIT_PRINT(r8, P1RAS8MA);
DBG_BIT_PRINT(r8, P1RAS4MA);
#undef DBG_BIT_PRINT
DPRINTF((TEXT("\n")));
DPRINTF((TEXT("PC Card General Control Register\n")));
r8 = _reg_read_1(HD64461_PCCPGCR_REG8);
bitdisp(r8);
#define DBG_BIT_PRINT(r, m) _dbg_bit_print(r, HD64461_PCCPGCR_##m, #m)
DBG_BIT_PRINT(r8, PSSDIR);
DBG_BIT_PRINT(r8, PSSRDWR);
#undef DBG_BIT_PRINT
DPRINTF((TEXT("\n")));
// GPIO
#define GPIO_DUMP(x) \
bitdisp(_reg_read_2(HD64461_GPA##x##R_REG16)); \
bitdisp(_reg_read_2(HD64461_GPB##x##R_REG16)); \
bitdisp(_reg_read_2(HD64461_GPC##x##R_REG16)); \
bitdisp(_reg_read_2(HD64461_GPD##x##R_REG16))
DPRINTF((TEXT("GPIO Port Control Register\n")));
GPIO_DUMP(C);
DPRINTF((TEXT("GPIO Port Data Register\n")));
GPIO_DUMP(D);
DPRINTF((TEXT("GPIO Port Interrupt Control Register\n")));
GPIO_DUMP(IC);
DPRINTF((TEXT("GPIO Port Interrupt Status Register\n")));
GPIO_DUMP(IS);
}
