/*---------------------------------------------------------------------------+
* program_ecc.
*---------------------------------------------------------------------------*/
static void program_ecc(unsigned long start_address, unsigned long num_bytes)
{
u32 val;
char str[] = "ECC generation -";
#if defined(CONFIG_PRAM)
u32 *magicPtr;
u32 magic;
if ((mfspr(dbcr0) & 0x80000000) == 0) {
/* only if no external debugger is alive!
* Check whether vxWorks is using EDR logging, if yes zero
* also PostMortem and user reserved memory
*/
magicPtr = (u32 *)(start_address + num_bytes -
(CONFIG_PRAM*1024) + sizeof(u32));
magic = in_be32(magicPtr);
debug("%s: CONFIG_PRAM %d kB magic 0x%x 0x%p\n",
__FUNCTION__, CONFIG_PRAM,
magicPtr, magic);
if (magic == 0xbeefbabe) {
printf("%s: preserving at %p\n", __FUNCTION__, magicPtr);
num_bytes -= (CONFIG_PRAM*1024) - PM_RESERVED_MEM;
}
}
#endif
sync();
eieio();
puts(str);
/* ECC bit set method for cached memory */
/* Fast method, no noticeable delay */
dcbz_area(start_address, num_bytes);
dflush();
blank_string(strlen(str));
/* Clear error status */
mfsdram(DDR0_00, val);
mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
/*
* Clear possible ECC errors
* If not done, then we could get an interrupt later on when
* exceptions are enabled.
*/
mtspr(mcsr, mfspr(mcsr));
/* Set 'int_mask' parameter to functionnal value */
mfsdram(DDR0_01, val);
mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) |
DDR0_01_INT_MASK_ALL_OFF));
return;
}
int cal_main(int argc, char **argv)
{
struct tm *local_time;
struct tm zero_tm;
time_t now;
unsigned month, year, flags, i;
char *month_names[12];
char day_headings[28]; /* 28 for julian, 21 for nonjulian */
char buf[40];
flags = getopt32(argv, "jy");
/* This sets julian = flags & 1: */
option_mask32 &= 1;
month = 0;
argv += optind;
argc -= optind;
if (argc > 2) {
bb_show_usage();
}
if (!argc) {
time(&now);
local_time = localtime(&now);
year = local_time->tm_year + 1900;
if (!(flags & 2)) { /* no -y */
month = local_time->tm_mon + 1;
}
} else {
if (argc == 2) {
month = xatou_range(*argv++, 1, 12);
}
year = xatou_range(*argv, 1, 9999);
}
blank_string(day_headings, sizeof(day_headings) - 7 + 7*julian);
i = 0;
do {
zero_tm.tm_mon = i;
strftime(buf, sizeof(buf), "%B", &zero_tm);
month_names[i] = xstrdup(buf);
if (i < 7) {
zero_tm.tm_wday = i;
strftime(buf, sizeof(buf), "%a", &zero_tm);
strncpy(day_headings + i * (3+julian) + julian, buf, 2);
}
} while (++i < 12);
if (month) {
unsigned row, len, days[MAXDAYS];
unsigned *dp = days;
char lineout[30];
day_array(month, year, dp);
len = sprintf(lineout, "%s %d", month_names[month - 1], year);
printf("%*s%s\n%s\n",
((7*julian + WEEK_LEN) - len) / 2, "",
lineout, day_headings);
for (row = 0; row < 6; row++) {
build_row(lineout, dp)[0] = '\0';
dp += 7;
trim_trailing_spaces_and_print(lineout);
}
} else {
unsigned row, which_cal, week_len, days[12][MAXDAYS];
unsigned *dp;
char lineout[80];
sprintf(lineout, "%d", year);
center(lineout,
(WEEK_LEN * 3 + HEAD_SEP * 2)
+ julian * (J_WEEK_LEN * 2 + HEAD_SEP
- (WEEK_LEN * 3 + HEAD_SEP * 2)),
0);
puts("\n"); /* two \n's */
for (i = 0; i < 12; i++) {
day_array(i + 1, year, days[i]);
}
blank_string(lineout, sizeof(lineout));
week_len = WEEK_LEN + julian * (J_WEEK_LEN - WEEK_LEN);
for (month = 0; month < 12; month += 3-julian) {
center(month_names[month], week_len, HEAD_SEP);
if (!julian) {
center(month_names[month + 1], week_len, HEAD_SEP);
}
center(month_names[month + 2 - julian], week_len, 0);
printf("\n%s%*s%s", day_headings, HEAD_SEP, "", day_headings);
if (!julian) {
printf("%*s%s", HEAD_SEP, "", day_headings);
}
bb_putchar('\n');
for (row = 0; row < (6*7); row += 7) {
for (which_cal = 0; which_cal < 3-julian; which_cal++) {
dp = days[month + which_cal] + row;
build_row(lineout + which_cal * (week_len + 2), dp);
}
/* blank_string took care of nul termination. */
trim_trailing_spaces_and_print(lineout);
}
}
}
fflush_stdout_and_exit(EXIT_SUCCESS);
}
int last_stage_init(void)
{
unsigned int k;
unsigned int fpga;
int failed = 0;
char str_phys[] = "Setup PHYs -";
char str_serdes[] = "Start SERDES blocks";
char str_channels[] = "Start FPGA channels";
char str_locks[] = "Verify SERDES locks";
char str_hicb[] = "Verify HICB status";
char str_status[] = "Verify PHY status -";
char slash[] = "\\|/-\\|/-";
print_fpga_info(0);
print_fpga_info(1);
/* setup Gbit PHYs */
puts("TRANS: ");
puts(str_phys);
miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
bb_miiphy_read, bb_miiphy_write);
for (k = 0; k < 32; ++k) {
configure_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k);
putc('\b');
putc(slash[k % 8]);
}
miiphy_register(CONFIG_SYS_GBIT_MII1_BUSNAME,
bb_miiphy_read, bb_miiphy_write);
for (k = 0; k < 32; ++k) {
configure_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k);
putc('\b');
putc(slash[k % 8]);
}
blank_string(strlen(str_phys));
/* take fpga serdes blocks out of reset */
puts(str_serdes);
udelay(500000);
FPGA_SET_REG(0, quad_serdes_reset, 0);
FPGA_SET_REG(1, quad_serdes_reset, 0);
blank_string(strlen(str_serdes));
/* take channels out of reset */
puts(str_channels);
udelay(500000);
for (fpga = 0; fpga < 2; ++fpga) {
for (k = 0; k < 32; ++k)
FPGA_SET_REG(fpga, ch[k].config_int, 0);
}
blank_string(strlen(str_channels));
/* verify channels serdes lock */
puts(str_locks);
udelay(500000);
for (fpga = 0; fpga < 2; ++fpga) {
for (k = 0; k < 32; ++k) {
u16 status;
FPGA_GET_REG(k, ch[k].status_int, &status);
if (!(status & (1 << 4))) {
failed = 1;
printf("fpga %d channel %d: no serdes lock\n",
fpga, k);
}
/* reset events */
FPGA_SET_REG(fpga, ch[k].status_int, 0);
}
}
blank_string(strlen(str_locks));
/* verify hicb_status */
puts(str_hicb);
for (fpga = 0; fpga < 2; ++fpga) {
for (k = 0; k < 32; ++k) {
u16 status;
FPGA_GET_REG(k, hicb_ch[k].status_int, &status);
if (status)
printf("fpga %d hicb %d: hicb status %04x\n",
fpga, k, status);
/* reset events */
FPGA_SET_REG(fpga, hicb_ch[k].status_int, 0);
}
}
blank_string(strlen(str_hicb));
/* verify phy status */
puts(str_status);
for (k = 0; k < 32; ++k) {
if (verify_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k)) {
printf("verify baseboard phy %d failed\n", k);
failed = 1;
}
putc('\b');
putc(slash[k % 8]);
}
for (k = 0; k < 32; ++k) {
if (verify_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k)) {
printf("verify extensionboard phy %d failed\n", k);
failed = 1;
}
putc('\b');
putc(slash[k % 8]);
}
blank_string(strlen(str_status));
printf("Starting 64 channels %s\n", failed ? "failed" : "ok");
return 0;
}
static void program_ecc_addr(unsigned long start_address,
unsigned long num_bytes,
unsigned long tlb_word2_i_value)
{
unsigned long current_address;
unsigned long end_address;
unsigned long address_increment;
unsigned long mcopt1;
char str[] = "ECC generation -";
char slash[] = "\\|/-\\|/-";
int loop = 0;
int loopi = 0;
current_address = start_address;
mfsdram(SDRAM_MCOPT1, mcopt1);
if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
mtsdram(SDRAM_MCOPT1,
(mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
sync();
eieio();
wait_ddr_idle();
puts(str);
#ifdef CONFIG_440
if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
#endif
/* ECC bit set method for non-cached memory */
if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
address_increment = 4;
else
address_increment = SDRAM_DATA_ALT_WIDTH;
end_address = current_address + num_bytes;
while (current_address < end_address) {
*((unsigned long *)current_address) = 0;
current_address += address_increment;
if ((loop++ % (2 << 20)) == 0) {
putc('\b');
putc(slash[loopi++ % 8]);
}
}
#ifdef CONFIG_440
} else {
/* ECC bit set method for cached memory */
dcbz_area(start_address, num_bytes);
/* Write modified dcache lines back to memory */
clean_dcache_range(start_address, start_address + num_bytes);
}
#endif /* CONFIG_440 */
blank_string(strlen(str));
sync();
eieio();
wait_ddr_idle();
/* clear ECC error repoting registers */
mtsdram(SDRAM_ECCES, 0xffffffff);
mtdcr(0x4c, 0xffffffff);
mtsdram(SDRAM_MCOPT1,
(mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
sync();
eieio();
wait_ddr_idle();
}
}
static void program_ecc(u32 start_address,
u32 num_bytes,
u32 tlb_word2_i_value)
{
u32 current_address;
u32 end_address;
u32 address_increment;
u32 val;
char str[] = "ECC generation -";
char slash[] = "\\|/-\\|/-";
int loop = 0;
int loopi = 0;
current_address = start_address;
sync();
eieio();
wait_ddr_idle();
if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
/* ECC bit set method for non-cached memory */
address_increment = 4;
end_address = current_address + num_bytes;
puts(str);
while (current_address < end_address) {
*((u32 *)current_address) = 0x00000000;
current_address += address_increment;
if ((loop++ % (2 << 20)) == 0) {
putc('\b');
putc(slash[loopi++ % 8]);
}
}
blank_string(strlen(str));
} else {
/* ECC bit set method for cached memory */
#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
/*
* Some boards (like lwmon5) need to preserve the memory
* content upon ECC generation (for the log-buffer).
* Therefore we don't fill the memory with a pattern or
* just zero it, but write the same values back that are
* already in the memory cells.
*/
address_increment = CFG_CACHELINE_SIZE;
end_address = current_address + num_bytes;
current_address = start_address;
while (current_address < end_address) {
/*
* TODO: Th following sequence doesn't work correctly.
* Just invalidating and flushing the cache doesn't
* seem to trigger the re-write of the memory.
*/
ppcDcbi(current_address);
ppcDcbf(current_address);
current_address += CFG_CACHELINE_SIZE;
}
#else
dcbz_area(start_address, num_bytes);
dflush();
#endif
}
sync();
eieio();
wait_ddr_idle();
/* Clear error status */
mfsdram(DDR0_00, val);
mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
/* Set 'int_mask' parameter to functionnal value */
mfsdram(DDR0_01, val);
mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF));
sync();
eieio();
wait_ddr_idle();
}
