ulong bootstage_mark_name(enum bootstage_id id, const char *name)
{
int flags = 0;
if (id == BOOTSTAGE_ID_ALLOC)
flags = BOOTSTAGEF_ALLOC;
return bootstage_add_record(id, name, flags, timer_get_boot_us());
}
int bootstage_init(bool first)
{
struct bootstage_data *data;
int size = sizeof(struct bootstage_data);
gd->bootstage = (struct bootstage_data *)malloc(size);
if (!gd->bootstage)
return -ENOMEM;
data = gd->bootstage;
memset(data, '\0', size);
if (first) {
data->next_id = BOOTSTAGE_ID_USER;
bootstage_add_record(BOOTSTAGE_ID_AWAKE, "reset", 0, 0);
}
return 0;
}
ulong bootstage_error(enum bootstage_id id)
{
return bootstage_add_record(id, NULL, BOOTSTAGEF_ERROR,
timer_get_boot_us());
}
ulong bootstage_mark(enum bootstage_id id)
{
return bootstage_add_record(id, NULL, 0, timer_get_boot_us());
}
int board_init(void)
{
struct fdt_memory mem_config;
/* Record the time we spent before SPL */
bootstage_add_record(BOOTSTAGE_ID_START_SPL, "spl_start", 0,
CONFIG_SPL_TIME_US);
bootstage_mark_name(BOOTSTAGE_ID_BOARD_INIT, "board_init");
if (fdtdec_decode_memory(gd->fdt_blob, &mem_config)) {
debug("%s: Failed to decode memory\n", __func__);
return -1;
}
gd->bd->bi_boot_params = mem_config.start + 0x100UL;
#ifdef CONFIG_OF_CONTROL
gd->bd->bi_arch_number = fdtdec_get_config_int(gd->fdt_blob,
"machine-arch-id", -1);
if (gd->bd->bi_arch_number == -1U)
debug("Warning: No /config/machine-arch-id defined in fdt\n");
#endif
#ifdef CONFIG_EXYNOS_SPI
spi_init();
#endif
if (board_i2c_arb_init(gd->fdt_blob))
return -1;
board_i2c_init(gd->fdt_blob);
#ifdef CONFIG_TPS65090_POWER
tps65090_init();
/*
* If we just reset, disable the backlight and lcd fets before
* [re-]initializing the lcd. This ensures we are always in the same
* state during lcd init. We've seen some oddities with these fets, so
* this removes a bit of uncertainty.
*/
if (board_is_processor_reset()) {
tps65090_fet_disable(1);
tps65090_fet_disable(6);
}
#endif
exynos_lcd_check_next_stage(gd->fdt_blob, 0);
if (max77686_enable_32khz_cp()) {
debug("%s: Failed to enable max77686 32khz coprocessor clock\n",
__func__);
return -1;
}
#if defined CONFIG_EXYNOS_CPUFREQ
if (exynos5250_cpufreq_init(gd->fdt_blob)) {
debug("%s: Failed to init CPU frequency scaling\n", __func__);
return -1;
}
#endif
#if defined CONFIG_EXYNOS_TMU
if (tmu_init(gd->fdt_blob)) {
debug("%s: Failed to init TMU\n", __func__);
return -1;
}
#endif
/* Clock Gating all the unused IP's to save power */
clock_gate();
/* Disable USB3.0 PLL to save 250mW of power */
disable_usb30_pll();
if (board_init_mkbp_devices(gd->fdt_blob))
return -1;
board_configure_analogix();
board_enable_audio_codec();
exynos_lcd_check_next_stage(gd->fdt_blob, 0);
bootstage_mark_name(BOOTSTAGE_ID_BOARD_INIT_DONE, "board_init_done");
return 0;
}
