int s5p_mfc_power_off(struct s5p_mfc_dev *dev)
{
#if defined(CONFIG_SOC_EXYNOS5422)
bts_initialize("pd-mfc", false);
#endif
atomic_set(&dev->pm.power, 0);
return pm_runtime_put_sync(dev->pm.device);
}
int s5p_mfc_power_on(struct s5p_mfc_dev *dev)
{
int ret;
atomic_set(&dev->pm.power, 1);
ret = pm_runtime_get_sync(dev->pm.device);
#if defined(CONFIG_SOC_EXYNOS5422)
bts_initialize("pd-mfc", true);
#endif
return ret;
}
int s5p_mfc_power_on(struct s5p_mfc_dev *dev)
{
int ret;
#if defined(CONFIG_SOC_EXYNOS5430)
struct clk *clk_child = NULL;
struct clk *clk_parent = NULL;
#endif
atomic_set(&dev->pm.power, 1);
MFC_TRACE_DEV("++ Power on\n");
ret = pm_runtime_get_sync(dev->pm.device);
#if defined(CONFIG_SOC_EXYNOS5422)
bts_initialize("pd-mfc", true);
#endif
#if defined(CONFIG_SOC_EXYNOS5430)
if (dev->id == 0) {
clk_child = clk_get(dev->device, "mout_mphy_pll");
if (IS_ERR(clk_child)) {
pr_err("failed to get %s clock\n", __clk_get_name(clk_child));
return PTR_ERR(clk_child);
}
clk_parent = clk_get(dev->device, "fout_mphy_pll");
if (IS_ERR(clk_parent)) {
clk_put(clk_child);
pr_err("failed to get %s clock\n", __clk_get_name(clk_parent));
return PTR_ERR(clk_parent);
}
/* 1. Enable MPHY_PLL */
clk_prepare_enable(clk_parent);
/* 2. Set parent as Fout_mphy */
clk_set_parent(clk_child, clk_parent);
}
#endif
MFC_TRACE_DEV("-- Power on: ret(%d)\n", ret);
return ret;
}
int s5p_mfc_power_off(struct s5p_mfc_dev *dev)
{
#if defined(CONFIG_SOC_EXYNOS5430) || defined(CONFIG_SOC_EXYNOS5433)
struct clk *clk_child = NULL;
struct clk *clk_parent = NULL;
#endif
#if defined(CONFIG_SOC_EXYNOS5430)
struct clk *clk_fout_mphy_pll = NULL;
#endif
#if defined(CONFIG_SOC_EXYNOS5433)
struct clk *clk_old_parent = NULL;
#endif
int ret;
MFC_TRACE_DEV("++ Power off\n");
#if defined(CONFIG_SOC_EXYNOS5422)
bts_initialize("pd-mfc", false);
#endif
#if defined(CONFIG_SOC_EXYNOS5430)
if (dev->id == 0) {
clk_fout_mphy_pll = clk_get(dev->device, "fout_mphy_pll");
if (IS_ERR(clk_fout_mphy_pll)) {
pr_err("failed to get %s clock\n", __clk_get_name(clk_fout_mphy_pll));
return PTR_ERR(clk_fout_mphy_pll);
}
clk_child = clk_get(dev->device, "mout_mphy_pll");
if (IS_ERR(clk_child)) {
clk_put(clk_fout_mphy_pll);
pr_err("failed to get %s clock\n", __clk_get_name(clk_child));
return PTR_ERR(clk_child);
}
clk_parent = clk_get(dev->device, "fin_pll");
if (IS_ERR(clk_parent)) {
clk_put(clk_child);
clk_put(clk_fout_mphy_pll);
pr_err("failed to get %s clock\n", __clk_get_name(clk_parent));
return PTR_ERR(clk_parent);
}
/* 1. Set parent as OSC */
clk_set_parent(clk_child, clk_parent);
/* 2. Disable MPHY_PLL */
clk_disable_unprepare(clk_fout_mphy_pll);
}
#endif
#if defined(CONFIG_SOC_EXYNOS5433)
clk_old_parent = clk_get(dev->device, "aclk_mfc_400");
if (IS_ERR(clk_old_parent)) {
pr_err("failed to get %s clock\n", __clk_get_name(clk_old_parent));
return PTR_ERR(clk_old_parent);
}
clk_child = clk_get(dev->device, "mout_aclk_mfc_400_user");
if (IS_ERR(clk_child)) {
clk_put(clk_old_parent);
pr_err("failed to get %s clock\n", __clk_get_name(clk_child));
return PTR_ERR(clk_child);
}
clk_parent = clk_get(dev->device, "oscclk");
if (IS_ERR(clk_parent)) {
clk_put(clk_child);
clk_put(clk_old_parent);
pr_err("failed to get %s clock\n", __clk_get_name(clk_parent));
return PTR_ERR(clk_parent);
}
/* before set mux register, all source clock have to enabled */
clk_prepare_enable(clk_parent);
if (clk_set_parent(clk_child, clk_parent)) {
pr_err("Unable to set parent %s of clock %s \n",
__clk_get_name(clk_parent), __clk_get_name(clk_child));
}
clk_disable_unprepare(clk_parent);
clk_disable_unprepare(clk_old_parent);
clk_put(clk_child);
clk_put(clk_parent);
clk_put(clk_old_parent);
/* expected mfc related ref clock value be set 0 */
#endif
atomic_set(&dev->pm.power, 0);
ret = pm_runtime_put_sync(dev->pm.device);
MFC_TRACE_DEV("-- Power off: ret(%d)\n", ret);
return ret;
}
