__stdcall static void
hal_writeport_buf_ushort(uint16_t *port, uint16_t *val, uint32_t cnt)
{
bus_space_write_multi_2(NDIS_BUS_SPACE_IO, 0x0,
(bus_size_t)port, val, cnt);
return;
}
void
ata_bs_wm_2(void *t, bus_space_handle_t h, bus_size_t o,
const u_int16_t *d, bus_size_t c)
{
struct ata_avila_softc *sc = t;
enable_16(sc);
bus_space_write_multi_2(sc->sc_iot, h, o, d, c);
disable_16(sc);
}
static void
cambria_bs_wm_2(void *t, bus_space_handle_t h, bus_size_t o,
const u_int16_t *d, bus_size_t c)
{
struct expbus_softc *exp = t;
struct ixp425_softc *sc = exp->sc;
EXP_LOCK(exp);
enable_16(sc, exp->csoff);
bus_space_write_multi_2(sc->sc_iot, h, o, d, c);
disable_16(sc, exp->csoff);
EXP_UNLOCK(exp);
}
u_char
ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte)
{
struct ppc_data *ppc = DEVTOSOFTC(ppcdev);
switch (iop) {
case PPB_OUTSB_EPP:
bus_space_write_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt);
break;
case PPB_OUTSW_EPP:
bus_space_write_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
break;
case PPB_OUTSL_EPP:
bus_space_write_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
break;
case PPB_INSB_EPP:
bus_space_read_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt);
break;
case PPB_INSW_EPP:
bus_space_read_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
break;
case PPB_INSL_EPP:
bus_space_read_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
break;
case PPB_RDTR:
return (r_dtr(ppc));
case PPB_RSTR:
return (r_str(ppc));
case PPB_RCTR:
return (r_ctr(ppc));
case PPB_REPP_A:
return (r_epp_A(ppc));
case PPB_REPP_D:
return (r_epp_D(ppc));
case PPB_RECR:
return (r_ecr(ppc));
case PPB_RFIFO:
return (r_fifo(ppc));
case PPB_WDTR:
w_dtr(ppc, byte);
break;
case PPB_WSTR:
w_str(ppc, byte);
break;
case PPB_WCTR:
w_ctr(ppc, byte);
break;
case PPB_WEPP_A:
w_epp_A(ppc, byte);
break;
case PPB_WEPP_D:
w_epp_D(ppc, byte);
break;
case PPB_WECR:
w_ecr(ppc, byte);
break;
case PPB_WFIFO:
w_fifo(ppc, byte);
break;
default:
panic("%s: unknown I/O operation", __func__);
break;
}
return (0); /* not significative */
}
static int
oak_pdma_out(struct ncr5380_softc *ncr_sc, int phase, int datalen,
u_char *data)
{
struct oak_softc *sc = (void *)ncr_sc;
bus_space_tag_t pdmat = sc->sc_pdmat;
bus_space_handle_t pdmah = sc->sc_pdmah;
int i, s, icmd, resid;
s = splbio();
icmd = NCR5380_READ(ncr_sc, sci_icmd) & SCI_ICMD_RMASK;
NCR5380_WRITE(ncr_sc, sci_icmd, icmd | SCI_ICMD_DATA);
NCR5380_WRITE(ncr_sc, sci_mode,
NCR5380_READ(ncr_sc, sci_mode) | SCI_MODE_DMA);
NCR5380_WRITE(ncr_sc, sci_dma_send, 0);
resid = datalen;
if (oak_ready(ncr_sc) == 0)
goto interrupt;
if (resid > OAK_TSIZE_OUT) {
/*
* Because of the chips DMA prefetch, phase changes
* etc, won't be detected until we have written at
* least one byte more. We pre-write 4 bytes so
* subsequent transfers will be aligned to a 4 byte
* boundary. Assuming disconects will only occur on
* block boundaries, we then correct for the pre-write
* when and if we get a phase change. If the chip had
* DMA byte counting hardware, the assumption would not
* be necessary.
*/
KASSERT(BUS_SPACE_ALIGNED_POINTER(data, u_int16_t));
bus_space_write_multi_2(pdmat, pdmah, OAK_PDMA_WRITE,
(u_int16_t *)data, 4/2);
data += 4;
resid -= 4;
for (; resid >= OAK_TSIZE_OUT; resid -= OAK_TSIZE_OUT) {
if (oak_ready(ncr_sc) == 0) {
resid += 4; /* Overshot */
goto interrupt;
}
bus_space_write_multi_2(pdmat, pdmah, OAK_PDMA_WRITE,
(u_int16_t *)data, OAK_TSIZE_OUT/2);
data += OAK_TSIZE_OUT;
}
if (oak_ready(ncr_sc) == 0) {
resid += 4; /* Overshot */
goto interrupt;
}
}
if (resid) {
bus_space_write_multi_2(pdmat, pdmah, OAK_PDMA_WRITE,
(u_int16_t *)data, resid/2);
resid = 0;
}
for (i = TIMEOUT; i > 0; i--) {
if ((NCR5380_READ(ncr_sc, sci_csr)
& (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH))
!= SCI_CSR_DREQ)
break;
}
if (i != 0)
bus_space_write_2(pdmat, pdmah, OAK_PDMA_WRITE, 0);
else
printf("%s: timeout waiting for final SCI_DSR_DREQ.\n",
ncr_sc->sc_dev.dv_xname);
oak_wait_not_req(ncr_sc);
interrupt:
SCI_CLR_INTR(ncr_sc);
NCR5380_WRITE(ncr_sc, sci_mode,
NCR5380_READ(ncr_sc, sci_mode) & ~SCI_MODE_DMA);
NCR5380_WRITE(ncr_sc, sci_icmd, icmd);
splx(s);
return(datalen - resid);
}
void
bs_through_bs_wm_2(bus_space_tag_t t, bus_space_handle_t bsh,
bus_size_t offset, const u_int16_t *addr, bus_size_t count)
{
bus_space_write_multi_2(t->bs_base, bsh, offset, addr, count);
}