void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat) { unsigned reg; cadence_qspi_apb_controller_disable(plat->regbase); /* Configure the device size and address bytes */ reg = readl(plat->regbase + CQSPI_REG_SIZE); /* Clear the previous value */ reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB); reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB); reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB); reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB); writel(reg, plat->regbase + CQSPI_REG_SIZE); /* Configure the remap address register, no remap */ writel(0, plat->regbase + CQSPI_REG_REMAP); /* Indirect mode configurations */ writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION); /* Disable all interrupts */ writel(0, plat->regbase + CQSPI_REG_IRQMASK); cadence_qspi_apb_controller_enable(plat->regbase); }
void cadence_qspi_apb_chipselect(void *reg_base, unsigned int chip_select, unsigned int decoder_enable) { unsigned int reg; cadence_qspi_apb_controller_disable(reg_base); debug("%s : chipselect %d decode %d\n", __func__, chip_select, decoder_enable); reg = readl(reg_base + CQSPI_REG_CONFIG); /* docoder */ if (decoder_enable) { reg |= CQSPI_REG_CONFIG_DECODE; } else { reg &= ~CQSPI_REG_CONFIG_DECODE; /* Convert CS if without decoder. * CS0 to 4b'1110 * CS1 to 4b'1101 * CS2 to 4b'1011 * CS3 to 4b'0111 */ chip_select = 0xF & ~(1 << chip_select); } reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK << CQSPI_REG_CONFIG_CHIPSELECT_LSB); reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK) << CQSPI_REG_CONFIG_CHIPSELECT_LSB; writel(reg, reg_base + CQSPI_REG_CONFIG); cadence_qspi_apb_controller_enable(reg_base); }
void cadence_qspi_apb_config_baudrate_div(void *reg_base, unsigned int ref_clk_hz, unsigned int sclk_hz) { unsigned int reg; unsigned int div; cadence_qspi_apb_controller_disable(reg_base); reg = readl(reg_base + CQSPI_REG_CONFIG); reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); /* * The baud_div field in the config reg is 4 bits, and the ref clock is * divided by 2 * (baud_div + 1). Round up the divider to ensure the * SPI clock rate is less than or equal to the requested clock rate. */ div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1; /* ensure the baud rate doesn't exceed the max value */ if (div > CQSPI_REG_CONFIG_BAUD_MASK) div = CQSPI_REG_CONFIG_BAUD_MASK; debug("%s: ref_clk %dHz sclk %dHz Div 0x%x, actual %dHz\n", __func__, ref_clk_hz, sclk_hz, div, ref_clk_hz / (2 * (div + 1))); reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB); writel(reg, reg_base + CQSPI_REG_CONFIG); cadence_qspi_apb_controller_enable(reg_base); }
void cadence_qspi_switch_cs(struct struct_cqspi *cadence_qspi, unsigned int cs) { unsigned int reg; struct platform_device *pdev = cadence_qspi->pdev; struct cqspi_platform_data *pdata = pdev->dev.platform_data; struct cqspi_flash_pdata *f_pdata = &(pdata->f_pdata[cs]); void __iomem *iobase = cadence_qspi->iobase; pr_debug("%s\n", __func__); cadence_qspi_apb_controller_disable(iobase); /* Configure page size and block size. */ reg = CQSPI_READL(iobase + CQSPI_REG_SIZE); /* clear the previous value */ reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB); reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB); reg |= (f_pdata->page_size << CQSPI_REG_SIZE_PAGE_LSB); reg |= (f_pdata->block_size << CQSPI_REG_SIZE_BLOCK_LSB); CQSPI_WRITEL(reg, iobase + CQSPI_REG_SIZE); /* configure the chip select */ cadence_qspi_apb_chipselect (iobase, cs, pdata->ext_decoder); cadence_qspi_apb_controller_enable(iobase); return; }
static int cadence_spi_set_speed(struct udevice *bus, uint hz) { struct cadence_spi_platdata *plat = bus->platdata; struct cadence_spi_priv *priv = dev_get_priv(bus); int err; /* Disable QSPI */ cadence_qspi_apb_controller_disable(priv->regbase); cadence_spi_write_speed(bus, hz); /* Calibration required for different SCLK speed or chip select */ if (priv->qspi_calibrated_hz != plat->max_hz || priv->qspi_calibrated_cs != spi_chip_select(bus)) { err = spi_calibration(bus); if (err) return err; } /* Enable QSPI */ cadence_qspi_apb_controller_enable(priv->regbase); debug("%s: speed=%d\n", __func__, hz); return 0; }
void cadence_qspi_apb_controller_init(struct struct_cqspi *cadence_qspi) { cadence_qspi_apb_controller_disable(cadence_qspi->iobase); /* Configure the remap address register, no remap */ CQSPI_WRITEL(0, cadence_qspi->iobase + CQSPI_REG_REMAP); /* Disable all interrupts. */ CQSPI_WRITEL(0, cadence_qspi->iobase + CQSPI_REG_IRQMASK); cadence_qspi_apb_controller_enable(cadence_qspi->iobase); return; }
static int cadence_spi_set_mode(struct udevice *bus, uint mode) { struct cadence_spi_priv *priv = dev_get_priv(bus); /* Disable QSPI */ cadence_qspi_apb_controller_disable(priv->regbase); /* Set SPI mode */ cadence_qspi_apb_set_clk_mode(priv->regbase, mode); /* Enable QSPI */ cadence_qspi_apb_controller_enable(priv->regbase); return 0; }
void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode) { unsigned int reg; cadence_qspi_apb_controller_disable(reg_base); reg = readl(reg_base + CQSPI_REG_CONFIG); reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA); if (mode & SPI_CPOL) reg |= CQSPI_REG_CONFIG_CLK_POL; if (mode & SPI_CPHA) reg |= CQSPI_REG_CONFIG_CLK_PHA; writel(reg, reg_base + CQSPI_REG_CONFIG); cadence_qspi_apb_controller_enable(reg_base); }
static int cadence_spi_set_mode(struct udevice *bus, uint mode) { struct cadence_spi_priv *priv = dev_get_priv(bus); unsigned int clk_pol = (mode & SPI_CPOL) ? 1 : 0; unsigned int clk_pha = (mode & SPI_CPHA) ? 1 : 0; /* Disable QSPI */ cadence_qspi_apb_controller_disable(priv->regbase); /* Set SPI mode */ cadence_qspi_apb_set_clk_mode(priv->regbase, clk_pol, clk_pha); /* Enable QSPI */ cadence_qspi_apb_controller_enable(priv->regbase); return 0; }
void cadence_qspi_apb_set_clk_mode(void *reg_base, unsigned int clk_pol, unsigned int clk_pha) { unsigned int reg; cadence_qspi_apb_controller_disable(reg_base); reg = readl(reg_base + CQSPI_REG_CONFIG); reg &= ~(1 << (CQSPI_REG_CONFIG_CLK_POL_LSB | CQSPI_REG_CONFIG_CLK_PHA_LSB)); reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB); reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB); writel(reg, reg_base + CQSPI_REG_CONFIG); cadence_qspi_apb_controller_enable(reg_base); return; }
void cadence_qspi_apb_delay(void *reg_base, unsigned int ref_clk, unsigned int sclk_hz, unsigned int tshsl_ns, unsigned int tsd2d_ns, unsigned int tchsh_ns, unsigned int tslch_ns) { unsigned int ref_clk_ns; unsigned int sclk_ns; unsigned int tshsl, tchsh, tslch, tsd2d; unsigned int reg; cadence_qspi_apb_controller_disable(reg_base); /* Convert to ns. */ ref_clk_ns = DIV_ROUND_UP(1000000000, ref_clk); /* Convert to ns. */ sclk_ns = DIV_ROUND_UP(1000000000, sclk_hz); /* The controller adds additional delay to that programmed in the reg */ if (tshsl_ns >= sclk_ns + ref_clk_ns) tshsl_ns -= sclk_ns + ref_clk_ns; if (tchsh_ns >= sclk_ns + 3 * ref_clk_ns) tchsh_ns -= sclk_ns + 3 * ref_clk_ns; tshsl = DIV_ROUND_UP(tshsl_ns, ref_clk_ns); tchsh = DIV_ROUND_UP(tchsh_ns, ref_clk_ns); tslch = DIV_ROUND_UP(tslch_ns, ref_clk_ns); tsd2d = DIV_ROUND_UP(tsd2d_ns, ref_clk_ns); reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK) << CQSPI_REG_DELAY_TSHSL_LSB); reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK) << CQSPI_REG_DELAY_TCHSH_LSB); reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK) << CQSPI_REG_DELAY_TSLCH_LSB); reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK) << CQSPI_REG_DELAY_TSD2D_LSB); writel(reg, reg_base + CQSPI_REG_DELAY); cadence_qspi_apb_controller_enable(reg_base); }
void cadence_qspi_apb_config_baudrate_div(void *reg_base, unsigned int ref_clk_hz, unsigned int sclk_hz) { unsigned int reg; unsigned int div; cadence_qspi_apb_controller_disable(reg_base); reg = readl(reg_base + CQSPI_REG_CONFIG); reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); div = ref_clk_hz / sclk_hz; if (div > 32) div = 32; /* Check if even number. */ if ((div & 1)) { div = (div / 2); } else { if (ref_clk_hz % sclk_hz) /* ensure generated SCLK doesn't exceed user specified sclk_hz */ div = (div / 2); else div = (div / 2) - 1; } debug("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__, ref_clk_hz, sclk_hz, div); /* ensure the baud rate doesn't exceed the max value */ if (div > CQSPI_REG_CONFIG_BAUD_MASK) div = CQSPI_REG_CONFIG_BAUD_MASK; reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB); writel(reg, reg_base + CQSPI_REG_CONFIG); cadence_qspi_apb_controller_enable(reg_base); return; }
void cadence_qspi_apb_readdata_capture(void *reg_base, unsigned int bypass, unsigned int delay) { unsigned int reg; cadence_qspi_apb_controller_disable(reg_base); reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE); if (bypass) reg |= CQSPI_REG_RD_DATA_CAPTURE_BYPASS; else reg &= ~CQSPI_REG_RD_DATA_CAPTURE_BYPASS; reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB); reg |= (delay & CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK) << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB; writel(reg, reg_base + CQSPI_REG_RD_DATA_CAPTURE); cadence_qspi_apb_controller_enable(reg_base); }
void cadence_qspi_apb_delay(void *reg_base, unsigned int ref_clk, unsigned int sclk_hz, unsigned int tshsl_ns, unsigned int tsd2d_ns, unsigned int tchsh_ns, unsigned int tslch_ns) { unsigned int ref_clk_ns; unsigned int sclk_ns; unsigned int tshsl, tchsh, tslch, tsd2d; unsigned int reg; cadence_qspi_apb_controller_disable(reg_base); /* Convert to ns. */ ref_clk_ns = (1000000000) / ref_clk; /* Convert to ns. */ sclk_ns = (1000000000) / sclk_hz; /* Plus 1 to round up 1 clock cycle. */ tshsl = CQSPI_CAL_DELAY(tshsl_ns, ref_clk_ns, sclk_ns) + 1; tchsh = CQSPI_CAL_DELAY(tchsh_ns, ref_clk_ns, sclk_ns) + 1; tslch = CQSPI_CAL_DELAY(tslch_ns, ref_clk_ns, sclk_ns) + 1; tsd2d = CQSPI_CAL_DELAY(tsd2d_ns, ref_clk_ns, sclk_ns) + 1; reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK) << CQSPI_REG_DELAY_TSHSL_LSB); reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK) << CQSPI_REG_DELAY_TCHSH_LSB); reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK) << CQSPI_REG_DELAY_TSLCH_LSB); reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK) << CQSPI_REG_DELAY_TSD2D_LSB); writel(reg, reg_base + CQSPI_REG_DELAY); cadence_qspi_apb_controller_enable(reg_base); return; }
int cadence_qspi_apb_process_queue(struct struct_cqspi *cadence_qspi, struct spi_device *spi, unsigned int n_trans, struct spi_transfer **spi_xfer) { struct platform_device *pdev = cadence_qspi->pdev; struct cqspi_platform_data *pdata = pdev->dev.platform_data; struct spi_transfer *cmd_xfer = spi_xfer[0]; struct spi_transfer *data_xfer = (n_trans >= 2) ? spi_xfer[1] : NULL; void __iomem *iobase = cadence_qspi->iobase; unsigned int sclk; int ret = 0; struct cqspi_flash_pdata *f_pdata; pr_debug("%s %d\n", __func__, n_trans); if (!cmd_xfer->len) { pr_err("QSPI: SPI transfer length is 0.\n"); return -EINVAL; } /* Switch chip select. */ if (cadence_qspi->current_cs != spi->chip_select) { cadence_qspi->current_cs = spi->chip_select; cadence_qspi_switch_cs(cadence_qspi, spi->chip_select); } /* Setup baudrate divisor and delays */ f_pdata = &(pdata->f_pdata[cadence_qspi->current_cs]); sclk = cmd_xfer->speed_hz ? cmd_xfer->speed_hz : spi->max_speed_hz; cadence_qspi_apb_controller_disable(iobase); cadence_qspi_apb_config_baudrate_div(iobase, pdata->master_ref_clk_hz, sclk); cadence_qspi_apb_delay(cadence_qspi, pdata->master_ref_clk_hz, sclk); cadence_qspi_apb_readdata_capture(iobase, 1, f_pdata->read_delay); cadence_qspi_apb_controller_enable(iobase); /* * Use STIG command to send if the transfer length is less than * 4 or if only one transfer. */ if ((cmd_xfer->len < 4) || (n_trans == 1)) { /* STIG command */ if (data_xfer && data_xfer->rx_buf) { /* STIG read */ ret = cadence_qspi_apb_command_read(iobase, cmd_xfer->len, cmd_xfer->tx_buf, data_xfer->len, data_xfer->rx_buf); } else { /* STIG write */ ret = cadence_qspi_apb_command_write(iobase, cmd_xfer->len, cmd_xfer->tx_buf); } } else if (cmd_xfer->len >= 4 && (n_trans == 2)){ /* Indirect operation */ if (data_xfer->rx_buf) { /* Indirect read */ ret = cadence_qspi_apb_indirect_read_setup(iobase, pdata->qspi_ahb_phy, cmd_xfer->len, cmd_xfer->tx_buf, spi->addr_width); if (pdata->enable_dma) { ret = cadence_qspi_apb_indirect_read_dma( cadence_qspi, data_xfer->len, data_xfer->rx_buf); } else { ret = cadence_qspi_apb_indirect_read_execute( cadence_qspi, data_xfer->len, data_xfer->rx_buf); } } else { /* Indirect write */ ret = cadence_qspi_apb_indirect_write_setup( iobase, pdata->qspi_ahb_phy, cmd_xfer->len, cmd_xfer->tx_buf); if (pdata->enable_dma) { ret = cadence_qspi_apb_indirect_write_dma( cadence_qspi, data_xfer->len, (unsigned char *)data_xfer->tx_buf); } else { ret = cadence_qspi_apb_indirect_write_execute( cadence_qspi, data_xfer->len, data_xfer->tx_buf); } } } else { pr_err("QSPI : Unknown SPI transfer.\n"); return -EINVAL; } return ret; }
/* Calibration sequence to determine the read data capture delay register */ static int spi_calibration(struct udevice *bus) { struct cadence_spi_platdata *plat = bus->platdata; struct cadence_spi_priv *priv = dev_get_priv(bus); void *base = priv->regbase; u8 opcode_rdid = 0x9F; unsigned int idcode = 0, temp = 0; int err = 0, i, range_lo = -1, range_hi = -1; /* start with slowest clock (1 MHz) */ cadence_spi_write_speed(bus, 1000000); /* configure the read data capture delay register to 0 */ cadence_qspi_apb_readdata_capture(base, 1, 0); /* Enable QSPI */ cadence_qspi_apb_controller_enable(base); /* read the ID which will be our golden value */ err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid, 3, (u8 *)&idcode); if (err) { puts("SF: Calibration failed (read)\n"); return err; } /* use back the intended clock and find low range */ cadence_spi_write_speed(bus, plat->max_hz); for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) { /* Disable QSPI */ cadence_qspi_apb_controller_disable(base); /* reconfigure the read data capture delay register */ cadence_qspi_apb_readdata_capture(base, 1, i); /* Enable back QSPI */ cadence_qspi_apb_controller_enable(base); /* issue a RDID to get the ID value */ err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid, 3, (u8 *)&temp); if (err) { puts("SF: Calibration failed (read)\n"); return err; } /* search for range lo */ if (range_lo == -1 && temp == idcode) { range_lo = i; continue; } /* search for range hi */ if (range_lo != -1 && temp != idcode) { range_hi = i - 1; break; } range_hi = i; } if (range_lo == -1) { puts("SF: Calibration failed (low range)\n"); return err; } /* Disable QSPI for subsequent initialization */ cadence_qspi_apb_controller_disable(base); /* configure the final value for read data capture delay register */ cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2); debug("SF: Read data capture delay calibrated to %i (%i - %i)\n", (range_hi + range_lo) / 2, range_lo, range_hi); /* just to ensure we do once only when speed or chip select change */ priv->qspi_calibrated_hz = plat->max_hz; priv->qspi_calibrated_cs = spi_chip_select(bus); return 0; }