rtems_status_code can_open( const lpc176x_can_number minor, can_freq freq )
{
const can_driver_entry *const can_driver = &can_driver_table[ minor ];
rtems_status_code sc = RTEMS_INVALID_NUMBER;
if ( CAN_DRIVER_IS_MINOR_VALID( minor ) ) {
/*Enable CAN and acceptance filter modules.*/
sc =
lpc176x_module_enable( can_driver->module, LPC176X_MODULE_PCLK_DEFAULT );
RTEMS_CHECK_SC( sc, "enable can module" );
sc = lpc176x_module_enable( LPC176X_MODULE_ACCF,
LPC176X_MODULE_PCLK_DEFAULT );
RTEMS_CHECK_SC( sc, "enable acceptance filter" );
/*Set pin functions.*/
setpins( minor );
can_reset( can_driver );
can_driver->device->IER = CAN_DEFAULT_INTERRUPT_CONFIGURATION;
sc = can_frequency( can_driver, freq );
RTEMS_CHECK_SC( sc, "Configure CAN frequency" );
can_initialize();
acceptance_filter_device->AFMR = CAN_ACCF_AFMR_ACCBP; /*Bypass Filter.*/
}
return sc;
}
void can_setup(void)
{
/* Enable peripheral clocks. */
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN);
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN);
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_CANEN);
AFIO_MAPR = AFIO_MAPR_CAN1_REMAP_PORTB;
/* Configure CAN pin: RX (input pull-up). */
gpio_set_mode(GPIOB, GPIO_MODE_INPUT,
GPIO_CNF_INPUT_PULL_UPDOWN, GPIO_CAN1_PB_RX);
gpio_set(GPIOB, GPIO_CAN1_PB_RX);
/* Configure CAN pin: TX. */
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_CAN1_PB_TX);
/* NVIC setup. */
nvic_enable_irq(NVIC_USB_LP_CAN_RX0_IRQ);
nvic_set_priority(NVIC_USB_LP_CAN_RX0_IRQ, 1);
/* Reset CAN. */
can_reset(CAN1);
/* CAN cell init. */
if (can_init(CAN1,
false, /* TTCM: Time triggered comm mode? */
true, /* ABOM: Automatic bus-off management? */
false, /* AWUM: Automatic wakeup mode? */
false, /* NART: No automatic retransmission? */
false, /* RFLM: Receive FIFO locked mode? */
false, /* TXFP: Transmit FIFO priority? */
CAN_BTR_SJW_1TQ,
CAN_BTR_TS1_3TQ,
CAN_BTR_TS2_4TQ,
12)) /* BRP+1: Baud rate prescaler */
{
gpio_set(GPIOA, GPIO8); /* LED0 off */
gpio_set(GPIOB, GPIO4); /* LED1 off */
gpio_set(GPIOC, GPIO15); /* LED2 off */
gpio_clear(GPIOC, GPIO2); /* LED3 on */
gpio_set(GPIOC, GPIO5); /* LED4 off */
/* Die because we failed to initialize. */
while (1)
__asm__("nop");
}
/* CAN filter 0 init. */
can_filter_id_mask_32bit_init(CAN1,
0, /* Filter ID */
0, /* CAN ID */
0, /* CAN ID mask */
0, /* FIFO assignment (here: FIFO0) */
true); /* Enable the filter. */
/* Enable CAN RX interrupt. */
can_enable_irq(CAN1, CAN_IER_FMPIE0);
}
void can_init(can_t *obj, PinName rd, PinName td) {
CANName can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD);
CANName can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD);
obj->dev = (LPC_CAN_TypeDef *)pinmap_merge(can_rd, can_td);
MBED_ASSERT((int)obj->dev != NC);
switch ((int)obj->dev) {
case CAN_1: LPC_SC->PCONP |= 1 << 13; break;
case CAN_2: LPC_SC->PCONP |= 1 << 14; break;
}
pinmap_pinout(rd, PinMap_CAN_RD);
pinmap_pinout(td, PinMap_CAN_TD);
switch ((int)obj->dev) {
case CAN_1: obj->index = 0; break;
case CAN_2: obj->index = 1; break;
}
can_reset(obj);
obj->dev->IER = 0; // Disable Interrupts
can_frequency(obj, 100000);
LPC_CANAF->AFMR = ACCF_BYPASS; // Bypass Filter
}
void can_config(int mode)
{
can_reset(); //reset mcp
spi_chipselect(ENABLE); //enable slave
spi_tx_rx(WRITE_CMD);
//Enter config mode
//Send address of CAN CONTROL registerxFF because 0xXFH is mentioned
//0b10000000 to enter config mode
//be aware of potential delay while setting config_mode
can_write_reg(0xFF,0x80); //check config mode is achieved or not
spi_chipselect(DISABLE);
if(can_read_status()>>5 !=0x04)
{
printf("\n\rERROR UNABLE TO ENTER CONFIG MODE\n\r");
}
else
{
static void can_setup(void) {
/* Enable peripheral clocks */
rcc_periph_clock_enable(RCC_AFIO);
rcc_periph_clock_enable(RCC_CAN1);
AFIO_MAPR |= AFIO_MAPR_CAN1_REMAP_PORTB;
/* Configure CAN pin: RX (input pull-up) */
gpio_set_mode(GPIO_BANK_CAN1_PB_RX, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, GPIO_CAN1_PB_RX);
gpio_set(GPIO_BANK_CAN1_PB_RX, GPIO_CAN1_PB_RX);
/* Configure CAN pin: TX */
gpio_set_mode(GPIO_BANK_CAN1_PB_TX, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_CAN1_PB_TX);
/* NVIC setup */
nvic_enable_irq(NVIC_USB_LP_CAN_RX0_IRQ);
nvic_set_priority(NVIC_USB_LP_CAN_RX0_IRQ, 1);
/* Reset CAN */
can_reset(CAN1);
/* CAN cell init.
* Setting the bitrate to 250kHz. APB1 = 36MHz,
* prescaler = 9 -> 4MHz time quanta frequency.
* 1tq sync + 9tq bit segment1 (TS1) + 6tq bit segment2 (TS2) =
* 16time quanto per bit period, therefor 4MHz/16 = 250kHz
*/
if (can_init(CAN1, false, /* TTCM: Time triggered comm mode? */
true, /* ABOM: Automatic bus-off management? */
false, /* AWUM: Automatic wakeup mode? */
false, /* NART: No automatic retransmission? */
false, /* RFLM: Receive FIFO locked mode? */
false, /* TXFP: Transmit FIFO priority? */
CAN_BTR_SJW_1TQ, CAN_BTR_TS1_9TQ, CAN_BTR_TS2_6TQ, 9, false, false)) {
gpio_clear(GPIOC, GPIO13); /* LED green on */
/* Die because we failed to initialize. */
while (1)
__asm__("nop");
}
/* CAN filter 0 init. */
can_filter_id_mask_32bit_init(CAN1, 0, /* Filter ID */
0, /* CAN ID */
0, /* CAN ID mask */
0, /* FIFO assignment (here: FIFO0) */
true); /* Enable the filter. */
/* Enable CAN RX interrupt. */
can_enable_irq(CAN1, CAN_IER_FMPIE0);
}
LONG cop_reset(BYTE baudrate)
{
// 1. Reset CAN, operation status = stopped
if((cop_error = can_reset()) != CANERR_NOERROR)
{
return cop_error;
}
// 2. Wait 100 milliseconds to continue
#if defined(_WIN32)
Sleep(100);
#elif defined(__linux__)
usleep(100000);
#else
can_start_timer(100); while(!can_is_timeout()) {}
#endif
// 3. Start CAN, operation status = running
if((cop_error = can_start(baudrate)) != CANERR_NOERROR)
{
can_reset(); // on error: reset CAN
return cop_error;
}
cop_baudrate = baudrate; // actual baudrate
return cop_error;
}
int can_init(uint32_t id, uint32_t mask, can_tx_callback_t atxcb, can_rx_callback_t arxcb, struct csp_can_config *conf) {
csp_assert(conf && conf->bitrate && conf->clock_speed);
/* Set id and mask */
can_id = id;
can_mask = mask;
/* Set callbacks */
txcb = atxcb;
rxcb = arxcb;
/* Set fcpu and bps */
clock_speed = conf->clock_speed;
bitrate = conf->bitrate;
return can_reset(clock_speed, bitrate);
}
/*
* Show CAN errors as text,
* in case of Bus-Off, try to recover
*/
static void displayerror(int device, canmsg_t *rx)
{
/* static int buffcnt = 0; */
fprintf(stderr, "Flags 0x%02x,", rx->flags);
if( 0 == (rx->flags & MSG_ERR_MASK)) {
fprintf(stderr, " CAN Error Free");
}
if( rx->flags & MSG_WARNING) {
fprintf(stderr, " CAN Warning Level,");
}
if( rx->flags & MSG_PASSIVE) {
fprintf(stderr, " CAN Error Passive,");
}
if( rx->flags & MSG_BUSOFF) {
fprintf(stderr, " CAN Bus Off,");
can_reset(fd[device]);
/* sleep 100ms */
usleep (100000);
can_start(fd[device]);
}
/* printf("\n"); */
}
LONG cop_init(LONG board, LPVOID param, BYTE baudrate)
{
// 1. Exit CAN if initialized or running
if((cop_error = can_exit()) != CANERR_NOERROR)
{
//return cop_error;
}
// 2. Init CAN, operation status = initialized
if((cop_error = can_init(board, param)) != CANERR_NOERROR)
{
can_exit(); // on error: exit CAN
return cop_error;
}
// 3. Start CAN, operation status = running
if((cop_error = can_start(baudrate)) != CANERR_NOERROR)
{
can_reset(); // on error: reset CAN
can_exit(); // exit CAN
return cop_error;
}
cop_baudrate = baudrate; // actual baudrate
return cop_error;
}
void can_hw_init(void)
{
/* Enable peripheral clocks. */
rcc_periph_clock_enable(RCC_AFIO);
rcc_periph_clock_enable(RCC_GPIOB);
rcc_periph_clock_enable(RCC_CAN1);
/* Remap the gpio pin if necessary. */
AFIO_MAPR |= AFIO_MAPR_CAN1_REMAP_PORTB;
/* Configure CAN pin: RX (input pull-up). */
gpio_set_mode(GPIO_BANK_CAN1_PB_RX, GPIO_MODE_INPUT,
GPIO_CNF_INPUT_PULL_UPDOWN, GPIO_CAN1_PB_RX);
gpio_set(GPIO_BANK_CAN1_PB_RX, GPIO_CAN1_PB_RX);
/* Configure CAN pin: TX (output push-pull). */
gpio_set_mode(GPIO_BANK_CAN1_PB_TX, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_CAN1_PB_TX);
/* NVIC setup. */
nvic_enable_irq(NVIC_USB_LP_CAN_RX0_IRQ);
nvic_set_priority(NVIC_USB_LP_CAN_RX0_IRQ, NVIC_USB_LP_CAN_RX0_IRQ_PRIO);
/* Reset CAN. */
can_reset(CAN1);
/* CAN cell init.
* For time quanta calculation see STM32 reference manual
* section 24.7.7 "Bit timing" page 645
*
* To talk to CSC using LPC mcu we need a baud rate of 375kHz
* The APB1 runs at 36MHz therefor we select a prescaler of 12
* resulting in time quanta frequency of 36MHz / 12 = 3MHz
*
* As the Bit time is combined of 1tq for SYNC_SEG, TS1tq for bit
* segment 1 and TS2tq for bit segment 2:
* BITtq = 1tq + TS1tq + TS2tq
*
* We can choose to use TS1 = 3 and TS2 = 4 getting
* 1tq + 3tq + 4tq = 8tq per bit therefor a bit frequency is
* 3MHZ / 8 = 375kHz
*
* Maximum baud rate of CAN is 1MHz so we can choose to use
* prescaler of 2 resulting in a quanta frequency of 36MHz / 2 = 18Mhz
*
* So we need to devide the frequency by 18. This can be accomplished
* using TS1 = 10 and TS2 = 7 resulting in:
* 1tq + 10tq + 7tq = 18tq
*
* NOTE: Although it is out of spec I managed to have CAN run at 2MBit
* Just decrease the prescaler to 1. It worked for me(tm) (esden)
*/
if (can_init(CAN1,
false, /* TTCM: Time triggered comm mode? */
true, /* ABOM: Automatic bus-off management? */
false, /* AWUM: Automatic wakeup mode? */
false, /* NART: No automatic retransmission? */
false, /* RFLM: Receive FIFO locked mode? */
false, /* TXFP: Transmit FIFO priority? */
CAN_BTR_SJW_1TQ,
CAN_BTR_TS1_10TQ,
CAN_BTR_TS2_7TQ,
2, /* BRP+1: Baud rate prescaler */
false, /* loopback mode */
false)) /* silent mode */
{
/* TODO we need something somewhere where we can leave a note
* that CAN was unable to initialize. Just like any other
* driver should...
*/
can_reset(CAN1);
return;
}
/* CAN filter 0 init. */
can_filter_id_mask_32bit_init(CAN1,
0, /* Filter ID */
0, /* CAN ID */
0, /* CAN ID mask */
0, /* FIFO assignment (here: FIFO0) */
true); /* Enable the filter. */
/* Enable CAN RX interrupt. */
can_enable_irq(CAN1, CAN_IER_FMPIE0);
/* Remember that we succeeded to initialize. */
can_initialized = true;
}
////////////////////////////////////////////////////////////
// MCP2515 init routine
////////////////////////////////////////////////////////////
void can_init(short id){
delay_ms(25);
// We don't do a hardware reset, since we use the CLKOUT to clock the PIC
//mcp2515_rst_tris = 0;
//mcp2515_rst = 0;
//mcp2515_rst = 1;
// Do software reset instead
can_reset();
// We're in config mode now (auto after reset)
rx_message_pending = 0;
tx_message_pending = 0;
// Set physical layer configuration
//
// Fosc = 16MHz
// BRP = 7 (divide by 8)
// Sync Seg = 1TQ
// Prop Seg = 1TQ
// Phase Seg1 = 3TQ
// Phase Seg2 = 3TQ
//
// TQ = 2 * (1/Fosc) * (BRP+1)
// Bus speed = 1/(Total # of TQ) * TQ
// set BRP to div by 8
can_write_reg(CNF1, 0x07);
can_write_reg(CNF2, 0x90);
can_write_reg(CNF3, 0x02);
// Configure Receive buffer 0 Mask and Filters
// Receive buffer 0 will not be used
can_write_reg(RXM0SIDH, 0xFF);
can_write_reg(RXM0SIDL, 0xFF);
can_write_reg(RXF0SIDH, 0xFF);
can_write_reg(RXF0SIDL, 0xFF);
// Configure Receive Buffer 1 Mask and Filters
can_write_reg(RXF1SIDH, 0xFF);
can_write_reg(RXF1SIDL, 0xFF);
can_write_reg(RXM1SIDH, 0x00); // was FF
can_write_reg(RXM1SIDL, 0x00);
// Initialize Filter 2 to match x0 bBaseRecID
can_write_reg(RXF2SIDH, CAN_RX_ID);
can_write_reg(RXF2SIDL, 0x00); //; Make sure EXIDE bit (bit 3) is set correctly in filter
// Initialize Filter 3 to match x1
can_write_reg(RXF3SIDH, CAN_RX_ID + 1);
can_write_reg(RXF3SIDL, 0x00);
// Initialize Filter 4 to match x2
can_write_reg(RXF4SIDH, CAN_RX_ID + 2);
can_write_reg(RXF4SIDL, 0x00);
// Initialize Filter 5 to match x3
can_write_reg(RXF5SIDH, CAN_RX_ID + 3);
can_write_reg(RXF5SIDL, 0x00);
// Disable all MCP2510 Interrupts
can_write_reg(CANINTE, 0x00);
// Set the TX id
can_set_id(id);
// Set normal mode (not loopback)
//can_set_loopback_mode();
can_set_normal_mode();
// Disable filter and mask on buffer 0
can_write_bits(RXB0CTRL, 0x60, 0x60);
}
void CAN::reset() {
lock();
can_reset(&_can);
unlock();
}
void CAN::reset() {
can_reset(&_can);
}
void can_setup(void)
{
/* Enable peripheral clocks. */
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN);
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN);
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_CANEN);
/* Configure CAN pin: RX */
gpio_set_mode(GPIOA, GPIO_MODE_INPUT,
GPIO_CNF_INPUT_PULL_UPDOWN, GPIO_CAN_RX);
gpio_set(GPIOA, GPIO_CAN_RX);
/* Configure CAN pin: TX */
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_CAN_TX);
/* NVIC configuration */
nvic_enable_irq(NVIC_USB_LP_CAN_RX0_IRQ);
nvic_set_priority(NVIC_USB_LP_CAN_RX0_IRQ, 1);
/* CAN register init */
can_reset(CAN1);
/* CAN cell init */
if (can_init(CAN1,
false, /* TTCM: Time triggered comm mode? */
true, /* ABOM: Automatic bus-off management? */
false, /* AWUM: Automatic wakeup mode? */
false, /* NART: No automatic retransmission? */
false, /* RFLM: Receive FIFO locked mode? */
false, /* TXFP: Transmit FIFO priority? */
CAN_BTR_SJW_1TQ,
CAN_BTR_TS1_3TQ,
CAN_BTR_TS2_4TQ,
12,
false,
false)) /* BRP+1: Baud rate prescaler */
{
ON(LED_RED);
OFF(LED_GREEN);
OFF(LED_BLUE);
OFF(LED_ORANGE);
/* Die because we failed to initialize. */
while (1)
__asm__("nop");
}
/* CAN filter init */
can_filter_id_mask_32bit_init(CAN1,
0, /* Filter ID */
0, /* CAN ID */
0, /* CAN ID mask */
0, /* FIFO assignment (here: FIFO0) */
true); /* Enable the filter. */
/* transmit struct init */
can_tx_msg.id = 0x0;
can_tx_msg.rtr = false;
#ifdef CAN__USE_EXT_ID
can_tx_msg.ide = true;
#else
can_tx_msg.ide = false;
#endif
can_tx_msg.dlc = 1;
can_enable_irq(CAN1, CAN_IER_FMPIE0);
}
void vCanCmdTask( void * pvParameters )
{
static xCanCmdElement_t xCanCmdElement;
(void) pvParameters;
xCanCmdQueue = xQueueCreate((unsigned portBASE_TYPE)CAN_CMD_QUEUE_LEN,
(unsigned portBASE_TYPE)sizeof(xCanCmdElement_t));
for( ;; )
{
while (pdFALSE == xQueueReceive(xCanCmdQueue, &xCanCmdElement, portMAX_DELAY));
switch (xCanCmdElement.xCanCmd)
{
case CMD_CAN_RESET:
can_reset();
break;
case CMD_CAN_CONF:
can_default_conf(xCanCmdElement.ucDefaultConfig);
break;
case CMD_CAN_BAUD:
switch (xCanCmdElement.ucGetSetAuto)
{
case CMD_CAN_BAUD_GET_VAL:
can_get_bt(&xCanCmdElement.xArgMsg[0],
&xCanCmdElement.xArgMsg[1],
&xCanCmdElement.xArgMsg[2]);
break;
case CMD_CAN_BAUD_SET_VAL:
can_set_bt(xCanCmdElement.xArgMsg[0],
xCanCmdElement.xArgMsg[1],
xCanCmdElement.xArgMsg[2]);
break;
case CMD_CAN_BAUD_AUTO_VAL:
can_auto_baudrate();
break;
}
break;
case CMD_CAN_ENA:
switch (xCanCmdElement.ucDisEnaListen)
{
case CMD_CAN_ENA_VAL:
can_ena();
break;
case CMD_CAN_ENA_LISTEN_VAL:
can_ena_listen();
break;
case CMD_CAN_DIS_VAL:
can_dis();
break;
}
break;
case CMD_CAN_MOB_RDWR:
if (CMD_CAN_RD_VAL == xCanCmdElement.ucReadWrite)
{
can_rd_cfg(xCanCmdElement.cMobNum,xCanCmdElement.sTag,xCanCmdElement.sMask);
} else
if (CMD_CAN_WR_VAL == xCanCmdElement.ucReadWrite)
{
static xCanPacket_t xCanPkt;
xCanPkt.len = xCanCmdElement.sLen;
xCanPkt.tag = xCanCmdElement.sTag;
xCanPkt.mob = xCanCmdElement.cMobNum;
xCanPkt.rtr = (xCanCmdElement.cRtr&0x10)>>4;
memcpy(xCanPkt.msg,xCanCmdElement.xArgMsg,(xCanPkt.len>8)?8:xCanPkt.len);
FreeRTOS_CAN_Write(&xCanPkt, portMAX_DELAY);
}
break;
case CMD_CAN_MOB_DUMP:
if (CMD_CAN_UNDUMP == xCanCmdElement.ucUndumpDump)
{
ucMobDump &= ~(1<< xCanCmdElement.cMobNum);
} else
if (CMD_CAN_DUMP == xCanCmdElement.ucUndumpDump)
{
ucMobDump |= ~(1<< xCanCmdElement.cMobNum);
}
break;
default:
can_unknow();
}
}
}
void modcan_init(void)
{
// enable the clocks
rcc_periph_clock_enable(RCC_CAN1);
rcc_periph_clock_enable(RCC_CAN2);
rcc_periph_clock_enable(RCC_GPIOB);
rcc_periph_clock_enable(RCC_GPIOA);
// init pins
gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO5 | GPIO6 );
gpio_set_af(GPIOB, GPIO_AF9, GPIO5 | GPIO6 );
gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO11 | GPIO12 );
gpio_set_af(GPIOA, GPIO_AF9, GPIO11 | GPIO12 );
gpio_set_output_options(GPIOB, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ, GPIO6 );
gpio_set_output_options(GPIOA, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ, GPIO12 );
can_reset(CAN1);
can_reset(CAN2);
can_leave_sleep_mode(CAN1);
can_leave_sleep_mode(CAN2);
struct can_timing ct;
can_timing_init(&ct, CAN_FREQ_500K, CAN_SAMPLE_75);
//uint32_t canfreq = can_timing_getfreq(&ct);
if (can_enter_init_mode_blocking(CAN1)) {
can_mode_set_autobusoff(CAN1, true);
can_mode_set_timetriggered(CAN1, true);
can_timing_set(CAN1, &ct);
can_filter_set_slave_start(CAN1, 5);
//CAN_MCR(CAN1) &= ~CAN_MCR_DBF;
can_filter_init_enter(CAN1);
can_filter_set_mask32(CAN1, 0, 0, MOB_ANY, MOB_ANY);
can_filter_set_mask32(CAN1, 5, 0, MOB_ANY, MOB_ANY);
can_filter_init_leave(CAN1);
can_leave_init_mode_blocking(CAN1);
}
if (can_enter_init_mode_blocking(CAN2)) {
can_mode_set_autobusoff(CAN2, true);
can_mode_set_timetriggered(CAN2, true);
can_timing_set(CAN2, &ct);
can_leave_init_mode_blocking(CAN2);
}
nvic_enable_irq(NVIC_CAN1_RX0_IRQ);
nvic_enable_irq(NVIC_CAN1_RX1_IRQ);
nvic_enable_irq(NVIC_CAN2_RX0_IRQ);
nvic_enable_irq(NVIC_CAN2_RX1_IRQ);
nvic_enable_irq(NVIC_CAN1_SCE_IRQ);
nvic_enable_irq(NVIC_CAN2_SCE_IRQ);
nvic_enable_irq(NVIC_CAN1_TX_IRQ);
nvic_enable_irq(NVIC_CAN2_TX_IRQ);
nvic_set_priority(NVIC_CAN1_RX0_IRQ, 1);
nvic_set_priority(NVIC_CAN1_RX1_IRQ, 1);
nvic_set_priority(NVIC_CAN2_RX0_IRQ, 1);
nvic_set_priority(NVIC_CAN2_RX1_IRQ, 1);
nvic_set_priority(NVIC_CAN1_SCE_IRQ, 1);
nvic_set_priority(NVIC_CAN2_SCE_IRQ, 1);
nvic_set_priority(NVIC_CAN1_TX_IRQ, 1);
nvic_set_priority(NVIC_CAN2_TX_IRQ, 1);
/* Enable CAN RX interrupt. */
can_enable_irq(CAN1, CAN_IER_FMPIE0 | CAN_IER_FMPIE1 | CAN_IER_TMEIE);
can_enable_irq(CAN2, CAN_IER_FMPIE0 | CAN_IER_FMPIE1 | CAN_IER_TMEIE);
}