BOOT_CODE static void init_irqs(cap_t root_cnode_cap) { irq_t i; for (i = 0; i <= maxIRQ; i++) { setIRQState(IRQInactive, i); } setIRQState(IRQTimer, KERNEL_TIMER_IRQ); #ifdef CONFIG_ARM_HYPERVISOR_SUPPORT setIRQState(IRQReserved, INTERRUPT_VGIC_MAINTENANCE); #endif #ifdef CONFIG_ARM_SMMU setIRQState(IRQReserved, INTERRUPT_SMMU); #endif #ifdef CONFIG_ARM_ENABLE_PMU_OVERFLOW_INTERRUPT #ifdef KERNEL_PMU_IRQ setIRQState(IRQReserved, KERNEL_PMU_IRQ); #if (defined CONFIG_PLAT_TX1 && defined ENABLE_SMP_SUPPORT) //SELFOUR-1252 #error "This platform doesn't support tracking CPU utilisation on multicore" #endif /* CONFIG_PLAT_TX1 && ENABLE_SMP_SUPPORT */ #else #error "This platform doesn't support tracking CPU utilisation feature" #endif /* KERNEL_TIMER_IRQ */ #endif /* CONFIG_ARM_ENABLE_PMU_OVERFLOW_INTERRUPT */ #ifdef ENABLE_SMP_SUPPORT setIRQState(IRQIPI, irq_remote_call_ipi); setIRQState(IRQIPI, irq_reschedule_ipi); #endif /* ENABLE_SMP_SUPPORT */ /* provide the IRQ control cap */ write_slot(SLOT_PTR(pptr_of_cap(root_cnode_cap), seL4_CapIRQControl), cap_irq_control_cap_new()); }
BOOT_CODE static void init_irqs(cap_t root_cnode_cap) { irq_t i; for (i = 0; i <= maxIRQ; i++) { if (i == irq_timer) { setIRQState(IRQTimer, i); } else if (i == irq_iommu) { setIRQState(IRQReserved, i); } else if (i == 2 && config_set(CONFIG_IRQ_PIC)) { /* cascaded legacy PIC */ setIRQState(IRQReserved, i); } else if (i >= irq_isa_min && i <= irq_isa_max) { if (config_set(CONFIG_IRQ_PIC)) { setIRQState(IRQInactive, i); } else { setIRQState(IRQReserved, i); } } else if (i >= irq_user_min && i <= irq_user_max) { if (config_set(CONFIG_IRQ_IOAPIC)) { setIRQState(IRQInactive, i); } else { setIRQState(IRQReserved, i); } } else { setIRQState(IRQReserved, i); } } Arch_irqStateInit(); /* provide the IRQ control cap */ write_slot(SLOT_PTR(pptr_of_cap(root_cnode_cap), seL4_CapIRQControl), cap_irq_control_cap_new()); }
BOOT_CODE static void init_irqs(cap_t root_cnode_cap, bool_t mask_irqs) { irq_t i; for (i = 0; i <= maxIRQ; i++) { if (i == irq_timer) { setIRQState(IRQTimer, i); } else if (i == irq_iommu) { setIRQState(IRQReserved, i); #ifdef CONFIG_IRQ_PIC } else if (i == 2) { /* cascaded legacy PIC */ setIRQState(IRQReserved, i); #endif } else if (i >= irq_controller_min && i <= irq_controller_max) if (mask_irqs) /* Don't use setIRQState() here because it implicitly also enables */ /* the IRQ on the interrupt controller which only node 0 is allowed to do. */ { intStateIRQTable[i] = IRQReserved; } else { setIRQState(IRQInactive, i); } else if (i >= irq_msi_min && i <= irq_msi_max) { setIRQState(IRQInactive, i); } } /* provide the IRQ control cap */ write_slot(SLOT_PTR(pptr_of_cap(root_cnode_cap), BI_CAP_IRQ_CTRL), cap_irq_control_cap_new()); }