main()
{
/*
catch_interrupt(irqhandler, 10);
catch_interrupt(irqhandler, 11);
catch_interrupt(irqhandler, 12);
enable_irq(10);
enable_irq(11);
enable_irq(12);
force_irq(10);
force_irq(11);
force_irq(12);
force_irq(10);
lreg[IFORCE/4] = (7 << 10); // force irq 10, 11 & 12 simultaneously
*/
catch_interrupt(irqhandler,8);
enable_irq(8);
timer[TCTRL/4] = 0x200;
timer[SCALOA/4] = 0x2FA;
timer[SCALVA/4] = 0x2FA;
timer[T1CTRL/4] = 0x0B;
timer[LOADT1/4] = 0xFFFF;
timer[T1VAL/4] = 0xFFFF;
while (1){
}
}
AppUtil::~AppUtil()
{
instance_ = NULL;
catch_interrupt( CUBIT_FALSE );
if (mProgressTool)
delete mProgressTool;
mProgressTool = NULL;
}
bool UartInit(
const uint32_t CPUFreq,
const uint32_t BaudRate,
const uint32_t Control,
uart_regs * uart_isr) {
int scaler = CPUFreq/(8*BaudRate);
int irq = 0;
uart = uart_isr;
/* most times the baudrate cannot be reached exactly!
* For this the PCs set the baudrate slightly higher
* and here this is done, too */
if (scaler*8*BaudRate != CPUFreq){
scaler--;
}
/* if you do this outside, more uarts can be used with this file*/
/* uart = (uart_regs *)GENERIC_UART_BASE_ADDR;*/
if ((BaudRate < 10) || (CPUFreq < 1000000) || (BaudRate > CPUFreq/8)) {
return false;
}
uart->scaler = scaler;
switch((uint32_t)uart){
case GENERIC_UART_BASE_ADDR: irq = 2; break;
case DEBUG_UART_BASE_ADDR: irq = 7; break;
default : return false;
}
catch_interrupt(IsrUart, irq);
uart->control = Control;
uart->status = 0;
// printf("Scaler = %d Control = %d\n",scaler,Control);
irq = GetUartIdx(uart);
UartData[irq].RxIdxHead = 0;
UartData[irq].RxIdxTail = 0;
UartData[irq].TxIdxHead = 0;
UartData[irq].TxIdxTail = 0;
return true;
}
/*
* gpio_test_ext():
*
* addr - core address
* imask - value of imask generic
* pirq - value of pirq generic
* irqgen - value of irqgen generic
*
* This test also makes use of IRQMP. irqmp_test() must
* be run before this test in order to initialize irqmp_base.
*
* This test requires that the GPIO lines have external pull-ups
*
*/
int gpio_test_irq_mask(int addr, int imask, int pirq, int irqgen, int iomask)
{
int width, k, i, numirq;
/* Perform simple test first, get back width of port */
width = gpio_test(addr);
report_subtest(2);
/* Initialize interrupts */
irqmp_base->irqlevel = 0; /* clear level reg */
irqmp_base->irqmask = 0; /* mask all interrupts */
irqmp_base->irqclear = -1; /* clear all pending interrupts */
/* Set up interrupt handler */
if (irqgen == 0) {
/* Fixed mapping IO[i] = interrupt pirq + i */
for (i=pirq ? 1 : 0; i <width; i++) {
if ((iomask & (1 << i)) == 0) continue;
if ((pirq+i) < 32) {
catch_interrupt(gpio_irqhandler, pirq+i);
/* Enable interrupt on IRQMP */
irqmp_base->irqmask |= (1 << (pirq+i));
}
}
} else if (irqgen == 1) {
/* One shared interrupt pirq */
catch_interrupt(gpio_irqhandler, pirq);
/* Enable interrupt on IRQMP */
irqmp_base->irqmask = (1 << pirq);
} else {
/* Core can map lines to irqgen interrupt lines */
for (i=0; i < irqgen; i++) {
if ((pirq+i) < 32) {
catch_interrupt(gpio_irqhandler, pirq+i);
/* Enable interrupt on IRQMP */
irqmp_base->irqmask |= (1 << (pirq+i));
}
}
}
pio[1] = 0; /* Prepare to drive all lines low */
pio[4] = 0; /* Interrupt level = low */
pio[5] = -1; /* Edge */
pio[3] = (-1) & iomask; /* Enable all interrupts */
/* Iterate once for irqgen = 0, 1 and irqgen times for other values */
for (k = 0; k < (irqgen ? irqgen : 1); k++) {
/* Possibly remap interrupts */
for (i = 0; (irqgen > 1) && (i < ((width+3)/4)); i++) {
pio[8+i] = (k << 24) | (k << 16) | (k << 8) | k;
}
/* Initialize interrupt counting */
irqtbl[0] = 1;
numirq = 0;
/* Assert interrupts */
for (i = (irqgen != 0 || pirq != 0) ? 0 : 1; i < width; i++) {
if ((iomask & (1 << i)) == 0) continue;
/* Drive line i low */
pio[2] = (1 << i);
/*
* Wait for interrupt, or skip to next if interrupt is masked.
* Test may lock here if imask is wrong or core/connection is
* bad.
*/
while((imask & (1 << i)) && pio[2]);
}
pio[2] = 0;
/* Check interrupts */
for (i = (irqgen != 0 || pirq != 0) ? 0 : 1; i < width; i++) {
/* Skip lines that cannot generate irqs */
if ((iomask & (1 << i)) == 0) continue;
if ((imask & (1 << i)) == 0)
continue;
numirq++;
/*
* With irqgen = 0 the interrupt asserted should equal the
* io line plus pirq offset. For the other modes, pirq+k should
* have been asserted
*/
if (((irqgen == 0) && (irqtbl[numirq] != (pirq+i+0x10))) ||
((irqgen != 0) && (irqtbl[numirq] != (pirq+k+0x10))))
fail(4+i+32*k);
}
/*
* The number of expected interrupts in all cases is the same as
* the number of I/O lines with interrupt generation capabilities
*/
if ((irqtbl[0] - numirq) != 1) fail(3);
}
pio[3] = 0; /* Mask all interrupts on GRGPIO */
irqmp_base->irqmask = 0x0; /* mask all interrupts */
irqmp_base->irqclear = -1; /* clear all pending interrupts */
return 0;
}
