/* Copy SPD data for on-board memory */
static void copy_spd(struct pei_data *peid)
{
const int gpio_vector[] = {13, 9, 47, -1};
int spd_index = get_gpios(gpio_vector);
char *spd_file;
size_t spd_file_len;
printk(BIOS_DEBUG, "SPD index %d\n", spd_index);
spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab,
&spd_file_len);
if (!spd_file)
die("SPD data not found.");
if (spd_file_len <
((spd_index + 1) * sizeof(peid->spd_data[0]))) {
printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
spd_index = 0;
}
if (spd_file_len < sizeof(peid->spd_data[0]))
die("Missing SPD data.");
/* Index 0-2 are 4GB config with both CH0 and CH1
* Index 3-5 are 2GB config with CH0 only
*/
if (spd_index > 2)
peid->dimm_channel1_disabled = 3;
memcpy(peid->spd_data[0],
spd_file +
spd_index * sizeof(peid->spd_data[0]),
sizeof(peid->spd_data[0]));
}
/* Copy SPD data for on-board memory */
static void copy_spd(struct pei_data *peid)
{
const int gpio_vector[] = {13, 9, 47, -1};
int spd_index = get_gpios(gpio_vector);
char *spd_file;
size_t spd_file_len;
printk(BIOS_DEBUG, "SPD index %d\n", spd_index);
spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin",
CBFS_TYPE_SPD, &spd_file_len);
if (!spd_file)
die("SPD data not found.");
if (spd_file_len <
((spd_index + 1) * sizeof(peid->spd_data[0]))) {
printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
spd_index = 0;
}
if (spd_file_len < sizeof(peid->spd_data[0]))
die("Missing SPD data.");
memcpy(peid->spd_data[0],
spd_file +
spd_index * sizeof(peid->spd_data[0]),
sizeof(peid->spd_data[0]));
}
/* Copy SPD data for on-board memory */
static void copy_spd(struct pei_data *peid)
{
char *spd_file;
size_t spd_file_len;
int spd_index = 0; /* No GPIO selection, force index 0 for now */
printk(BIOS_DEBUG, "SPD index %d\n", spd_index);
spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab,
&spd_file_len);
if (!spd_file)
die("SPD data not found.");
if (spd_file_len <
((spd_index + 1) * sizeof(peid->spd_data[0]))) {
printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
spd_index = 0;
}
if (spd_file_len < sizeof(peid->spd_data[0]))
die("Missing SPD data.");
memcpy(peid->spd_data[0],
spd_file +
spd_index * sizeof(peid->spd_data[0]),
sizeof(peid->spd_data[0]));
}
/* FIXME: we would like GFX disable for fam14 too for headless systems. */
AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt)
{
GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt;
pVbiosImageInfo->ImagePtr = cbfs_get_file_content(
CBFS_DEFAULT_MEDIA, "pci"CONFIG_VGA_BIOS_ID".rom",
CBFS_TYPE_OPTIONROM, NULL);
/* printk(BIOS_DEBUG, "IMGptr=%x\n", pVbiosImageInfo->ImagePtr); */
return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS;
}
void vbe_set_graphics(void)
{
u8 rval;
vbe_info_t info;
rval = vbe_info(&info);
if (rval != 0)
return;
DEBUG_PRINTF_VBE("VbeSignature: %s\n", info.signature);
DEBUG_PRINTF_VBE("VbeVersion: 0x%04x\n", info.version);
DEBUG_PRINTF_VBE("OemString: %s\n", info.oem_string_ptr);
DEBUG_PRINTF_VBE("Capabilities:\n");
DEBUG_PRINTF_VBE("\tDAC: %s\n",
(info.capabilities & 0x1) ==
0 ? "fixed 6bit" : "switchable 6/8bit");
DEBUG_PRINTF_VBE("\tVGA: %s\n",
(info.capabilities & 0x2) ==
0 ? "compatible" : "not compatible");
DEBUG_PRINTF_VBE("\tRAMDAC: %s\n",
(info.capabilities & 0x4) ==
0 ? "normal" : "use blank bit in Function 09h");
mode_info.video_mode = (1 << 14) | CONFIG_FRAMEBUFFER_VESA_MODE;
vbe_get_mode_info(&mode_info);
vbe_set_mode(&mode_info);
#if CONFIG_BOOTSPLASH
unsigned char *framebuffer =
(unsigned char *) le32_to_cpu(mode_info.vesa.phys_base_ptr);
DEBUG_PRINTF_VBE("FRAMEBUFFER: 0x%p\n", framebuffer);
struct jpeg_decdata *decdata;
/* Switching Intel IGD to 1MB video memory will break this. Who
* cares. */
// int imagesize = 1024*768*2;
unsigned char *jpeg = cbfs_get_file_content(CBFS_DEFAULT_MEDIA,
"bootsplash.jpg",
CBFS_TYPE_BOOTSPLASH,
NULL);
if (!jpeg) {
DEBUG_PRINTF_VBE("Could not find bootsplash.jpg\n");
return;
}
DEBUG_PRINTF_VBE("Splash at %p ...\n", jpeg);
dump(jpeg, 64);
decdata = malloc(sizeof(*decdata));
int ret = 0;
DEBUG_PRINTF_VBE("Decompressing boot splash screen...\n");
ret = jpeg_decode(jpeg, framebuffer, 1024, 768, 16, decdata);
DEBUG_PRINTF_VBE("returns %x\n", ret);
#endif
}
int rmodule_stage_load_from_cbfs(struct rmod_stage_load *rsl)
{
struct cbfs_stage *stage;
stage = cbfs_get_file_content(CBFS_DEFAULT_MEDIA,
rsl->prog->name, CBFS_TYPE_STAGE, NULL);
if (stage == NULL)
return -1;
return rmodule_stage_load(rsl, stage);
}
/*
* Load archive into RAM
*/
static VbError_t load_archive(const char *name, struct directory **dest)
{
struct directory *dir;
struct dentry *entry;
size_t size;
int i;
printf("%s: loading %s\n", __func__, name);
*dest = NULL;
/* load archive from cbfs */
dir = cbfs_get_file_content(ro_cbfs, name, CBFS_TYPE_RAW, &size);
if (!dir || !size) {
printf("%s: failed to load %s\n", __func__, name);
return VBERROR_INVALID_BMPFV;
}
/* convert endianness of archive header */
dir->count = le32toh(dir->count);
dir->size = le32toh(dir->size);
/* validate the total size */
if (dir->size != size) {
printf("%s: archive size does not match\n", __func__);
return VBERROR_INVALID_BMPFV;
}
/* validate magic field */
if (memcmp(dir->magic, CBAR_MAGIC, sizeof(CBAR_MAGIC))) {
printf("%s: invalid archive magic\n", __func__);
return VBERROR_INVALID_BMPFV;
}
/* validate count field */
if (get_first_offset(dir) > dir->size) {
printf("%s: invalid count\n", __func__);
return VBERROR_INVALID_BMPFV;
}
/* convert endianness of file headers */
entry = get_first_dentry(dir);
for (i = 0; i < dir->count; i++) {
entry[i].offset = le32toh(entry[i].offset);
entry[i].size = le32toh(entry[i].size);
}
*dest = dir;
return VBERROR_SUCCESS;
}
static int cbfs_locate_payload(struct prog *payload)
{
void *buffer;
size_t size;
const int type = CBFS_TYPE_PAYLOAD;
buffer = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, payload->name,
type, &size);
if (buffer == NULL)
return -1;
prog_set_area(payload, buffer, size);
return 0;
}
/**
* Find PEI executable in coreboot filesystem and execute it.
*
* @param pei_data: configuration data for UEFI PEI reference code
*/
void sdram_initialize(struct pei_data *pei_data)
{
unsigned long entry;
printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n");
/*
* Do not pass MRC data in for recovery mode boot,
* Always pass it in for S3 resume.
*/
if (!recovery_mode_enabled() || pei_data->boot_mode == 2)
prepare_mrc_cache(pei_data);
/* If MRC data is not found we cannot continue S3 resume. */
if (pei_data->boot_mode == 2 && !pei_data->mrc_input) {
post_code(POST_RESUME_FAILURE);
printk(BIOS_DEBUG, "Giving up in sdram_initialize: "
"No MRC data\n");
outb(0x6, 0xcf9);
halt();
}
/* Pass console handler in pei_data */
pei_data->tx_byte = do_putchar;
/* Locate and call UEFI System Agent binary. */
entry = (unsigned long)cbfs_get_file_content(
CBFS_DEFAULT_MEDIA, "mrc.bin", CBFS_TYPE_MRC, NULL);
if (entry) {
int rv;
asm volatile (
"call *%%ecx\n\t"
:"=a" (rv) : "c" (entry), "a" (pei_data));
if (rv) {
switch (rv) {
case -1:
printk(BIOS_ERR, "PEI version mismatch.\n");
break;
case -2:
printk(BIOS_ERR, "Invalid memory frequency.\n");
break;
default:
printk(BIOS_ERR, "MRC returned %x.\n", rv);
}
die("Nonzero MRC return value.\n");
}
} else {
static int cbfs_locate_payload(struct payload *payload)
{
void *buffer;
size_t size;
const int type = CBFS_TYPE_PAYLOAD;
buffer = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, payload->name,
type, &size);
if (buffer == NULL)
return -1;
payload->backing_store.data = buffer;
payload->backing_store.size = size;
return 0;
}
/* Copy SPD data for on-board memory */
static void copy_spd(struct pei_data *peid)
{
const int gpio_vector[] = {13, 9, 47, -1};
int spd_index = get_gpios(gpio_vector);
char *spd_file;
size_t spd_file_len;
printk(BIOS_DEBUG, "SPD index %d\n", spd_index);
spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab,
&spd_file_len);
if (!spd_file)
die("SPD data not found.");
switch (google_chromeec_get_board_version()) {
case PEPPY_BOARD_VERSION_PROTO:
/* Index 0 is 2GB config with CH0 only. */
if (spd_index == 0)
peid->dimm_channel1_disabled = 3;
break;
case PEPPY_BOARD_VERSION_EVT:
default:
/* Index 0-2 are 4GB config with both CH0 and CH1.
* Index 4-6 are 2GB config with CH0 only. */
if (spd_index > 3)
peid->dimm_channel1_disabled = 3;
break;
}
if (spd_file_len <
((spd_index + 1) * sizeof(peid->spd_data[0]))) {
printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
spd_index = 0;
}
if (spd_file_len < sizeof(peid->spd_data[0]))
die("Missing SPD data.");
memcpy(peid->spd_data[0],
spd_file +
spd_index * sizeof(peid->spd_data[0]),
sizeof(peid->spd_data[0]));
}
static int fetch_file_from_cbfs( char *filename, char destination[MAX_DEVICES][MAX_LENGTH], u8 *line_count) {
char *cbfs_dat, tmp;
int cbfs_offset = 0, char_cnt = 0;
size_t cbfs_length;
cbfs_dat = (char *) cbfs_get_file_content( CBFS_DEFAULT_MEDIA, filename, CBFS_TYPE_RAW, &cbfs_length );
if (!cbfs_dat) {
printf("Error: file [%%s] not found!\n");
return 1;
}
//count up the lines and display
*line_count = 0;
while (1) {
tmp = *(cbfs_dat + cbfs_offset++);
destination[*line_count][char_cnt] = tmp;
if (tmp == NEWLINE) {
(*line_count)++;
char_cnt = 0;
}
else if ((tmp == NUL) || (cbfs_offset > cbfs_length))
break;
else
char_cnt++;
if ( *line_count > MAX_DEVICES) {
printf("aborting due to excessive line_count\n");
break;
}
if ( char_cnt > MAX_LENGTH) {
printf("aborting due to excessive char count\n");
break;
}
if ( cbfs_offset > (MAX_LENGTH*MAX_DEVICES)) {
printf("aborting due to excessive cbfs ptr length\n");
break;
}
}
return 0;
}
void raminit(struct mrc_params *mp, int prev_sleep_state)
{
int ret;
mrc_wrapper_entry_t mrc_entry;
const struct mrc_saved_data *cache;
/* Fill in default entries. */
mp->version = MRC_PARAMS_VER;
mp->console_out = &send_to_console;
mp->prev_sleep_state = prev_sleep_state;
if (!mrc_cache_get_current(&cache)) {
mp->saved_data_size = cache->size;
mp->saved_data = &cache->data[0];
} else {
printk(BIOS_DEBUG, "No MRC cache found.\n");
}
mrc_entry = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab,
NULL);
if (mrc_entry == NULL) {
printk(BIOS_DEBUG, "Couldn't find mrc.bin\n");
return;
}
if (mp->mainboard.dram_info_location == DRAM_INFO_SPD_SMBUS)
enable_smbus();
ret = mrc_entry(mp);
cbmem_initialize_empty();
printk(BIOS_DEBUG, "MRC Wrapper returned %d\n", ret);
printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", mp->data_to_save,
mp->data_to_save_size);
if (mp->data_to_save != NULL && mp->data_to_save_size > 0)
mrc_cache_stash_data(mp->data_to_save, mp->data_to_save_size);
}
const void *agesawrapper_locate_module (const CHAR8 name[8])
{
struct cbfs_media media;
struct cbfs_file* file;
const void* agesa;
const AMD_IMAGE_HEADER* image;
const AMD_MODULE_HEADER* module;
size_t file_size;
if (init_default_cbfs_media(&media))
return NULL;
file = cbfs_get_file(&media, (const char*)CONFIG_CBFS_AGESA_NAME);
if (!file)
return NULL;
agesa = cbfs_get_file_content(&media, (const char*)CONFIG_CBFS_AGESA_NAME,
ntohl(file->type), &file_size);
if (!agesa)
return NULL;
image = LibAmdLocateImage(agesa, agesa + file_size - 1, 4096, name);
module = (AMD_MODULE_HEADER*)image->ModuleInfoOffset;
return module;
}
unsigned long write_coreboot_table(
unsigned long low_table_start, unsigned long low_table_end,
unsigned long rom_table_start, unsigned long rom_table_end)
{
struct lb_header *head;
struct lb_memory *mem;
if (low_table_start || low_table_end) {
printk(BIOS_DEBUG, "Writing table forward entry at 0x%08lx\n",
low_table_end);
head = lb_table_init(low_table_end);
lb_forward(head, (struct lb_header*)rom_table_end);
low_table_end = (unsigned long) lb_table_fini(head, 0);
printk(BIOS_DEBUG, "Table forward entry ends at 0x%08lx.\n",
low_table_end);
low_table_end = ALIGN(low_table_end, 4096);
printk(BIOS_DEBUG, "... aligned to 0x%08lx\n", low_table_end);
}
printk(BIOS_DEBUG, "Writing coreboot table at 0x%08lx\n",
rom_table_end);
head = lb_table_init(rom_table_end);
rom_table_end = (unsigned long)head;
printk(BIOS_DEBUG, "rom_table_end = 0x%08lx\n", rom_table_end);
rom_table_end = ALIGN(rom_table_end, (64 * 1024));
printk(BIOS_DEBUG, "... aligned to 0x%08lx\n", rom_table_end);
#if CONFIG_USE_OPTION_TABLE
{
struct cmos_option_table *option_table = cbfs_get_file_content(
CBFS_DEFAULT_MEDIA, "cmos_layout.bin",
CBFS_COMPONENT_CMOS_LAYOUT);
if (option_table) {
struct lb_record *rec_dest = lb_new_record(head);
/* Copy the option config table, it's already a lb_record... */
memcpy(rec_dest, option_table, option_table->size);
/* Create cmos checksum entry in coreboot table */
lb_cmos_checksum(head);
} else {
printk(BIOS_ERR, "cmos_layout.bin could not be found!\n");
}
}
#endif
/* The Linux kernel assumes this region is reserved */
/* Record where RAM is located */
mem = build_lb_mem(head);
if (low_table_start || low_table_end) {
/* Record the mptable and the the lb_table.
* (This will be adjusted later) */
lb_add_memory_range(mem, LB_MEM_TABLE,
low_table_start, low_table_end - low_table_start);
}
/* Record the pirq table, acpi tables, and maybe the mptable. However,
* these only need to be added when the rom_table is sitting below
* 1MiB. If it isn't that means high tables are being written.
* The code below handles high tables correctly. */
if (rom_table_end <= (1 << 20))
lb_add_memory_range(mem, LB_MEM_TABLE,
rom_table_start, rom_table_end - rom_table_start);
#if CONFIG_DYNAMIC_CBMEM
cbmem_add_lb_mem(mem);
#else /* CONFIG_DYNAMIC_CBMEM */
lb_add_memory_range(mem, LB_MEM_TABLE,
high_tables_base, high_tables_size);
#endif /* CONFIG_DYNAMIC_CBMEM */
/* Add reserved regions */
add_lb_reserved(mem);
lb_dump_memory_ranges(mem);
/* Note:
* I assume that there is always memory at immediately after
* the low_table_end. This means that after I setup the coreboot table.
* I can trivially fixup the reserved memory ranges to hold the correct
* size of the coreboot table.
*/
/* Record our motherboard */
lb_mainboard(head);
/* Record the serial port, if present */
lb_serial(head);
/* Record our console setup */
lb_console(head);
/* Record our various random string information */
lb_strings(head);
/* Record our framebuffer */
lb_framebuffer(head);
#if CONFIG_CHROMEOS
/* Record our GPIO settings (ChromeOS specific) */
lb_gpios(head);
/* pass along the VDAT buffer adress */
lb_vdat(head);
/* pass along VBNV offsets in CMOS */
lb_vbnv(head);
/* pass along the vboot_handoff address. */
lb_vboot_handoff(head);
#endif
add_cbmem_pointers(head);
/* Remember where my valid memory ranges are */
return lb_table_fini(head, 1);
}
static void mainboard_init(device_t dev)
{
u32 search_address = 0x0;
size_t search_length = -1;
u16 io_base = 0;
struct device *ethernet_dev = NULL;
#if CONFIG_CHROMEOS
char **vpd_region_ptr = NULL;
search_length = find_fmap_entry("RO_VPD", (void **)vpd_region_ptr);
search_address = (unsigned long)(*vpd_region_ptr);
#else
void *vpd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "vpd.bin",
CBFS_TYPE_RAW, &search_length);
if (vpd_file) {
search_address = (unsigned long)vpd_file;
} else {
search_length = -1;
search_address = 0;
}
#endif
/* Initialize the Embedded Controller */
butterfly_ec_init();
/* Program EC Keyboard locale based on VPD data */
program_keyboard_type(search_address, search_length);
/* Get NIC's IO base address */
ethernet_dev = dev_find_device(BUTTERFLY_NIC_VENDOR_ID,
BUTTERFLY_NIC_DEVICE_ID, dev);
if (ethernet_dev != NULL) {
io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe;
/*
* Battery life time - LAN PCIe should enter ASPM L1 to save
* power when LAN connection is idle.
* enable CLKREQ: LAN pci config space 0x81h=01
*/
pci_write_config8(ethernet_dev, 0x81, 0x01);
}
if (io_base) {
/* Program MAC address based on VPD data */
program_mac_address(io_base, search_address, search_length);
/*
* Program NIC LEDS
*
* RTL8105E Series EEPROM-Less Application Note,
* Section 5.6 LED Mode Configuration
*
* Step1: Write C0h to I/O register 0x50 via byte access to
* disable 'register protection'
* Step2: Write xx001111b to I/O register 0x52 via byte access
* (bit7 is LEDS1 and bit6 is LEDS0)
* Step3: Write 0x00 to I/O register 0x50 via byte access to
* enable 'register protection'
*/
outb(0xc0, io_base + 0x50); /* Disable protection */
outb((BUTTERFLY_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52);
outb(0x00, io_base + 0x50); /* Enable register protection */
}
}
/**
* Find PEI executable in coreboot filesystem and execute it.
*
* @param pei_data: configuration data for UEFI PEI reference code
*/
void sdram_initialize(struct pei_data *pei_data)
{
struct sys_info sysinfo;
int (*entry) (struct pei_data *pei_data) __attribute__ ((regparm(1)));
report_platform_info();
/* Wait for ME to be ready */
intel_early_me_init();
intel_early_me_uma_size();
printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n");
memset(&sysinfo, 0, sizeof(sysinfo));
sysinfo.boot_path = pei_data->boot_mode;
/*
* Do not pass MRC data in for recovery mode boot,
* Always pass it in for S3 resume.
*/
if (!recovery_mode_enabled() || pei_data->boot_mode == 2)
prepare_mrc_cache(pei_data);
/* If MRC data is not found we cannot continue S3 resume. */
if (pei_data->boot_mode == 2 && !pei_data->mrc_input) {
printk(BIOS_DEBUG, "Giving up in sdram_initialize: No MRC data\n");
outb(0x6, 0xcf9);
halt();
}
/* Pass console handler in pei_data */
pei_data->tx_byte = do_putchar;
/* Locate and call UEFI System Agent binary. */
entry = cbfs_get_file_content(
CBFS_DEFAULT_MEDIA, "mrc.bin", CBFS_TYPE_MRC, NULL);
if (entry) {
int rv;
rv = entry (pei_data);
if (rv) {
switch (rv) {
case -1:
printk(BIOS_ERR, "PEI version mismatch.\n");
break;
case -2:
printk(BIOS_ERR, "Invalid memory frequency.\n");
break;
default:
printk(BIOS_ERR, "MRC returned %x.\n", rv);
}
die("Nonzero MRC return value.\n");
}
} else {
die("UEFI PEI System Agent not found.\n");
}
#if CONFIG_USBDEBUG_IN_ROMSTAGE
/* mrc.bin reconfigures USB, so reinit it to have debug */
usbdebug_init();
#endif
/* For reference print the System Agent version
* after executing the UEFI PEI stage.
*/
u32 version = MCHBAR32(0x5034);
printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n",
version >> 24 , (version >> 16) & 0xff,
(version >> 8) & 0xff, version & 0xff);
/* Send ME init done for SandyBridge here. This is done
* inside the SystemAgent binary on IvyBridge. */
if (BASE_REV_SNB ==
(pci_read_config16(PCI_CPU_DEVICE, PCI_DEVICE_ID) & BASE_REV_MASK))
intel_early_me_init_done(ME_INIT_STATUS_SUCCESS);
else
intel_early_me_status();
post_system_agent_init(pei_data);
report_memory_config();
}
int main(void) {
char bootlist[MAX_DEVICES][MAX_LENGTH];
int i;
char key;
u8 max_lines = 0;
u8 bootlist_def_ln = 0;
u8 bootlist_map_ln = 0;
char *ipxe_str;
char *scon_str;
#ifdef CONFIG_USB /* this needs to be done in order to use the USB keyboard */
usb_initialize();
noecho(); /* don't echo keystrokes */
#endif
printf("\n*********************************************************************");
printf("\n*** Sortbootorder payload ver 1.1 Sage Electronic Engineering *");
printf("\n*********************************************************************\n");
// Find out where the bootorder file is in rom
char *tmp = cbfs_get_file_content( CBFS_DEFAULT_MEDIA, BOOTORDER_FILE, CBFS_TYPE_RAW, NULL );
flash_address = (int)tmp;
if ((u32)tmp & 0xfff)
printf("Warning: The bootorder file is not 4k aligned!\n");
// Get required files from CBFS
fetch_file_from_cbfs( BOOTORDER_FILE, bootlist, &max_lines );
fetch_file_from_cbfs( BOOTORDER_DEF, bootlist_def, &bootlist_def_ln );
fetch_file_from_cbfs( BOOTORDER_MAP, bootlist_map, &bootlist_map_ln );
// Init ipxe and serial status
ipxe_str = cbfs_find_string("pxen", BOOTORDER_FILE);
ipxe_str += strlen("pxen");
ipxe_toggle = ipxe_str ? strtoul(ipxe_str, NULL, 10) : 1;
scon_str = cbfs_find_string("scon", BOOTORDER_FILE);
scon_str += strlen("scon");
serial_toggle = scon_str ? strtoul(scon_str, NULL, 10) : 1;
show_boot_device_list( bootlist, max_lines, bootlist_def_ln );
int_ids( bootlist, max_lines, bootlist_def_ln );
// Start main loop for user input
while (1) {
printf("\n> ");
key = getchar();
printf("%c\n\n\n", key);
switch(key) {
case 'R':
for (i = 0; i < max_lines && i < bootlist_def_ln; i++ )
copy_list_line(&(bootlist_def[i][0]), &(bootlist[i][0]));
int_ids( bootlist, max_lines, bootlist_def_ln );
break;
case 'T':
serial_toggle ^= 0x1;
break;
case 'N':
ipxe_toggle ^= 0x1;
break;
case 'U':
usb_toggle ^= 0x1;
break;
case 'E':
update_tag_value(bootlist, max_lines, "scon", serial_toggle + '0');
update_tag_value(bootlist, max_lines, "pxen", ipxe_toggle + '0');
save_flash( bootlist, max_lines );
// fall through to exit ...
case 'X':
printf("\nExiting ...");
outb(0x06, 0x0cf9); /* reset */
break;
default:
if (key >= 'a' && key <= 'm' ) {
move_boot_list( bootlist, get_line_number(max_lines,key), max_lines );
}
break;
}
show_boot_device_list( bootlist, max_lines, bootlist_def_ln );
}
return 0; /* should never get here! */
}
unsigned long write_coreboot_table(
unsigned long low_table_start, unsigned long low_table_end,
unsigned long rom_table_start, unsigned long rom_table_end)
{
struct lb_header *head;
if (low_table_start || low_table_end) {
printk(BIOS_DEBUG, "Writing table forward entry at 0x%08lx\n",
low_table_end);
head = lb_table_init(low_table_end);
lb_forward(head, (struct lb_header*)rom_table_end);
low_table_end = (unsigned long) lb_table_fini(head);
printk(BIOS_DEBUG, "Table forward entry ends at 0x%08lx.\n",
low_table_end);
low_table_end = ALIGN(low_table_end, 4096);
printk(BIOS_DEBUG, "... aligned to 0x%08lx\n", low_table_end);
}
printk(BIOS_DEBUG, "Writing coreboot table at 0x%08lx\n",
rom_table_end);
head = lb_table_init(rom_table_end);
rom_table_end = (unsigned long)head;
printk(BIOS_DEBUG, "rom_table_end = 0x%08lx\n", rom_table_end);
rom_table_end = ALIGN(rom_table_end, (64 * 1024));
printk(BIOS_DEBUG, "... aligned to 0x%08lx\n", rom_table_end);
#if CONFIG_USE_OPTION_TABLE
{
struct cmos_option_table *option_table = cbfs_get_file_content(
CBFS_DEFAULT_MEDIA, "cmos_layout.bin",
CBFS_COMPONENT_CMOS_LAYOUT, NULL);
if (option_table) {
struct lb_record *rec_dest = lb_new_record(head);
/* Copy the option config table, it's already a lb_record... */
memcpy(rec_dest, option_table, option_table->size);
} else {
printk(BIOS_ERR, "cmos_layout.bin could not be found!\n");
}
}
#endif
/* Initialize the memory map at boot time. */
bootmem_init();
if (low_table_start || low_table_end) {
uint64_t size = low_table_end - low_table_start;
/* Record the mptable and the the lb_table.
* (This will be adjusted later) */
bootmem_add_range(low_table_start, size, LB_MEM_TABLE);
}
/* Record the pirq table, acpi tables, and maybe the mptable. However,
* these only need to be added when the rom_table is sitting below
* 1MiB. If it isn't that means high tables are being written.
* The code below handles high tables correctly. */
if (rom_table_end <= (1 << 20)) {
uint64_t size = rom_table_end - rom_table_start;
bootmem_add_range(rom_table_start, size, LB_MEM_TABLE);
}
/* No other memory areas can be added after the memory table has been
* committed as the entries won't show up in the serialize mem table. */
bootmem_write_memory_table(lb_memory(head));
/* Record our motherboard */
lb_mainboard(head);
/* Record the serial ports and consoles */
#if CONFIG_CONSOLE_SERIAL
uart_fill_lb(head);
#endif
#if CONFIG_CONSOLE_USB
lb_add_console(LB_TAG_CONSOLE_EHCI, head);
#endif
/* Record our various random string information */
lb_strings(head);
/* Record our framebuffer */
lb_framebuffer(head);
#if CONFIG_CHROMEOS
/* Record our GPIO settings (ChromeOS specific) */
lb_gpios(head);
/* pass along the VDAT buffer address */
lb_vdat(head);
/* pass along VBNV offsets in CMOS */
lb_vbnv(head);
/* pass along the vboot_handoff address. */
lb_vboot_handoff(head);
#endif
add_cbmem_pointers(head);
/* Add board-specific table entries, if any. */
lb_board(head);
/* Remember where my valid memory ranges are */
return lb_table_fini(head);
}
