/** * Initalizes both (Rx/Tx) DMA fifo's and related management structures */ static int ccat_eth_priv_init_dma(struct ccat_eth_priv *priv) { struct ccat_dma_mem *const dma = &priv->dma_mem; struct pci_dev *const pdev = priv->func->ccat->pdev; void __iomem *const bar_2 = priv->func->ccat->bar_2; const u8 rx_chan = priv->func->info.rx_dma_chan; const u8 tx_chan = priv->func->info.tx_dma_chan; int status = 0; dma->dev = &pdev->dev; dma->size = CCAT_ALIGNMENT * 3; dma->base = dma_zalloc_coherent(dma->dev, dma->size, &dma->phys, GFP_KERNEL); if (!dma->base || !dma->phys) { pr_err("init DMA memory failed.\n"); return -ENOMEM; } priv->rx_fifo.ops = &dma_rx_fifo_ops; status = ccat_dma_init(dma, rx_chan, bar_2, &priv->rx_fifo); if (status) { pr_info("init RX DMA memory failed.\n"); ccat_dma_free(priv); return status; } priv->tx_fifo.ops = &dma_tx_fifo_ops; status = ccat_dma_init(dma, tx_chan, bar_2, &priv->tx_fifo); if (status) { pr_info("init TX DMA memory failed.\n"); ccat_dma_free(priv); return status; } return ccat_hw_disable_mac_filter(priv); }
/** * Stop both (Rx/Tx) DMA fifo's and free related management structures */ static void ccat_eth_priv_free_dma(struct ccat_eth_priv *priv) { /* reset hw fifo's */ iowrite32(0, priv->rx_fifo.reg + 0x8); iowrite32(0, priv->tx_fifo.reg + 0x8); wmb(); /* release dma */ ccat_dma_free(&priv->rx_fifo.dma); ccat_dma_free(&priv->tx_fifo.dma); }
static void ccat_eth_priv_free(struct ccat_eth_priv *priv) { /* reset hw fifo's */ ccat_eth_fifo_hw_reset(&priv->rx_fifo); ccat_eth_fifo_hw_reset(&priv->tx_fifo); /* release dma */ ccat_dma_free(priv); }
/** * Initalizes both (Rx/Tx) DMA fifo's and related management structures */ static int ccat_eth_priv_init_dma(struct ccat_eth_priv *priv) { if (ccat_eth_dma_fifo_init (&priv->rx_fifo, priv->reg.rx_fifo, ccat_eth_rx_fifo_add, priv->info.rx_dma_chan, priv)) { pr_warn("init Rx DMA fifo failed.\n"); return -1; } if (ccat_eth_dma_fifo_init (&priv->tx_fifo, priv->reg.tx_fifo, ccat_eth_tx_fifo_add_free, priv->info.tx_dma_chan, priv)) { pr_warn("init Tx DMA fifo failed.\n"); ccat_dma_free(&priv->rx_fifo.dma); return -1; } /* disable MAC filter */ iowrite8(0, priv->reg.mii + 0x8 + 6); wmb(); return 0; }