/** * @brief Interrupt simulation. */ void ChkIntSources(void) { LARGE_INTEGER n; #if HAL_USE_SERIAL if (sd_lld_interrupt_pending()) { dbg_check_lock(); if (chSchIsPreemptionRequired()) chSchDoReschedule(); dbg_check_unlock(); return; } #endif /* Interrupt Timer simulation (10ms interval).*/ QueryPerformanceCounter(&n); if (n.QuadPart > nextcnt.QuadPart) { nextcnt.QuadPart += slice.QuadPart; CH_IRQ_PROLOGUE(); chSysLockFromIsr(); chSysTimerHandlerI(); chSysUnlockFromIsr(); CH_IRQ_EPILOGUE(); dbg_check_lock(); if (chSchIsPreemptionRequired()) chSchDoReschedule(); dbg_check_unlock(); } else { /* Avoid CPU spinning */ Sleep(1); } }
/** * @brief Process system timer interrupts, if present. * * @notapi */ static void systimer_serve_interrupt( void ) { // Update the system time chSysLockFromIsr(); chSysTimerHandlerI(); chSysUnlockFromIsr(); // Clear timer interrupt ARM_TIMER_CLI = 0; }
/* * Timer 0 IRQ handling here. */ static CH_IRQ_HANDLER(T0IrqHandler) { CH_IRQ_PROLOGUE(); T0IR = 1; /* Clear interrupt on match MR0. */ chSysLockFromIsr(); chSysTimerHandlerI(); chSysUnlockFromIsr(); VICVectAddr = 0; CH_IRQ_EPILOGUE(); }
/* * SYS IRQ handling here. */ static CH_IRQ_HANDLER(SYSIrqHandler) { CH_IRQ_PROLOGUE(); if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) { (void) AT91C_BASE_PITC->PITC_PIVR; chSysLockFromIsr(); chSysTimerHandlerI(); chSysUnlockFromIsr(); } AT91C_BASE_AIC->AIC_EOICR = 0; CH_IRQ_EPILOGUE(); }
/* * SYS IRQ handling here. */ static CH_IRQ_HANDLER(SYSIrqHandler) { CH_IRQ_PROLOGUE(); if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) { (void) AT91C_BASE_PITC->PITC_PIVR; chSysLockFromIsr(); chSysTimerHandlerI(); chSysUnlockFromIsr(); } #if USE_SAM7_DBGU_UART if (AT91C_BASE_DBGU->DBGU_CSR & (AT91C_US_RXRDY | AT91C_US_TXRDY | AT91C_US_PARE | AT91C_US_FRAME | AT91C_US_OVRE | AT91C_US_RXBRK)) { sd_lld_serve_interrupt(&SDDBG); } #endif AT91C_BASE_AIC->AIC_EOICR = 0; CH_IRQ_EPILOGUE(); }