void mt_clr_rwi (uint32 un)
{
mt_rwi &= ~(1u << un); /* clear */
if (mt_rwi != 0) /* more? */
chan_set_dvi (mt_dib.dva);
else if (chan_chk_chi (mt_dib.dva) < 0) /* any int? */
chan_clr_chi (mt_dib.dva); /* clr INP */
return;
}
uint32 lp_disp (uint32 op, uint32 dva, uint32 *dvst)
{
switch (op) { /* case on op */
case OP_SIO: /* start I/O */
*dvst = lp_tio_status (); /* get status */
if ((*dvst & DVS_DST) == 0) { /* idle? */
lp_cmd = LPS_INIT; /* start dev thread */
sim_activate (&lp_unit, chan_ctl_time);
}
break;
case OP_TIO: /* test status */
*dvst = lp_tio_status (); /* return status */
break;
case OP_TDV: /* test status */
*dvst = lp_tdv_status (); /* return status */
break;
case OP_HIO: /* halt I/O */
chan_clr_chi (lp_dib.dva); /* clear int */
*dvst = lp_tio_status (); /* get status */
if ((*dvst & DVS_DST) != 0) { /* busy? */
sim_cancel (&lp_unit); /* stop dev thread */
chan_uen (lp_dib.dva); /* uend */
}
break;
case OP_AIO: /* acknowledge int */
chan_clr_chi (lp_dib.dva); /* clear int */
*dvst = lp_lastcmd & LPS_INT; /* int requested */
lp_lastcmd = 0;
break;
default:
*dvst = 0;
return SCPE_IERR;
}
return 0;
}
uint32 pt_disp (uint32 op, uint32 dva, uint32 *dvst)
{
switch (op) { /* case on op */
case OP_SIO: /* start I/O */
*dvst = pt_tio_status (); /* get status */
if ((*dvst & DVS_DST) == 0) { /* idle? */
pt_cmd = PTS_INIT; /* start dev thread */
sim_activate (&pt_unit[PTR], chan_ctl_time);
}
break;
case OP_TIO: /* test status */
*dvst = pt_tio_status (); /* return status */
break;
case OP_TDV: /* test status */
*dvst = pt_tdv_status (); /* return status */
break;
case OP_HIO: /* halt I/O */
chan_clr_chi (pt_dib.dva); /* clr int*/
*dvst = pt_tio_status (); /* get status */
if ((*dvst & DVS_DST) != 0) { /* busy? */
sim_cancel (&pt_unit[PTR]); /* stop dev thread */
chan_uen (pt_dib.dva); /* uend */
}
break;
case OP_AIO: /* acknowledge int */
chan_clr_chi (pt_dib.dva); /* clr int*/
*dvst = 0; /* no status */
break;
default:
*dvst = 0;
return SCPE_IERR;
}
return 0;
}
uint32 mt_disp (uint32 op, uint32 dva, uint32 *dvst)
{
uint32 un = DVA_GETUNIT (dva);
UNIT *uptr = &mt_unit[un];
if ((un >= MT_NUMDR) || /* inv unit num? */
(uptr-> flags & UNIT_DIS)) /* disabled unit? */
return DVT_NODEV;
switch (op) { /* case on op */
case OP_SIO: /* start I/O */
*dvst = mt_tio_status (un); /* get status */
if ((*dvst & (DVS_CST|DVS_DST)) == 0) { /* ctrl + dev idle? */
uptr->UCMD = MCM_INIT; /* start dev thread */
sim_activate (uptr, chan_ctl_time);
}
break;
case OP_TIO: /* test status */
*dvst = mt_tio_status (un); /* return status */
break;
case OP_TDV: /* test status */
*dvst = mt_tdv_status (un); /* return status */
break;
case OP_HIO: /* halt I/O */
*dvst = mt_tio_status (un); /* get status */
if ((int32) un == chan_chk_chi (dva)) /* halt active ctlr int? */
chan_clr_chi (dva); /* clear ctlr int */
if (sim_is_active (uptr)) { /* chan active? */
sim_cancel (uptr); /* stop unit */
chan_uen (dva); /* uend */
}
mt_clr_rwi (un); /* clear rewind int */
sim_cancel (uptr + MT_REW); /* cancel rewind */
break;
case OP_AIO: /* acknowledge int */
un = mt_clr_int (mt_dib.dva); /* clr int, get unit */
*dvst = (mt_tdv_status (un) & MTAI_MASK) | /* device status */
(un & MTAI_INT) | /* device int flag */
((un & DVA_M_UNIT) << DVT_V_UN); /* unit number */
break;
default:
*dvst = 0;
return SCPE_IERR;
}
return 0;
}
int32 mt_clr_int (uint32 dva)
{
int32 iu;
if ((iu = chan_clr_chi (dva)) >= 0) { /* chan int? clear */
if (mt_rwi != 0) /* dev ints? */
chan_set_dvi (dva); /* set them */
return iu;
}
for (iu = 0; iu < MT_NUMDR; iu++) { /* rewind int? */
if (mt_rwi & (1u << iu)) {
mt_clr_rwi ((uint32) iu);
return (iu | MTAI_INT);
}
}
return 0;
}
