void LIR_Assembler::emit_op0(LIR_Op0* op) {
switch (op->code()) {
case lir_word_align: {
_masm->align(BytesPerWord);
break;
}
case lir_nop:
assert(op->info() == NULL, "not supported");
_masm->nop();
break;
case lir_label:
Unimplemented();
break;
case lir_build_frame:
build_frame();
break;
case lir_std_entry:
// init offsets
offsets()->set_value(CodeOffsets::OSR_Entry, _masm->offset());
_masm->align(CodeEntryAlignment);
if (needs_icache(compilation()->method())) {
check_icache();
}
offsets()->set_value(CodeOffsets::Verified_Entry, _masm->offset());
_masm->verified_entry();
build_frame();
offsets()->set_value(CodeOffsets::Frame_Complete, _masm->offset());
break;
case lir_osr_entry:
offsets()->set_value(CodeOffsets::OSR_Entry, _masm->offset());
osr_entry();
break;
case lir_24bit_FPU:
set_24bit_FPU();
break;
case lir_reset_FPU:
reset_FPU();
break;
case lir_breakpoint:
breakpoint();
break;
case lir_fpop_raw:
fpop();
break;
case lir_membar:
membar();
break;
case lir_membar_acquire:
membar_acquire();
break;
case lir_membar_release:
membar_release();
break;
case lir_membar_loadload:
membar_loadload();
break;
case lir_membar_storestore:
membar_storestore();
break;
case lir_membar_loadstore:
membar_loadstore();
break;
case lir_membar_storeload:
membar_storeload();
break;
case lir_get_thread:
get_thread(op->result_opr());
break;
default:
ShouldNotReachHere();
break;
}
}
int _tmain(int argc, _TCHAR* argv[])
{
FILE *fp;
FILE *fp2;
int i, j, l, k, type, tag_shift, trace_length;
int icache[32768], dcache[32768];
float ihit_percent, imiss_percent, dmiss_percent, dhit_percent;
unsigned int address, tag, instr, new_tag;
unsigned int masked_addr;
// open trace file for reading
fp = fopen("C:\\gcc_trace2.txt", "r");
if (fp == NULL) printf("data file open error");
trace_length = 1000000;
//First, simulate nonassociative cache//
////////////////////////////////////////
// for(l=256; l <= 32768; l = l * 2){ //go through each cache size of 256 to 32K
//for(l=256; l <= 2048; l = l * 2){ //for testing, just do 256, 512, and 1024 sized caches
l = 128;
for(j=0; j<=l; j++){ //reset caches to 0 to prevent false positives
icache[j] = 0;
dcache[j] = 0;
}
imiss_count = 0;
ihit_count = 0;
dmiss_count = 0;
dhit_count = 0;
//printf("cache reset\n");
(int)tag_shift = (log((double)l))/log((double)2); //this does log2(l)
for (i=0; i<=trace_length; i++) {
// read 1 line of trace file
fscanf_s(fp, "%d %x %x", &type, &address, &instr);
//printf("instruction is %x\n\n", instr );
tag = address >> 2;
new_tag = tag & (l-1); //this is L minus one
////printf("tag shift is %i\n", tag_shift);
////Sleep(500);
//new_tag = tag << ((32 - tag_shift));
//new_tag = new_tag >> ((32 - tag_shift));
//printf("new tag is %i\n", new_tag);
if(type == 2){ //fetch
check_icache(new_tag, icache, address);
}
if(type == 0){ //load instruction
check_dcache(new_tag, icache, address);
}
if(type == 1) ; //store
// Delay a bit to see output
//Sleep(1000);
} //end of file parse loop
ihit_percent = (((float)(ihit_count))/((float)(imiss_count+ihit_count)))*100;
imiss_percent = (((float)(imiss_count))/((float)(imiss_count+ihit_count)))*100;
dhit_percent = (((float)(dhit_count))/((float)(dmiss_count+dhit_count)))*100;
dmiss_percent = (((float)(dmiss_count))/((float)(dmiss_count+dhit_count)))*100;
// printf("I hit count is %i\n", ihit_count);
//printf("I miss count is %i\n", imiss_count);
// printf("l is %i\n", l);
printf("I hit percentage for %i cache is %f\n", l, ihit_percent);
printf("I miss percentage for %i cache is %f\n", l, imiss_percent);
//printf("D hit count is %i\n", dhit_count);
//printf("D miss count is %i\n", dmiss_count);
//printf("D hit percentage for %i cache is %f\n", l, dhit_percent);
printf("D miss percentage for %i cache is %f\n", l, dmiss_percent);
//} //end of loop of caches
Sleep(15000);
return 0;
} //end of main()
