int ccci_modem_suspend(struct platform_device *dev, pm_message_t state)
{
struct ccci_modem *md = (struct ccci_modem *)dev->dev.platform_data;
struct md_cd_ctrl *md_ctrl = (struct md_cd_ctrl *)md->private_data;
CCCI_INF_MSG(md->index, TAG, "AP_BUSY(%p)=%x\n", md_ctrl->ap_ccif_base+APCCIF_BUSY, cldma_read32(md_ctrl->ap_ccif_base, APCCIF_BUSY));
CCCI_INF_MSG(md->index, TAG, "MD_BUSY(%p)=%x\n", md_ctrl->md_ccif_base+APCCIF_BUSY, cldma_read32(md_ctrl->md_ccif_base, APCCIF_BUSY));
return 0;
}
void cldma_dump_register(struct ccci_modem *md)
{
struct md_cd_ctrl *md_ctrl = (struct md_cd_ctrl *)md->private_data;
md_cd_lock_cldma_clock_src(1);
printk("[CCCI%d-DUMP]dump AP CLDMA md_global_con0=0x%x\n",md->index+1, cldma_read32(md_ctrl->md_global_con0, 0) );
printk("[CCCI%d-DUMP]dump AP CLDMA Tx register, active=%x\n",md->index+1, md_ctrl->txq_active);
ccci_mem_dump(md->index, md_ctrl->cldma_ap_pdn_base+CLDMA_AP_UL_START_ADDR_0, CLDMA_AP_UL_CHECKSUM_CHANNEL_ENABLE-CLDMA_AP_UL_START_ADDR_0+4);
printk("[CCCI%d-DUMP]dump AP CLDMA Rx register, active=%x\n",md->index+1, md_ctrl->rxq_active);
ccci_mem_dump(md->index, md_ctrl->cldma_ap_pdn_base+CLDMA_AP_SO_ERROR, CLDMA_AP_DEBUG_ID_EN-CLDMA_AP_SO_ERROR+4);
printk("[CCCI%d-DUMP]dump AP CLDMA MISC register\n",md->index+1);
ccci_mem_dump(md->index, md_ctrl->cldma_ap_pdn_base+CLDMA_AP_L2TISAR0, CLDMA_AP_CHNL_IDLE-CLDMA_AP_L2TISAR0+4);
printk("[CCCI%d-DUMP]dump MD CLDMA Tx register\n",md->index+1);
ccci_mem_dump(md->index, md_ctrl->cldma_md_pdn_base+CLDMA_AP_UL_START_ADDR_0, CLDMA_AP_UL_CHECKSUM_CHANNEL_ENABLE-CLDMA_AP_UL_START_ADDR_0+4);
printk("[CCCI%d-DUMP]dump MD CLDMA Rx register\n",md->index+1);
ccci_mem_dump(md->index, md_ctrl->cldma_md_pdn_base+CLDMA_AP_SO_ERROR, CLDMA_AP_DEBUG_ID_EN-CLDMA_AP_SO_ERROR+4);
printk("[CCCI%d-DUMP]dump MD CLDMA MISC register\n",md->index+1);
ccci_mem_dump(md->index, md_ctrl->cldma_md_pdn_base+CLDMA_AP_L2TISAR0, CLDMA_AP_CHNL_IDLE-CLDMA_AP_L2TISAR0+4);
md_cd_lock_cldma_clock_src(0);
}
void ccci_modem_restore_reg(struct ccci_modem *md)
{
struct md_cd_ctrl *md_ctrl = (struct md_cd_ctrl *)md->private_data;
int i;
unsigned long flags;
if(md->md_state == GATED||md->md_state == RESET||md->md_state == INVALID){
CCCI_INF_MSG(md->index, TAG, "Resume no need reset cldma for md_state=%d\n",md->md_state);
return;
}
cldma_write32(md_ctrl->ap_ccif_base, APCCIF_CON, 0x01); // arbitration
if(cldma_read32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_TQSAR(0)))
{
CCCI_INF_MSG(md->index, TAG, "Resume cldma pdn register: No need ...\n");
}
else
{
CCCI_INF_MSG(md->index, TAG, "Resume cldma pdn register ...11\n");
spin_lock_irqsave(&md_ctrl->cldma_timeout_lock, flags);
cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_HPQR, 0x00);
// set checksum
switch (CHECKSUM_SIZE) {
case 0:
cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_UL_CHECKSUM_CHANNEL_ENABLE, 0);
break;
case 12:
cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_UL_CHECKSUM_CHANNEL_ENABLE, CLDMA_BM_ALL_QUEUE);
cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_UL_CFG, cldma_read32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_UL_CFG)&~0x10);
break;
case 16:
cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_UL_CHECKSUM_CHANNEL_ENABLE, CLDMA_BM_ALL_QUEUE);
cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_UL_CFG, cldma_read32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_UL_CFG)|0x10);
break;
}
// set start address
for(i=0; i<QUEUE_LEN(md_ctrl->txq); i++) {
if(cldma_read32(md_ctrl->cldma_ap_ao_base, CLDMA_AP_TQCPBAK(md_ctrl->txq[i].index)) == 0){
CCCI_INF_MSG(md->index, TAG, "Resume CH(%d) current bak:== 0\n", i);
cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_TQSAR(md_ctrl->txq[i].index), md_ctrl->txq[i].tr_done->gpd_addr);
cldma_write32(md_ctrl->cldma_ap_ao_base, CLDMA_AP_TQSABAK(md_ctrl->txq[i].index), md_ctrl->txq[i].tr_done->gpd_addr);
}
else{
cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_TQSAR(md_ctrl->txq[i].index), cldma_read32(md_ctrl->cldma_ap_ao_base, CLDMA_AP_TQCPBAK(md_ctrl->txq[i].index)));
cldma_write32(md_ctrl->cldma_ap_ao_base, CLDMA_AP_TQSABAK(md_ctrl->txq[i].index), cldma_read32(md_ctrl->cldma_ap_ao_base, CLDMA_AP_TQCPBAK(md_ctrl->txq[i].index)));
}
}
wmb();
// start all Tx and Rx queues
cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_UL_START_CMD, CLDMA_BM_ALL_QUEUE);
cldma_read32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_UL_START_CMD); // dummy read
md_ctrl->txq_active |= CLDMA_BM_ALL_QUEUE;
//cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_SO_START_CMD, CLDMA_BM_ALL_QUEUE);
//cldma_read32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_SO_START_CMD); // dummy read
//md_ctrl->rxq_active |= CLDMA_BM_ALL_QUEUE;
// enable L2 DONE and ERROR interrupts
cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_L2TIMCR0, CLDMA_BM_INT_DONE|CLDMA_BM_INT_ERROR);
// enable all L3 interrupts
cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_L3TIMCR0, CLDMA_BM_INT_ALL);
cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_L3TIMCR1, CLDMA_BM_INT_ALL);
cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_L3RIMCR0, CLDMA_BM_INT_ALL);
cldma_write32(md_ctrl->cldma_ap_pdn_base, CLDMA_AP_L3RIMCR1, CLDMA_BM_INT_ALL);
spin_unlock_irqrestore(&md_ctrl->cldma_timeout_lock, flags);
CCCI_INF_MSG(md->index, TAG, "Resume cldma pdn register done\n");
}
}
