void BX_CPU_C::protected_mode_int(Bit8u vector, unsigned soft_int, bx_bool push_error, Bit16u error_code) { bx_descriptor_t gate_descriptor, cs_descriptor; bx_selector_t cs_selector; Bit16u raw_tss_selector; bx_selector_t tss_selector; bx_descriptor_t tss_descriptor; Bit16u gate_dest_selector; Bit32u gate_dest_offset; // interrupt vector must be within IDT table limits, // else #GP(vector*8 + 2 + EXT) if ((vector*8 + 7) > BX_CPU_THIS_PTR idtr.limit) { BX_ERROR(("interrupt(): vector must be within IDT table limits, IDT.limit = 0x%x", BX_CPU_THIS_PTR idtr.limit)); exception(BX_GP_EXCEPTION, vector*8 + 2); } Bit64u desctmp = system_read_qword(BX_CPU_THIS_PTR idtr.base + vector*8); Bit32u dword1 = GET32L(desctmp); Bit32u dword2 = GET32H(desctmp); parse_descriptor(dword1, dword2, &gate_descriptor); if ((gate_descriptor.valid==0) || gate_descriptor.segment) { BX_ERROR(("interrupt(): gate descriptor is not valid sys seg (vector=0x%02x)", vector)); exception(BX_GP_EXCEPTION, vector*8 + 2); } // descriptor AR byte must indicate interrupt gate, trap gate, // or task gate, else #GP(vector*8 + 2 + EXT) switch (gate_descriptor.type) { case BX_TASK_GATE: case BX_286_INTERRUPT_GATE: case BX_286_TRAP_GATE: case BX_386_INTERRUPT_GATE: case BX_386_TRAP_GATE: break; default: BX_ERROR(("interrupt(): gate.type(%u) != {5,6,7,14,15}", (unsigned) gate_descriptor.type)); exception(BX_GP_EXCEPTION, vector*8 + 2); } // if software interrupt, then gate descripor DPL must be >= CPL, // else #GP(vector * 8 + 2 + EXT) if (soft_int && gate_descriptor.dpl < CPL) { BX_ERROR(("interrupt(): soft_int && (gate.dpl < CPL)")); exception(BX_GP_EXCEPTION, vector*8 + 2); } // Gate must be present, else #NP(vector * 8 + 2 + EXT) if (! IS_PRESENT(gate_descriptor)) { BX_ERROR(("interrupt(): gate not present")); exception(BX_NP_EXCEPTION, vector*8 + 2); } switch (gate_descriptor.type) { case BX_TASK_GATE: // examine selector to TSS, given in task gate descriptor raw_tss_selector = gate_descriptor.u.taskgate.tss_selector; parse_selector(raw_tss_selector, &tss_selector); // must specify global in the local/global bit, // else #GP(TSS selector) if (tss_selector.ti) { BX_ERROR(("interrupt(): tss_selector.ti=1 from gate descriptor - #GP(tss_selector)")); exception(BX_GP_EXCEPTION, raw_tss_selector & 0xfffc); } // index must be within GDT limits, else #TS(TSS selector) fetch_raw_descriptor(&tss_selector, &dword1, &dword2, BX_GP_EXCEPTION); parse_descriptor(dword1, dword2, &tss_descriptor); // AR byte must specify available TSS, // else #GP(TSS selector) if (tss_descriptor.valid==0 || tss_descriptor.segment) { BX_ERROR(("interrupt(): TSS selector points to invalid or bad TSS - #GP(tss_selector)")); exception(BX_GP_EXCEPTION, raw_tss_selector & 0xfffc); } if (tss_descriptor.type!=BX_SYS_SEGMENT_AVAIL_286_TSS && tss_descriptor.type!=BX_SYS_SEGMENT_AVAIL_386_TSS) { BX_ERROR(("interrupt(): TSS selector points to bad TSS - #GP(tss_selector)")); exception(BX_GP_EXCEPTION, raw_tss_selector & 0xfffc); } // TSS must be present, else #NP(TSS selector) if (! IS_PRESENT(tss_descriptor)) { BX_ERROR(("interrupt(): TSS descriptor.p == 0")); exception(BX_NP_EXCEPTION, raw_tss_selector & 0xfffc); } // switch tasks with nesting to TSS task_switch(0, &tss_selector, &tss_descriptor, BX_TASK_FROM_INT, dword1, dword2); RSP_SPECULATIVE; // if interrupt was caused by fault with error code // stack limits must allow push of 2 more bytes, else #SS(0) // push error code onto stack if (push_error) { if (tss_descriptor.type >= 9) // TSS386 push_32(error_code); else push_16(error_code); } // instruction pointer must be in CS limit, else #GP(0) if (EIP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled) { BX_ERROR(("interrupt(): EIP > CS.limit")); exception(BX_GP_EXCEPTION, 0); } RSP_COMMIT; return; case BX_286_INTERRUPT_GATE: case BX_286_TRAP_GATE: case BX_386_INTERRUPT_GATE: case BX_386_TRAP_GATE: gate_dest_selector = gate_descriptor.u.gate.dest_selector; gate_dest_offset = gate_descriptor.u.gate.dest_offset; // examine CS selector and descriptor given in gate descriptor // selector must be non-null else #GP(EXT) if ((gate_dest_selector & 0xfffc) == 0) { BX_ERROR(("int_trap_gate(): selector null")); exception(BX_GP_EXCEPTION, 0); } parse_selector(gate_dest_selector, &cs_selector); // selector must be within its descriptor table limits // else #GP(selector+EXT) fetch_raw_descriptor(&cs_selector, &dword1, &dword2, BX_GP_EXCEPTION); parse_descriptor(dword1, dword2, &cs_descriptor); // descriptor AR byte must indicate code seg // and code segment descriptor DPL<=CPL, else #GP(selector+EXT) if (cs_descriptor.valid==0 || cs_descriptor.segment==0 || IS_DATA_SEGMENT(cs_descriptor.type) || cs_descriptor.dpl > CPL) { BX_ERROR(("interrupt(): not accessible or not code segment cs=0x%04x", cs_selector.value)); exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc); } // segment must be present, else #NP(selector + EXT) if (! IS_PRESENT(cs_descriptor)) { BX_ERROR(("interrupt(): segment not present")); exception(BX_NP_EXCEPTION, cs_selector.value & 0xfffc); } // if code segment is non-conforming and DPL < CPL then // INTERRUPT TO INNER PRIVILEGE if(IS_CODE_SEGMENT_NON_CONFORMING(cs_descriptor.type) && cs_descriptor.dpl < CPL) { Bit16u old_SS, old_CS, SS_for_cpl_x; Bit32u ESP_for_cpl_x, old_EIP, old_ESP; bx_descriptor_t ss_descriptor; bx_selector_t ss_selector; int is_v8086_mode = v8086_mode(); BX_DEBUG(("interrupt(): INTERRUPT TO INNER PRIVILEGE")); // check selector and descriptor for new stack in current TSS get_SS_ESP_from_TSS(cs_descriptor.dpl, &SS_for_cpl_x, &ESP_for_cpl_x); if (is_v8086_mode && cs_descriptor.dpl != 0) { // if code segment DPL != 0 then #GP(new code segment selector) BX_ERROR(("interrupt(): code segment DPL(%d) != 0 in v8086 mode", cs_descriptor.dpl)); exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc); } // Selector must be non-null else #TS(EXT) if ((SS_for_cpl_x & 0xfffc) == 0) { BX_ERROR(("interrupt(): SS selector null")); exception(BX_TS_EXCEPTION, 0); /* TS(ext) */ } // selector index must be within its descriptor table limits // else #TS(SS selector + EXT) parse_selector(SS_for_cpl_x, &ss_selector); // fetch 2 dwords of descriptor; call handles out of limits checks fetch_raw_descriptor(&ss_selector, &dword1, &dword2, BX_TS_EXCEPTION); parse_descriptor(dword1, dword2, &ss_descriptor); // selector rpl must = dpl of code segment, // else #TS(SS selector + ext) if (ss_selector.rpl != cs_descriptor.dpl) { BX_ERROR(("interrupt(): SS.rpl != CS.dpl")); exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc); } // stack seg DPL must = DPL of code segment, // else #TS(SS selector + ext) if (ss_descriptor.dpl != cs_descriptor.dpl) { BX_ERROR(("interrupt(): SS.dpl != CS.dpl")); exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc); } // descriptor must indicate writable data segment, // else #TS(SS selector + EXT) if (ss_descriptor.valid==0 || ss_descriptor.segment==0 || IS_CODE_SEGMENT(ss_descriptor.type) || !IS_DATA_SEGMENT_WRITEABLE(ss_descriptor.type)) { BX_ERROR(("interrupt(): SS is not writable data segment")); exception(BX_TS_EXCEPTION, SS_for_cpl_x & 0xfffc); } // seg must be present, else #SS(SS selector + ext) if (! IS_PRESENT(ss_descriptor)) { BX_ERROR(("interrupt(): SS not present")); exception(BX_SS_EXCEPTION, SS_for_cpl_x & 0xfffc); } // IP must be within CS segment boundaries, else #GP(0) if (gate_dest_offset > cs_descriptor.u.segment.limit_scaled) { BX_ERROR(("interrupt(): gate EIP > CS.limit")); exception(BX_GP_EXCEPTION, 0); } old_ESP = ESP; old_SS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value; old_EIP = EIP; old_CS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value; // Prepare new stack segment bx_segment_reg_t new_stack; new_stack.selector = ss_selector; new_stack.cache = ss_descriptor; new_stack.selector.rpl = cs_descriptor.dpl; // add cpl to the selector value new_stack.selector.value = (0xfffc & new_stack.selector.value) | new_stack.selector.rpl; if (ss_descriptor.u.segment.d_b) { Bit32u temp_ESP = ESP_for_cpl_x; if (is_v8086_mode) { if (gate_descriptor.type>=14) { // 386 int/trap gate write_new_stack_dword_32(&new_stack, temp_ESP-4, cs_descriptor.dpl, BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value); write_new_stack_dword_32(&new_stack, temp_ESP-8, cs_descriptor.dpl, BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value); write_new_stack_dword_32(&new_stack, temp_ESP-12, cs_descriptor.dpl, BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value); write_new_stack_dword_32(&new_stack, temp_ESP-16, cs_descriptor.dpl, BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value); temp_ESP -= 16; } else { write_new_stack_word_32(&new_stack, temp_ESP-2, cs_descriptor.dpl, BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value); write_new_stack_word_32(&new_stack, temp_ESP-4, cs_descriptor.dpl, BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value); write_new_stack_word_32(&new_stack, temp_ESP-6, cs_descriptor.dpl, BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value); write_new_stack_word_32(&new_stack, temp_ESP-8, cs_descriptor.dpl, BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value); temp_ESP -= 8; } } if (gate_descriptor.type>=14) { // 386 int/trap gate // push long pointer to old stack onto new stack write_new_stack_dword_32(&new_stack, temp_ESP-4, cs_descriptor.dpl, old_SS); write_new_stack_dword_32(&new_stack, temp_ESP-8, cs_descriptor.dpl, old_ESP); write_new_stack_dword_32(&new_stack, temp_ESP-12, cs_descriptor.dpl, read_eflags()); write_new_stack_dword_32(&new_stack, temp_ESP-16, cs_descriptor.dpl, old_CS); write_new_stack_dword_32(&new_stack, temp_ESP-20, cs_descriptor.dpl, old_EIP); temp_ESP -= 20; if (push_error) { temp_ESP -= 4; write_new_stack_dword_32(&new_stack, temp_ESP, cs_descriptor.dpl, error_code); } } else { // 286 int/trap gate // push long pointer to old stack onto new stack write_new_stack_word_32(&new_stack, temp_ESP-2, cs_descriptor.dpl, old_SS); write_new_stack_word_32(&new_stack, temp_ESP-4, cs_descriptor.dpl, (Bit16u) old_ESP); write_new_stack_word_32(&new_stack, temp_ESP-6, cs_descriptor.dpl, (Bit16u) read_eflags()); write_new_stack_word_32(&new_stack, temp_ESP-8, cs_descriptor.dpl, old_CS); write_new_stack_word_32(&new_stack, temp_ESP-10, cs_descriptor.dpl, (Bit16u) old_EIP); temp_ESP -= 10; if (push_error) { temp_ESP -= 2; write_new_stack_word_32(&new_stack, temp_ESP, cs_descriptor.dpl, error_code); } } ESP = temp_ESP; } else { Bit16u temp_SP = (Bit16u) ESP_for_cpl_x; if (is_v8086_mode) { if (gate_descriptor.type>=14) { // 386 int/trap gate write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-4), cs_descriptor.dpl, BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value); write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-8), cs_descriptor.dpl, BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value); write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-12), cs_descriptor.dpl, BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value); write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-16), cs_descriptor.dpl, BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value); temp_SP -= 16; } else { write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-2), cs_descriptor.dpl, BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value); write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-4), cs_descriptor.dpl, BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value); write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-6), cs_descriptor.dpl, BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value); write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-8), cs_descriptor.dpl, BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value); temp_SP -= 8; } } if (gate_descriptor.type>=14) { // 386 int/trap gate // push long pointer to old stack onto new stack write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-4), cs_descriptor.dpl, old_SS); write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-8), cs_descriptor.dpl, old_ESP); write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-12), cs_descriptor.dpl, read_eflags()); write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-16), cs_descriptor.dpl, old_CS); write_new_stack_dword_32(&new_stack, (Bit16u)(temp_SP-20), cs_descriptor.dpl, old_EIP); temp_SP -= 20; if (push_error) { temp_SP -= 4; write_new_stack_dword_32(&new_stack, temp_SP, cs_descriptor.dpl, error_code); } } else { // 286 int/trap gate // push long pointer to old stack onto new stack write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-2), cs_descriptor.dpl, old_SS); write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-4), cs_descriptor.dpl, (Bit16u) old_ESP); write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-6), cs_descriptor.dpl, (Bit16u) read_eflags()); write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-8), cs_descriptor.dpl, old_CS); write_new_stack_word_32(&new_stack, (Bit16u)(temp_SP-10), cs_descriptor.dpl, (Bit16u) old_EIP); temp_SP -= 10; if (push_error) { temp_SP -= 2; write_new_stack_word_32(&new_stack, temp_SP, cs_descriptor.dpl, error_code); } } SP = temp_SP; } // load new CS:eIP values from gate // set CPL to new code segment DPL // set RPL of CS to CPL load_cs(&cs_selector, &cs_descriptor, cs_descriptor.dpl); // load new SS:eSP values from TSS load_ss(&ss_selector, &ss_descriptor, cs_descriptor.dpl); if (is_v8086_mode) { BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.valid = 0; BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].selector.value = 0; BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.valid = 0; BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].selector.value = 0; BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.valid = 0; BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].selector.value = 0; BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.valid = 0; BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].selector.value = 0; } } else { BX_DEBUG(("interrupt(): INTERRUPT TO SAME PRIVILEGE")); if (v8086_mode() && (IS_CODE_SEGMENT_CONFORMING(cs_descriptor.type) || cs_descriptor.dpl != 0)) { // if code segment DPL != 0 then #GP(new code segment selector) BX_ERROR(("interrupt(): code segment conforming or DPL(%d) != 0 in v8086 mode", cs_descriptor.dpl)); exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc); } // EIP must be in CS limit else #GP(0) if (gate_dest_offset > cs_descriptor.u.segment.limit_scaled) { BX_ERROR(("interrupt(): IP > CS descriptor limit")); exception(BX_GP_EXCEPTION, 0); } // push flags onto stack // push current CS selector onto stack // push return offset onto stack if (gate_descriptor.type >= 14) { // 386 gate push_32(read_eflags()); push_32(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value); push_32(EIP); if (push_error) push_32(error_code); } else { // 286 gate push_16((Bit16u) read_eflags()); push_16(BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value); push_16(IP); if (push_error) push_16(error_code); } // load CS:IP from gate // load CS descriptor // set the RPL field of CS to CPL load_cs(&cs_selector, &cs_descriptor, CPL); } EIP = gate_dest_offset; // if interrupt gate then set IF to 0 if (!(gate_descriptor.type & 1)) // even is int-gate BX_CPU_THIS_PTR clear_IF(); BX_CPU_THIS_PTR clear_TF(); BX_CPU_THIS_PTR clear_NT(); BX_CPU_THIS_PTR clear_VM(); BX_CPU_THIS_PTR clear_RF(); return; default: BX_PANIC(("bad descriptor type in interrupt()!")); break; } }
void BX_CPU_C::long_mode_int(Bit8u vector, bx_bool is_INT, bx_bool is_error_code, Bit16u error_code) { // long mode interrupt Bit64u tmp1, tmp2; bx_descriptor_t gate_descriptor, cs_descriptor; bx_selector_t cs_selector; // interrupt vector must be within IDT table limits, // else #GP(vector number*16 + 2 + EXT) if ((vector*16 + 15) > BX_CPU_THIS_PTR idtr.limit) { BX_ERROR(("interrupt(long mode): vector must be within IDT table limits, IDT.limit = 0x%x", BX_CPU_THIS_PTR idtr.limit)); exception(BX_GP_EXCEPTION, vector*16 + 2, 0); } access_read_linear(BX_CPU_THIS_PTR idtr.base + vector*16, 8, 0, BX_READ, &tmp1); access_read_linear(BX_CPU_THIS_PTR idtr.base + vector*16 + 8, 8, 0, BX_READ, &tmp2); if (tmp2 & BX_CONST64(0x00001F0000000000)) { BX_ERROR(("interrupt(long mode): IDT entry extended attributes DWORD4 TYPE != 0")); exception(BX_GP_EXCEPTION, vector*16 + 2, 0); } Bit32u dword1 = GET32L(tmp1); Bit32u dword2 = GET32H(tmp1); Bit32u dword3 = GET32L(tmp2); parse_descriptor(dword1, dword2, &gate_descriptor); if ((gate_descriptor.valid==0) || gate_descriptor.segment) { BX_ERROR(("interrupt(long mode): gate descriptor is not valid sys seg")); exception(BX_GP_EXCEPTION, vector*16 + 2, 0); } // descriptor AR byte must indicate interrupt gate, trap gate, // or task gate, else #GP(vector*16 + 2 + EXT) if (gate_descriptor.type != BX_386_INTERRUPT_GATE && gate_descriptor.type != BX_386_TRAP_GATE) { BX_ERROR(("interrupt(long mode): unsupported gate type %u", (unsigned) gate_descriptor.type)); exception(BX_GP_EXCEPTION, vector*16 + 2, 0); } // if software interrupt, then gate descripor DPL must be >= CPL, // else #GP(vector * 16 + 2 + EXT) if (is_INT && (gate_descriptor.dpl < CPL)) { BX_ERROR(("interrupt(long mode): is_INT && (dpl < CPL)")); exception(BX_GP_EXCEPTION, vector*16 + 2, 0); } // Gate must be present, else #NP(vector * 16 + 2 + EXT) if (! IS_PRESENT(gate_descriptor)) { BX_ERROR(("interrupt(long mode): p == 0")); exception(BX_NP_EXCEPTION, vector*16 + 2, 0); } Bit16u gate_dest_selector = gate_descriptor.u.gate.dest_selector; Bit64u gate_dest_offset = ((Bit64u)dword3 << 32) | gate_descriptor.u.gate.dest_offset; unsigned ist = gate_descriptor.u.gate.param_count & 0x7; // examine CS selector and descriptor given in gate descriptor // selector must be non-null else #GP(EXT) if ((gate_dest_selector & 0xfffc) == 0) { BX_ERROR(("int_trap_gate(long mode): selector null")); exception(BX_GP_EXCEPTION, 0, 0); } parse_selector(gate_dest_selector, &cs_selector); // selector must be within its descriptor table limits // else #GP(selector+EXT) fetch_raw_descriptor(&cs_selector, &dword1, &dword2, BX_GP_EXCEPTION); parse_descriptor(dword1, dword2, &cs_descriptor); // descriptor AR byte must indicate code seg // and code segment descriptor DPL<=CPL, else #GP(selector+EXT) if (cs_descriptor.valid==0 || cs_descriptor.segment==0 || IS_DATA_SEGMENT(cs_descriptor.type) || cs_descriptor.dpl>CPL) { BX_ERROR(("interrupt(long mode): not accessable or not code segment")); exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc, 0); } // check that it's a 64 bit segment if (! IS_LONG64_SEGMENT(cs_descriptor) || cs_descriptor.u.segment.d_b) { BX_ERROR(("interrupt(long mode): must be 64 bit segment")); exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc, 0); } // segment must be present, else #NP(selector + EXT) if (! IS_PRESENT(cs_descriptor)) { BX_ERROR(("interrupt(long mode): segment not present")); exception(BX_NP_EXCEPTION, cs_selector.value & 0xfffc, 0); } // if code segment is non-conforming and DPL < CPL then // INTERRUPT TO INNER PRIVILEGE: if (IS_CODE_SEGMENT_NON_CONFORMING(cs_descriptor.type) && cs_descriptor.dpl<CPL) { Bit64u RSP_for_cpl_x; BX_DEBUG(("interrupt(long mode): INTERRUPT TO INNER PRIVILEGE")); // check selector and descriptor for new stack in current TSS if (ist != 0) { BX_DEBUG(("interrupt(long mode): trap to IST, vector = %d", ist)); get_RSP_from_TSS(ist+3, &RSP_for_cpl_x); } else { get_RSP_from_TSS(cs_descriptor.dpl, &RSP_for_cpl_x); } RSP_for_cpl_x &= BX_CONST64(0xfffffffffffffff0); Bit64u old_CS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value; Bit64u old_RIP = RIP; Bit64u old_SS = BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value; Bit64u old_RSP = RSP; if (! IsCanonical(RSP_for_cpl_x)) { // #SS(selector) when changing priviledge level BX_ERROR(("interrupt(long mode): canonical address failure %08x%08x", GET32H(RSP_for_cpl_x), GET32L(RSP_for_cpl_x))); exception(BX_SS_EXCEPTION, old_SS & 0xfffc, 0); } // push old stack long pointer onto new stack write_new_stack_qword_64(RSP_for_cpl_x - 8, cs_descriptor.dpl, old_SS); write_new_stack_qword_64(RSP_for_cpl_x - 16, cs_descriptor.dpl, old_RSP); write_new_stack_qword_64(RSP_for_cpl_x - 24, cs_descriptor.dpl, read_eflags()); // push long pointer to return address onto new stack write_new_stack_qword_64(RSP_for_cpl_x - 32, cs_descriptor.dpl, old_CS); write_new_stack_qword_64(RSP_for_cpl_x - 40, cs_descriptor.dpl, old_RIP); RSP_for_cpl_x -= 40; if (is_error_code) { RSP_for_cpl_x -= 8; write_new_stack_qword_64(RSP_for_cpl_x, cs_descriptor.dpl, error_code); } bx_selector_t ss_selector; bx_descriptor_t ss_descriptor; // set up a null descriptor parse_selector(0, &ss_selector); parse_descriptor(0, 0, &ss_descriptor); // load CS:RIP (guaranteed to be in 64 bit mode) branch_far64(&cs_selector, &cs_descriptor, gate_dest_offset, cs_descriptor.dpl); // set up null SS descriptor load_ss(&ss_selector, &ss_descriptor, cs_descriptor.dpl); RSP = RSP_for_cpl_x; // if INTERRUPT GATE set IF to 0 if (!(gate_descriptor.type & 1)) // even is int-gate BX_CPU_THIS_PTR clear_IF(); BX_CPU_THIS_PTR clear_TF(); BX_CPU_THIS_PTR clear_VM(); BX_CPU_THIS_PTR clear_RF(); BX_CPU_THIS_PTR clear_NT(); return; } // if code segment is conforming OR code segment DPL = CPL then // INTERRUPT TO SAME PRIVILEGE LEVEL: if (IS_CODE_SEGMENT_CONFORMING(cs_descriptor.type) || cs_descriptor.dpl==CPL) { BX_DEBUG(("interrupt(long mode): INTERRUPT TO SAME PRIVILEGE")); Bit64u old_RSP = RSP; // check selector and descriptor for new stack in current TSS if (ist > 0) { BX_DEBUG(("interrupt(long mode): trap to IST, vector = %d", ist)); get_RSP_from_TSS(ist+3, &RSP); } // align stack RSP &= BX_CONST64(0xfffffffffffffff0); // push flags onto stack // push current CS selector onto stack // push return offset onto stack write_new_stack_qword_64(RSP - 8, cs_descriptor.dpl, BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].selector.value); write_new_stack_qword_64(RSP - 16, cs_descriptor.dpl, old_RSP); write_new_stack_qword_64(RSP - 24, cs_descriptor.dpl, read_eflags()); write_new_stack_qword_64(RSP - 32, cs_descriptor.dpl, BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value); write_new_stack_qword_64(RSP - 40, cs_descriptor.dpl, RIP); RSP -= 40; if (is_error_code) { RSP -= 8; write_new_stack_qword_64(RSP, cs_descriptor.dpl, error_code); } // set the RPL field of CS to CPL branch_far64(&cs_selector, &cs_descriptor, gate_dest_offset, CPL); // if interrupt gate then set IF to 0 if (!(gate_descriptor.type & 1)) // even is int-gate BX_CPU_THIS_PTR clear_IF(); BX_CPU_THIS_PTR clear_TF(); BX_CPU_THIS_PTR clear_VM(); BX_CPU_THIS_PTR clear_RF(); BX_CPU_THIS_PTR clear_NT(); return; } // else #GP(CS selector + ext) BX_ERROR(("interrupt(long mode): bad descriptor type=%u, descriptor.dpl=%u, CPL=%u", (unsigned) cs_descriptor.type, (unsigned) cs_descriptor.dpl, (unsigned) CPL)); BX_ERROR(("cs.segment = %u", (unsigned) cs_descriptor.segment)); exception(BX_GP_EXCEPTION, cs_selector.value & 0xfffc, 0); }