static char do_patern_led(struct args_t *args) {
if(args) {
/*
* Patern 0 -> clear
* Patern 1 -> unie
* Patern 2 -> defilement
* Patern 3 -> empiler
* Patern 4 -> aller_retour
* Couleur 0 -> Clear
* Couleur 1 -> Bleu
* Couleur 2 -> Rouge
* Couleur 3 -> Vert
*/
INIT_WAIT;
SPI_INIT;
//On clear les LED
clear_led();
uint16_t coul = get_coul((int) args->couleur1);
uint16_t coul2 = get_coul((int) args->couleur2);
int patern = (int) args->patern;
int tour = (int) args->tour;
switch(patern){
case 0 :
clear_led();
break;
case 1 :
unie(coul);
break;
case 2 :
defilement_led(coul);
//On clear les LED
clear_led();
break;
case 3 :
empiler(coul, coul2, tour);
//On clear les LED
clear_led();
break;
case 4 :
allerRetour(coul, coul2, tour);
break;
//On clear les LED
clear_led();
default :
break;
}
}
return 0;
}
static void
quicc_eth_TxEvent(struct eth_drv_sc *sc, int stat)
{
struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private;
volatile struct cp_bufdesc *txbd;
int txindex;
bool restart = false;
txbd = qi->tnext;
while ((txbd->ctrl & (QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int)) == QUICC_BD_CTL_Int) {
txindex = ((unsigned long)txbd - (unsigned long)qi->tbase) / sizeof(*txbd);
qi->tx_complete++;
(sc->funs->eth_drv->tx_done)(sc, qi->txkey[txindex], 0);
txbd->ctrl &= ~QUICC_BD_CTL_Int; // Reset int pending bit
if (txbd->ctrl & QUICC_BD_TX_LC )
qi->tx_late_collisions++, restart = true;
if (txbd->ctrl & QUICC_BD_TX_RL )
qi->tx_retransmit_error++, restart = true;
if (txbd->ctrl & QUICC_BD_TX_UN )
qi->tx_underrun++, restart = true;
if (txbd->ctrl & QUICC_BD_TX_CSL )
qi->tx_carrier_loss++;
if (txbd->ctrl & QUICC_BD_TX_HB )
qi->tx_heartbeat_loss++;
if (txbd->ctrl & QUICC_BD_TX_DEF )
qi->tx_deferred++;
if( (txbd->ctrl & QUICC_BD_TX_ERRORS) == 0 )
qi->tx_good++;
if (txbd->ctrl & QUICC_BD_CTL_Wrap) {
txbd->ctrl = QUICC_BD_CTL_Wrap;
txbd = qi->tbase;
} else {
txbd->ctrl = 0;
txbd++;
}
qi->txactive--;
}
if (qi->txactive == 0) {
clear_led(LED_TxACTIVE);
}
// Remember where we left off
qi->tnext = (struct cp_bufdesc *)txbd;
if (restart)
{
quicc_eth_command(sc,QUICC_CPM_CR_RESTART_TX);
qi->tx_restart++;
}
}
void my_exit ()
{
if (opt_b && ! opt_q)
printf("Bye-Bye !\n");
if (myDisplay) {
#if (! REMOVE_X_CODE)
clear_led(NUMLOCKLED);
clear_led(SCROLLLOCKLED);
XCloseDisplay(myDisplay); /* X */
#endif
}
detach_vt_leds(FALSE); /* re-attach */
if (keyboardDevice) /* EUID root - CONSOLE */
close(keyboardDevice);
if(getpid() == get_old_pid()) {
unlink(pidFileName);
unlink(rootPidFileName);
}
}
void mike::close() noexcept
{
if(is_open())
{
// don't throw, when closing
try { clear_led(); } catch(...) { /* do nothing */ }
::close(fd);
fd = invalid;
}
}
void led_flash_task(void *pvParameters)
{
uint8_t led = *(uint8_t*)pvParameters;
clear_led(led);
for (;;)
{
usleep(1000000);
toggle_led(led);
usleep(60000);
toggle_led(led);
}
}
int main(void)
{
int i;
if(sdcard_mount(&sddisk, 0) == FR_OK)
{
// open a new file for writing
if(f_open(&appdata.file, TEST_FILENAME, FA_WRITE|FA_OPEN_ALWAYS) == FR_OK)
{
// flash twice
appdata.flash = 2;
// write a number to the file (no newline needed in this case)
f_puts((const TCHAR *)TEST_FLASHES, &appdata.file);
f_close(&appdata.file);
}
// open the new file for reading
if(f_open(&appdata.file, TEST_FILENAME, FA_READ) == FR_OK)
{
// flash three times
appdata.flash = 3;
if(f_gets((TCHAR *)appdata.buffer, sizeof(appdata.buffer)-1, &appdata.file))
{
// flash the number of times set in the file
// decode the number in the file
appdata.flash = atoi(appdata.buffer);
}
f_close(&appdata.file);
}
}
while(1)
{
for(i = 0; i < appdata.flash; i++)
{
set_led(LED1);
usleep(100000);
clear_led(LED1);
usleep(200000);
}
sleep(1);
}
return 0;
}
//
// This function is called as a result of the "eth_drv_recv()" call above.
// It's job is to actually fetch data for a packet from the hardware once
// memory buffers have been allocated for the packet. Note that the buffers
// may come in pieces, using a scatter-gather list. This allows for more
// efficient processing in the upper layers of the stack.
//
static void
fec_eth_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len)
{
struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
unsigned char *bp;
int i, cache_state;
bp = (unsigned char *)qi->rxbd->buffer;
// Note: the MPC860 does not seem to snoop/invalidate the data cache properly!
HAL_DCACHE_IS_ENABLED(cache_state);
if (cache_state) {
HAL_DCACHE_INVALIDATE(qi->rxbd->buffer, qi->rxbd->length); // Make sure no stale data
}
for (i = 0; i < sg_len; i++) {
if (sg_list[i].buf != 0) {
memcpy((void *)sg_list[i].buf, bp, sg_list[i].len);
bp += sg_list[i].len;
}
}
qi->rxbd->ctrl |= FEC_BD_Rx_Empty;
clear_led(LED_RxACTIVE);
}
static void
fec_eth_TxEvent(struct eth_drv_sc *sc)
{
struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
volatile struct fec_bd *txbd;
int key, txindex, cache_state;
HAL_DCACHE_IS_ENABLED(cache_state);
#ifndef FEC_USE_EPPC_BD
if (cache_state) {
HAL_DCACHE_FLUSH(fec_eth_txring, sizeof(fec_eth_txring)); // Make sure no stale data
}
#endif
txbd = qi->tnext;
// Note: TC field is used to indicate the buffer has/had data in it
while ((txbd->ctrl & (FEC_BD_Tx_Ready|FEC_BD_Tx_TC)) == FEC_BD_Tx_TC) {
txindex = ((unsigned long)txbd - (unsigned long)qi->tbase) / sizeof(*txbd);
if ((key = qi->txkey[txindex]) != 0) {
qi->txkey[txindex] = 0;
(sc->funs->eth_drv->tx_done)(sc, key, 0);
}
if (--qi->txactive == 0) {
clear_led(LED_TxACTIVE);
}
txbd->ctrl &= ~FEC_BD_Tx_TC;
if (txbd->ctrl & FEC_BD_Tx_Wrap) {
txbd = qi->tbase;
} else {
txbd++;
}
}
// Remember where we left off
qi->tnext = (struct fec_bd *)txbd;
#ifndef FEC_USE_EPPC_BD
if (cache_state) {
HAL_DCACHE_FLUSH(fec_eth_txring, sizeof(fec_eth_txring)); // Make sure no stale data
}
#endif
}
/*----------------------------------------------------------------------------*/
void disp_port(u8 menu)
{
if (menu < 0x80) //显示场景切换，整个显示均会更新
{
clear_led();
cur_menu = menu;
main_menu_conter = 0;
if (menu != MENU_INPUT_NUMBER)
input_number = 0;
switch (menu)
{
case MENU_NULL:
break;
case MENU_PAUSE:
disp_music_pause();
break;
case MENU_STOP:
disp_music_stop();
break;
case MENU_SCAN_DISK:
disp_scan_disk();
break;
case MENU_MAIN_VOL:
disp_main_vol(sys_main_vol);
break;
case MENU_FILENUM:
play_time_filenum_slider=0;
disp_input_number(filenum_phy_logic(fs_msg.fileNumber));
break;
case MENU_MUSIC_MAIN:
disp_music_main();
break;
case MENU_INPUT_NUMBER:
disp_input_number(input_number);
break;
case MENU_FM_MAIN:
#if FM_MODULE
disp_fm_main();
#endif
break;
case MENU_FM_CHANNEL:
#if FM_MODULE
disp_fm_channel();
#endif
break;
case MENU_POWER_UP:
disp_power_on();
break;
case MENU_FM_DISP_FRE:
#if FM_MODULE
disp_fm_freq();
#endif
break;
case MENU_FM_FIND_STATION:
#if FM_MODULE
disp_fm_find_station();
#endif
break;
case MENU_AUX:
disp_aux();
break;
case MENU_REC_ERR:
disp_rec_err();
break;
case MENU_REC_MAIN:
disp_music_main();
break;
case MENU_SET_EQ:
disp_eq();
break;
case MENU_SET_PLAY_MODE:
disp_play_mode();
break;
case DISP_PWR_TIMER:
disp_sleep_timer();
break;
case MENU_RECWORKING:
disp_rec_working();
break;
case MENU_REC:
disp_rec();
break;
case MENU_REC_PAUSE:
disp_rec_pause();
break;
case MENU_REC_DEL:
disp_del();
break;
#if ECHO_ENABLE
case MENU_REV_DEEP:
disp_rev_deep();
break;
case MENU_REV_STRONG:
disp_rev_strong();
break;
#endif
#if USB_DEVICE_ENABLE
case MENU_USBDEV_MAIN:
disp_usb_device();
break;
#endif
#if RTC_ENABLE
case MENU_RTC:
disp_curr_time();
break;
case MENU_ALM_SET:
disp_alarm();
break;
case MENU_ALM_UP:
disp_alarm_up();
break;
case MENU_RTC_PWD:
disp_power_off();
break;
#if USB_DEVICE_ENABLE
case MENU_ALM_REQUEST:
disp_alm_request();
break;
#endif
#endif
}
}
else //局部显示替换和更新
{
switch (menu)
{
case MENU_HALF_SEC_REFRESH:
disp_main_menu_refresh();
break;
case MENU_POWER_DOWN:
disp_nothing();
break;
}
}
if(alm_on_flag){
led_flash_icon(LED0_ALARM);
}
if(alarm.sw){
led_disp_icon(LED0_ALARM);
}
}
/*----------------------------------------------------------------------------*/
void disp_nothing(void)
{
clear_led();
}
jam_info process_signal(win_peak peak, float sample_rate, time_info *time)
{
jam_info rv;
float min = INFINITY;
float max = -INFINITY;
float max_freq = -INFINITY;
float freq;
int i, max_i;
rv.valid = 0;
++time->time;
/* Skip if not time->triggered and peak is below threshold */
if (!time->trigger && peak.value <= THRESHOLD)
{
return rv;
}
time->trigger = 1;
if (time->index == 0)
{
time->freq_vs_time = prot_mem_malloc(sizeof(cplx) * BUFFER_LEN);
clear_led(0);
}
if (peak.valid)
time->freq_vs_time[time->index] = peak.freq + 0 * I;
else
time->freq_vs_time[time->index] = time->freq_vs_time[time->index - 1];
++(time->index);
if (time->index == BUFFER_LEN)
{
for (i = 0; i < BUFFER_LEN; ++i)
{
freq = creal(time->freq_vs_time[i]);
min = fmin(min, freq);
max = fmax(max, freq);
}
fft(time->freq_vs_time, BUFFER_LEN);
time->freq_vs_time[BUFFER_LEN/2] = 0; /* Delete the DC value of the result */
for (i = 0; i < BUFFER_LEN; i++){
freq = cabs(time->freq_vs_time[i]);
if (freq > max_freq){
max_freq = freq;
max_i = i;
}
}
rv.bandwidth = max - min;
rv.chirprate = (sample_rate / WIN_SIZE) * (2.0 * max_i - (BUFFER_LEN / 2.0) / (2.0 * BUFFER_LEN));
rv.time = time->time / (sample_rate / 64000);
if (rv.bandwidth != 0.0)
rv.valid = 1;
time->trigger = 0;
time->index = 0;
set_led(0);
prot_mem_free(time->freq_vs_time);
}
return rv;
}
/* thread spawned for each connection */
void process_echo_request(void *p)
{
int sd = (int)p;
int n, i, nsamples;
float sample_rate, center_freq;
win_peak peak;
jam_info info;
time_info time;
cplx *buf = prot_mem_malloc(sizeof(cplx) * WIN_SIZE);
float *bhwin = prot_mem_malloc(sizeof(float) * WIN_SIZE);
unsigned int run_time;
blackman_harris(bhwin, WIN_SIZE);
union Fpass{
unsigned int i[UNION_SIZE];
float fl[UNION_SIZE];
char ch[RECV_BUF_SIZE];
} fpass;
time.trigger = 0;
time.time = 0;
time.index = 0;
time.freq_vs_time = NULL;
run_time = 0;
while (1) {
/* read a max of RECV_BUF_SIZE bytes from socket */
if ((n = read(sd, fpass.ch, RECV_BUF_SIZE)) < 0) {
xil_printf("%s: error reading from socket %d, closing socket\r\n", __FUNCTION__, sd);
#ifndef OS_IS_FREERTOS
close(sd);
return;
#else
break;
#endif
}
/* break if the recved message = "quit" */
if (!strncmp(fpass.ch, "quit", 4))
break;
/* break if client closed connection */
if (n <= 0)
break;
++run_time;
/* Rearrange from network order */
for (i = 0; i < UNION_SIZE; ++i)
{
fpass.i[i] = ntohl(fpass.i[i]);
}
/* Get info from header */
nsamples = fpass.i[0];
sample_rate = fpass.fl[1];
center_freq = fpass.fl[2];
if (nsamples != 64)
continue;
/* Limit nsamples to window size */
if (nsamples > WIN_SIZE)
nsamples = WIN_SIZE;
uninter(&fpass.fl[3], buf, nsamples);
for (i = 0; i < WIN_SIZE; ++i)
{
buf[i] *= bhwin[i];
}
/* fft and get peak */
fft(buf, nsamples);
peak = get_peak(buf, nsamples, sample_rate, center_freq);
info = process_signal(peak, sample_rate, &time);
if (info.valid)
{
printf("Time: %.2f Bandwidth: %.2f, Chirp Rate: %.2f\r\n", run_time / (sample_rate / 64000), info.bandwidth, info.chirprate);
info.valid = 0;
}
/* handle request */
/*if ((nwrote = write(sd, fpass.ch, n)) < 0) {
xil_printf("%s: ERROR responding to client echo request. received = %d, written = %d\r\n",
__FUNCTION__, n, nwrote);
xil_printf("Closing socket %d\r\n", sd);
#ifndef OS_IS_FREERTOS
close(sd);
return;
#else
break;
#endif
}
*/
}
/* close connection */
clear_led(7);
prot_mem_free(bhwin);
prot_mem_free(buf);
close(sd);
#ifdef OS_IS_FREERTOS
vTaskDelete(NULL);
#endif
}
//
// This function is called when a packet has been received. It's job is
// to prepare to unload the packet from the hardware. Once the length of
// the packet is known, the upper layer of the driver can be told. When
// the upper layer is ready to unload the packet, the internal function
// 'quicc_eth_recv' will be called to actually fetch it from the hardware.
//
static void
quicc_eth_RxEvent(struct eth_drv_sc *sc)
{
struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private;
volatile struct cp_bufdesc *rxbd;
rxbd = qi->rnext;
while ((rxbd->ctrl & (QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int)) == QUICC_BD_CTL_Int) {
qi->rx_count++;
if( rxbd->ctrl & QUICC_BD_RX_MISS )
{
qi->rx_miss++;
}
if( rxbd->ctrl & QUICC_BD_RX_LG )
{
qi->rx_long_frames++;
}
if( rxbd->ctrl & QUICC_BD_RX_NO )
{
qi->rx_align_errors++;
}
if( rxbd->ctrl & QUICC_BD_RX_SH )
{
qi->rx_short_frames++;
}
if( rxbd->ctrl & QUICC_BD_RX_CR )
{
qi->rx_crc_errors++;
}
if( rxbd->ctrl & QUICC_BD_RX_OV )
{
qi->rx_overrun_errors++;
}
if( rxbd->ctrl & QUICC_BD_RX_CL )
{
qi->rx_collisions++;
}
if( (rxbd->ctrl & QUICC_BD_RX_ERRORS) == 0 )
{
qi->rx_good++;
// OK frame - Prepare for callback
qi->rxbd = rxbd; // Save for callback
set_led(LED_RxACTIVE);
(sc->funs->eth_drv->recv)(sc, rxbd->length);
clear_led(LED_RxACTIVE);
}
// Clear flags and wrap if needed else step up BD pointer
if (rxbd->ctrl & QUICC_BD_CTL_Wrap)
{
rxbd->ctrl = QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int | QUICC_BD_CTL_Wrap;
rxbd = qi->rbase;
}
else
{
rxbd->ctrl = QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int;
rxbd++;
}
}
// Remember where we left off
qi->rnext = (struct cp_bufdesc *)rxbd;
}
//
// Initialize the interface - performed at system startup
// This function must set up the interface, including arranging to
// handle interrupts, etc, so that it may be "started" cheaply later.
//
static bool
quicc_eth_init(struct cyg_netdevtab_entry *tab)
{
struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance;
struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private;
volatile EPPC *eppc = (volatile EPPC *)eppc_base();
struct cp_bufdesc *rxbd, *txbd;
unsigned char *RxBUF, *TxBUF, *ep, *ap;
volatile struct ethernet_pram *enet_pram;
volatile struct scc_regs *scc;
int TxBD, RxBD;
int cache_state;
int i;
bool esa_ok = false;
#ifdef QUICC_ETH_FETCH_ESA
QUICC_ETH_FETCH_ESA(esa_ok);
#endif
if (!esa_ok) {
#if defined(CYGPKG_REDBOOT) && \
defined(CYGSEM_REDBOOT_FLASH_CONFIG)
esa_ok = flash_get_config("quicc_esa", enaddr, CONFIG_ESA);
#else
esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
"quicc_esa", enaddr, CONFIG_ESA);
#endif
if (!esa_ok) {
// Can't figure out ESA
diag_printf("QUICC_ETH - Warning! ESA unknown\n");
memcpy(&enaddr, &_default_enaddr, sizeof(enaddr));
}
}
// Ensure consistent state between cache and what the QUICC sees
HAL_DCACHE_IS_ENABLED(cache_state);
HAL_DCACHE_SYNC();
HAL_DCACHE_DISABLE();
#ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
// Set up to handle interrupts
cyg_drv_interrupt_create(QUICC_ETH_INT,
CYGARC_SIU_PRIORITY_HIGH,
(cyg_addrword_t)sc, // Data item passed to interrupt handler
(cyg_ISR_t *)quicc_eth_isr,
(cyg_DSR_t *)eth_drv_dsr,
&quicc_eth_interrupt_handle,
&quicc_eth_interrupt);
cyg_drv_interrupt_attach(quicc_eth_interrupt_handle);
cyg_drv_interrupt_acknowledge(QUICC_ETH_INT);
cyg_drv_interrupt_unmask(QUICC_ETH_INT);
#endif
qi->pram = enet_pram = &eppc->pram[QUICC_ETH_SCC].enet_scc;
qi->ctl = scc = &eppc->scc_regs[QUICC_ETH_SCC]; // Use SCCx
// Shut down ethernet, in case it is already running
scc->scc_gsmr_l &= ~(QUICC_SCC_GSML_ENR | QUICC_SCC_GSML_ENT);
memset((void *)enet_pram, 0, sizeof(*enet_pram));
TxBD = _mpc8xx_allocBd(CYGNUM_DEVS_ETH_POWERPC_QUICC_TxNUM * sizeof(struct cp_bufdesc));
RxBD = _mpc8xx_allocBd(CYGNUM_DEVS_ETH_POWERPC_QUICC_RxNUM * sizeof(struct cp_bufdesc));
txbd = (struct cp_bufdesc *)((char *)eppc + TxBD);
rxbd = (struct cp_bufdesc *)((char *)eppc + RxBD);
qi->tbase = txbd;
qi->txbd = txbd;
qi->tnext = txbd;
qi->rbase = rxbd;
qi->rxbd = rxbd;
qi->rnext = rxbd;
qi->txactive = 0;
RxBUF = &quicc_eth_rxbufs[0][0];
TxBUF = &quicc_eth_txbufs[0][0];
// setup buffer descriptors
for (i = 0; i < CYGNUM_DEVS_ETH_POWERPC_QUICC_RxNUM; i++) {
rxbd->length = 0;
rxbd->buffer = RxBUF;
rxbd->ctrl = QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int;
RxBUF += CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE;
rxbd++;
}
rxbd--;
rxbd->ctrl |= QUICC_BD_CTL_Wrap; // Last buffer
for (i = 0; i < CYGNUM_DEVS_ETH_POWERPC_QUICC_TxNUM; i++) {
txbd->length = 0;
txbd->buffer = TxBUF;
txbd->ctrl = 0;
TxBUF += CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE;
txbd++;
}
txbd--;
txbd->ctrl |= QUICC_BD_CTL_Wrap; // Last buffer
// Set up parallel ports for connection to ethernet tranceiver
eppc->pio_papar |= (QUICC_ETH_PA_RXD | QUICC_ETH_PA_TXD);
eppc->pio_padir &= ~(QUICC_ETH_PA_RXD | QUICC_ETH_PA_TXD);
eppc->pio_paodr &= ~QUICC_ETH_PA_TXD;
eppc->pio_pcpar &= ~(QUICC_ETH_PC_COLLISION | QUICC_ETH_PC_Rx_ENABLE);
eppc->pio_pcdir &= ~(QUICC_ETH_PC_COLLISION | QUICC_ETH_PC_Rx_ENABLE);
eppc->pio_pcso |= (QUICC_ETH_PC_COLLISION | QUICC_ETH_PC_Rx_ENABLE);
eppc->pio_papar |= (QUICC_ETH_PA_Tx_CLOCK | QUICC_ETH_PA_Rx_CLOCK);
eppc->pio_padir &= ~(QUICC_ETH_PA_Tx_CLOCK | QUICC_ETH_PA_Rx_CLOCK);
// Set up clock routing
eppc->si_sicr &= ~QUICC_ETH_SICR_MASK;
eppc->si_sicr |= QUICC_ETH_SICR_ENET;
eppc->si_sicr &= ~QUICC_ETH_SICR_ENABLE;
// Set up DMA mode
eppc->dma_sdcr = 0x0001;
// Initialize shared PRAM
enet_pram->rbase = RxBD;
enet_pram->tbase = TxBD;
// Set Big Endian mode
enet_pram->rfcr = QUICC_SCC_FCR_BE;
enet_pram->tfcr = QUICC_SCC_FCR_BE;
// Size of receive buffers
enet_pram->mrblr = CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE;
// Initialize CRC calculations
enet_pram->c_pres = 0xFFFFFFFF;
enet_pram->c_mask = 0xDEBB20E3; // Actual CRC formula
enet_pram->crcec = 0;
enet_pram->alec = 0;
enet_pram->disfc = 0;
// Frame padding
enet_pram->pads = 0x8888;
enet_pram->pads = 0x0000;
// Retries
enet_pram->ret_lim = 15;
enet_pram->ret_cnt = 0;
// Frame sizes
enet_pram->mflr = IEEE_8023_MAX_FRAME;
enet_pram->minflr = IEEE_8023_MIN_FRAME;
enet_pram->maxd1 = CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE;
enet_pram->maxd2 = CYGNUM_DEVS_ETH_POWERPC_QUICC_BUFSIZE;
// Group address hash
enet_pram->gaddr1 = 0;
enet_pram->gaddr2 = 0;
enet_pram->gaddr3 = 0;
enet_pram->gaddr4 = 0;
// Device physical address
ep = &enaddr[sizeof(enaddr)];
ap = (unsigned char *)&enet_pram->paddr_h;
for (i = 0; i < sizeof(enaddr); i++) {
*ap++ = *--ep;
}
// Persistence counter
enet_pram->p_per = 0;
// Individual address filter
enet_pram->iaddr1 = 0;
enet_pram->iaddr2 = 0;
enet_pram->iaddr3 = 0;
enet_pram->iaddr4 = 0;
// Temp address
enet_pram->taddr_h = 0;
enet_pram->taddr_m = 0;
enet_pram->taddr_l = 0;
// Initialize the CPM (set up buffer pointers, etc).
eppc->cp_cr = QUICC_CPM_SCCx | QUICC_CPM_CR_INIT_TXRX | QUICC_CPM_CR_BUSY;
while (eppc->cp_cr & QUICC_CPM_CR_BUSY) ;
// Clear any pending interrupt/exceptions
scc->scc_scce = 0xFFFF;
// Enable interrupts
scc->scc_sccm = QUICC_SCCE_INTS | QUICC_SCCE_GRC | QUICC_SCCE_BSY;
// Set up SCCx to run in ethernet mode
scc->scc_gsmr_h = 0;
scc->scc_gsmr_l = QUICC_SCC_GSML_TCI | QUICC_SCC_GSML_TPL_48 |
QUICC_SCC_GSML_TPP_01 | QUICC_SCC_GSML_MODE_ENET;
// Sync delimiters
scc->scc_dsr = 0xD555;
// Protocol specifics (as if GSML wasn't enough)
scc->scc_psmr = QUICC_PMSR_ENET_CRC | QUICC_PMSR_SEARCH_AFTER_22 |
QUICC_PMSR_RCV_SHORT_FRAMES;
#ifdef QUICC_ETH_ENABLE
QUICC_ETH_ENABLE();
#endif
#ifdef QUICC_ETH_RESET_PHY
QUICC_ETH_RESET_PHY();
#endif
// Enable ethernet interface
#ifdef QUICC_ETH_PC_Tx_ENABLE
eppc->pio_pcpar |= QUICC_ETH_PC_Tx_ENABLE;
eppc->pio_pcdir &= ~QUICC_ETH_PC_Tx_ENABLE;
#else
eppc->pip_pbpar |= QUICC_ETH_PB_Tx_ENABLE;
eppc->pip_pbdir |= QUICC_ETH_PB_Tx_ENABLE;
#endif
if (cache_state)
HAL_DCACHE_ENABLE();
// Initialize upper level driver
(sc->funs->eth_drv->init)(sc, (unsigned char *)&enaddr);
// Set LED state
clear_led(LED_TxACTIVE);
clear_led(LED_RxACTIVE);
return true;
}
/*----------------------------------------------------------------------------*/
void Disp_Con(u8 LCDinterf)
{
///*
return_cnt = 0;
curr_menu = LCDinterf;
if (DISP_NULL == LCDinterf)
{
return;
}
clear_led();
switch (LCDinterf)
{
case DISP_NULL:
Disp_Play();
break;
case DISP_DWORD_NUMBER:
Disp_Num();
break;
case DISP_FILENUM:
Disp_Filenum();
break;
case DISP_NOFILE:
Disp_Nofile();
break;
case DISP_NODEVICE:
Disp_Nodevice();
break;
case DISP_PLAY:
Disp_Play();
break;
case DISP_PAUSE:
Disp_Pause();
break;
case DISP_VOL:
Disp_Vol();
break;
case DISP_EQ:
Disp_Eq();
break;
case DISP_POWER_UP:
Disp_Power_up();
break;
case DISP_PLAYMODE:
Diap_Playmode();
break;
case DISP_WAIT:
Disp_Waiting();
break;
case DISP_USBDEV:
Disp_USB_Slave();
break;
case DISP_FREQ:
Disp_Freq();
break;
case DISP_CH_NO:
Disp_CH_NO();
break;
case DISP_SCAN_NO:
Disp_Scan_NO();
break;
case DISP_USBOUT:
disp_devchange(2);
break;
case DISP_SDOUT:
disp_devchange(1);
break;
case DISP_AUX:
Disp_AUX();
break;
case DISP_START:
Disp_Start();
break;
case DISP_PWR_OFF:
Disp_PwrOFF();
break;
#if RTC_ENABLE
case DISP_RTC_POINT:
Disp_RTC_POINT();
Disp_RTC();
break;
#ifdef USE_RTC_YEAR_FUNCTION
case DISP_RTC_DATE:
Disp_RTC_Date();
break;
#endif
case DISP_RTC:
Disp_RTC();
break;
case DISP_RTC_PWD:
break;
case DISP_ALM_UP:
Disp_Alm_Up();
break;
#endif
default:break;
}
}
void do_keyboard_mode(void) {
signed int shift = 0;
uint8_t accent=0, slide=0;
uint8_t i, last_bank;
// turn tempo off!
turn_off_tempo();
clear_bank_leds();
read_switches();
last_bank = bank;
has_bank_knob_changed(); // ignore startup change
while (1) {
read_switches();
if (function_changed) {
midi_notesoff(); // turn all notes off
return;
}
// show the current MIDI address
if (!is_bank_led_set(midi_out_addr)) {
clear_bank_leds();
set_bank_led(midi_out_addr);
}
if (has_bank_knob_changed()) {
// bank knob was changed, which means they want a different
// midi addr... OK then!
midi_out_addr = bank;
// set the new midi address (burn to EEPROM)
internal_eeprom_write8(MIDIOUT_ADDR_EEADDR, midi_out_addr);
last_bank = bank;
}
// show the octave
display_octave_shift(shift);
for (i=0; i<13; i++) {
// check if any notes were just pressed
if (just_pressed(notekey_tab[i])) {
note_on((C2+i) + shift*OCTAVE, slide, accent);
midi_send_note_on( ((C2+i) + shift*OCTAVE) | (accent << 6));
slide = TRUE;
// turn on that LED
set_notekey_led(i);
}
// check if any notes were released
if (just_released(notekey_tab[i])) {
midi_send_note_off( ((C2+i) + shift*OCTAVE) | (accent << 6));
// turn off that LED
clear_notekey_led(i);
}
}
if (just_pressed(KEY_UP)) {
if (shift < 2)
shift++;
} else if (just_pressed(KEY_DOWN)) {
if (shift > -1)
shift--;
}
// check if they turned accent on
if (just_pressed(KEY_ACCENT)) {
accent = !accent;
if (accent)
set_led(LED_ACCENT);
else
clear_led(LED_ACCENT);
}
// if no keys are held down and there was a note just playing
// turn off the note.
if ((NOTE_PIN & 0x3F) && no_keys_pressed()) {
note_off(0);
slide = FALSE;
clear_notekey_leds();
}
}
}
//
// [re]Initialize the ethernet controller
// Done separately since shutting down the device requires a
// full reconfiguration when re-enabling.
// when
static bool
fec_eth_reset(struct eth_drv_sc *sc, unsigned char *enaddr, int flags)
{
struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
volatile EPPC *eppc = (volatile EPPC *)eppc_base();
volatile struct fec *fec = (volatile struct fec *)((unsigned char *)eppc + FEC_OFFSET);
volatile struct fec_bd *rxbd, *txbd;
unsigned char *RxBUF, *TxBUF;
int cache_state, int_state;
int i;
// Ignore unless device is idle/stopped
if ((qi->fec->eControl & eControl_EN) != 0) {
return true;
}
// Make sure interrupts are off while we mess with the device
HAL_DISABLE_INTERRUPTS(int_state);
// Ensure consistent state between cache and what the FEC sees
HAL_DCACHE_IS_ENABLED(cache_state);
HAL_DCACHE_SYNC();
HAL_DCACHE_DISABLE();
// Shut down ethernet controller, in case it is already running
fec->eControl = eControl_RESET;
i = 0;
while ((fec->eControl & eControl_RESET) != 0) {
if (++i >= 500000) {
os_printf("FEC Ethernet does not reset\n");
if (cache_state)
HAL_DCACHE_ENABLE();
HAL_RESTORE_INTERRUPTS(int_state);
return false;
}
}
fec->iMask = 0x0000000; // Disables all interrupts
fec->iEvent = 0xFFFFFFFF; // Clear all interrupts
fec->iVector = (1<<29); // Caution - must match FEC_ETH_INT above
#define ROUNDUP(b,s) (((unsigned long)(b) + (s-1)) & ~(s-1))
#ifdef FEC_USE_EPPC_BD
txbd = (struct fec_bd *)(0x2C00 + (cyg_uint32)eppc);
rxbd = &txbd[CYGNUM_DEVS_ETH_POWERPC_FEC_TxNUM];
#else
txbd = fec_eth_txring;
rxbd = fec_eth_rxring;
#endif
qi->tbase = qi->txbd = qi->tnext = txbd;
qi->rbase = qi->rxbd = qi->rnext = rxbd;
qi->txactive = 0;
RxBUF = (unsigned char *)ROUNDUP(&fec_eth_rxbufs[0][0], 32);
TxBUF = (unsigned char *)ROUNDUP(&fec_eth_txbufs[0][0], 32);
// setup buffer descriptors
for (i = 0; i < CYGNUM_DEVS_ETH_POWERPC_FEC_RxNUM; i++) {
rxbd->length = 0;
rxbd->buffer = RxBUF;
rxbd->ctrl = FEC_BD_Rx_Empty;
RxBUF += CYGNUM_DEVS_ETH_POWERPC_FEC_BUFSIZE;
rxbd++;
}
rxbd--;
rxbd->ctrl |= FEC_BD_Rx_Wrap; // Last buffer
for (i = 0; i < CYGNUM_DEVS_ETH_POWERPC_FEC_TxNUM; i++) {
txbd->length = 0;
txbd->buffer = TxBUF;
txbd->ctrl = 0;
TxBUF += CYGNUM_DEVS_ETH_POWERPC_FEC_BUFSIZE;
txbd++;
}
txbd--;
txbd->ctrl |= FEC_BD_Tx_Wrap; // Last buffer
// Reset interrupts
fec->iMask = 0x00000000; // No interrupts enabled
fec->iEvent = 0xFFFFFFFF; // Clear all interrupts
// Initialize shared PRAM
fec->RxRing = qi->rbase;
fec->TxRing = qi->tbase;
// Size of receive buffers
fec->RxBufSize = CYGNUM_DEVS_ETH_POWERPC_FEC_BUFSIZE;
// Receiver control
fec->RxControl = RxControl_MII | RxControl_DRT;
// fec->RxControl = RxControl_MII | RxControl_LOOP | RxControl_PROM;
fec->RxHash = IEEE_8023_MAX_FRAME; // Largest possible ethernet frame
// Transmit control
fec->TxControl = 4+0;
// Use largest possible Tx FIFO
fec->TxWater = 3;
// DMA control
fec->FunCode = ((2<<29) | (2<<27) | (0<<24));
// MII speed control (50MHz)
fec->MiiSpeed = 0x14;
// Group address hash
fec->hash[0] = 0;
fec->hash[1] = 0;
// Device physical address
fec->addr[0] = *(unsigned long *)&enaddr[0];
fec->addr[1] = *(unsigned long *)&enaddr[4];
// os_printf("FEC ESA = %08x/%08x\n", fec->addr[0], fec->addr[1]);
// Enable device
fec->eControl = eControl_EN | eControl_MUX;
fec->RxUpdate = 0x0F0F0F0F; // Any write tells machine to look for work
#ifdef _FEC_USE_INTS
// Set up for interrupts
fec->iMask = iEvent_TFINT | iEvent_TXB |
iEvent_RFINT | iEvent_RXB;
fec->iEvent = 0xFFFFFFFF; // Clear all interrupts
#endif
if (cache_state)
HAL_DCACHE_ENABLE();
// Set LED state
clear_led(LED_TxACTIVE);
clear_led(LED_RxACTIVE);
HAL_RESTORE_INTERRUPTS(int_state);
return true;
}
