static int __init dm646x_init_devices(void)
{
if (!cpu_is_davinci_dm646x())
return 0;
platform_device_register(&dm646x_mdio_device);
platform_device_register(&dm646x_emac_device);
clk_add_alias(NULL, dev_name(&dm646x_mdio_device.dev),
NULL, &dm646x_emac_device.dev);
return 0;
}
static void __init e800_init(void)
{
pxa2xx_mfp_config(ARRAY_AND_SIZE(e800_pin_config));
pxa_set_ffuart_info(NULL);
pxa_set_btuart_info(NULL);
pxa_set_stuart_info(NULL);
clk_add_alias("CLK_CK3P6MI", e800_tc6393xb_device.name,
"GPIO11_CLK", NULL),
eseries_get_tmio_gpios();
platform_add_devices(ARRAY_AND_SIZE(e800_devices));
pxa_set_ac97_info(NULL);
}
static void __init e800_init(void)
{
pxa_set_ffuart_info(NULL);
pxa_set_btuart_info(NULL);
pxa_set_stuart_info(NULL);
clk_add_alias("CLK_CK3P6MI", e800_tc6393xb_device.name,
"GPIO11_CLK", NULL),
eseries_get_tmio_gpios();
platform_add_devices(devices, ARRAY_SIZE(devices));
pxa_set_udc_info(&e800_udc_mach_info);
pxa_set_ac97_info(NULL);
}
static int __init dm644x_init_devices(void)
{
if (!cpu_is_davinci_dm644x())
return 0;
/* Add ccdc clock aliases */
clk_add_alias("master", dm644x_ccdc_dev.name, "vpss_master", NULL);
clk_add_alias("slave", dm644x_ccdc_dev.name, "vpss_slave", NULL);
platform_device_register(&dm644x_edma_device);
platform_device_register(&dm644x_mdio_device);
platform_device_register(&dm644x_emac_device);
clk_add_alias(NULL, dev_name(&dm644x_mdio_device.dev),
NULL, &dm644x_emac_device.dev);
platform_device_register(&dm644x_vpss_device);
platform_device_register(&dm644x_ccdc_dev);
platform_device_register(&vpfe_capture_dev);
return 0;
}
static void __init omap4_ehci_init(void)
{
int ret;
/* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */
ret = clk_add_alias("main_clk", "nop_usb_xceiv.1", "auxclk3_ck", NULL);
if (ret)
pr_err("Failed to add main_clk alias to auxclk3_ck\n");
usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
usbhs_init(&usbhs_bdata);
}
static void __init e740_init(void)
{
pxa2xx_mfp_config(ARRAY_AND_SIZE(e740_pin_config));
pxa_set_ffuart_info(NULL);
pxa_set_btuart_info(NULL);
pxa_set_stuart_info(NULL);
eseries_register_clks();
clk_add_alias("CLK_CK48M", e740_t7l66xb_device.name,
"UDCCLK", &pxa25x_device_udc.dev),
eseries_get_tmio_gpios();
platform_add_devices(ARRAY_AND_SIZE(e740_devices));
pxa_set_ac97_info(NULL);
pxa_set_ficp_info(&e7xx_ficp_platform_data);
}
int __init da8xx_register_emac(void)
{
int ret;
ret = platform_device_register(&da8xx_mdio_device);
if (ret < 0)
return ret;
ret = platform_device_register(&da8xx_emac_device);
if (ret < 0)
return ret;
ret = clk_add_alias(NULL, dev_name(&da8xx_mdio_device.dev),
NULL, &da8xx_emac_device.dev);
return ret;
}
void am33xx_cpsw_init(unsigned int gigen)
{
u32 mac_lo, mac_hi;
u32 i;
mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_LO);
mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_HI);
am33xx_cpsw_slaves[0].mac_addr[0] = mac_hi & 0xFF;
am33xx_cpsw_slaves[0].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
am33xx_cpsw_slaves[0].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
am33xx_cpsw_slaves[0].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
am33xx_cpsw_slaves[0].mac_addr[4] = mac_lo & 0xFF;
am33xx_cpsw_slaves[0].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
/* Read MACID0 from eeprom if eFuse MACID is invalid */
if (!is_valid_ether_addr(am33xx_cpsw_slaves[0].mac_addr)) {
for (i = 0; i < ETH_ALEN; i++)
am33xx_cpsw_slaves[0].mac_addr[i] = am33xx_macid0[i];
}
mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_LO);
mac_hi = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID1_HI);
am33xx_cpsw_slaves[1].mac_addr[0] = mac_hi & 0xFF;
am33xx_cpsw_slaves[1].mac_addr[1] = (mac_hi & 0xFF00) >> 8;
am33xx_cpsw_slaves[1].mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
am33xx_cpsw_slaves[1].mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
am33xx_cpsw_slaves[1].mac_addr[4] = mac_lo & 0xFF;
am33xx_cpsw_slaves[1].mac_addr[5] = (mac_lo & 0xFF00) >> 8;
/* Read MACID1 from eeprom if eFuse MACID is invalid */
if (!is_valid_ether_addr(am33xx_cpsw_slaves[1].mac_addr)) {
for (i = 0; i < ETH_ALEN; i++)
am33xx_cpsw_slaves[1].mac_addr[i] = am33xx_macid1[i];
}
if (am33xx_evmid == IND_AUT_MTR_EVM) {
am33xx_cpsw_slaves[0].phy_id = "0:1e";
am33xx_cpsw_slaves[1].phy_id = "0:00";
}
am33xx_cpsw_pdata.gigabit_en = gigen;
memcpy(am33xx_cpsw_pdata.mac_addr,
am33xx_cpsw_slaves[0].mac_addr, ETH_ALEN);
platform_device_register(&am33xx_cpsw_mdiodevice);
platform_device_register(&am33xx_cpsw_device);
clk_add_alias(NULL, dev_name(&am33xx_cpsw_mdiodevice.dev),
NULL, &am33xx_cpsw_device.dev);
}
static int __init dm365_init_devices(void)
{
if (!cpu_is_davinci_dm365())
return 0;
davinci_cfg_reg(DM365_INT_EDMA_CC);
platform_device_register(&dm365_edma_device);
platform_device_register(&dm365_emac_device);
/* Add isif clock alias */
clk_add_alias("master", dm365_isif_dev.name, "vpss_master", NULL);
platform_device_register(&dm365_vpss_device);
platform_device_register(&dm365_isif_dev);
platform_device_register(&vpfe_capture_dev);
return 0;
}
static void _add_clkdev(struct omap_device *od, const char *clk_alias,
const char *clk_name)
{
struct clk *r;
int rc;
if (!clk_alias || !clk_name)
return;
dev_dbg(&od->pdev->dev, "Creating %s -> %s\n", clk_alias, clk_name);
r = clk_get_sys(dev_name(&od->pdev->dev), clk_alias);
if (!IS_ERR(r)) {
dev_dbg(&od->pdev->dev,
"alias %s already exists\n", clk_alias);
clk_put(r);
return;
}
r = clk_get_sys(NULL, clk_name);
if (IS_ERR(r)) {
struct of_phandle_args clkspec;
clkspec.np = of_find_node_by_name(NULL, clk_name);
r = of_clk_get_from_provider(&clkspec);
rc = clk_register_clkdev(r, clk_alias,
dev_name(&od->pdev->dev));
} else {
rc = clk_add_alias(clk_alias, dev_name(&od->pdev->dev),
clk_name, NULL);
}
if (rc) {
if (rc == -ENODEV || rc == -ENOMEM)
dev_err(&od->pdev->dev,
"clkdev_alloc for %s failed\n", clk_alias);
else
dev_err(&od->pdev->dev,
"clk_get for %s failed\n", clk_name);
}
}
/**
* _add_optional_clock_alias - Add clock alias for hwmod optional clocks
* @od: struct omap_device *od
*
* For every optional clock present per hwmod per omap_device, this function
* adds an entry in the clocks list of the form <dev-id=dev_name, con-id=role>
* if an entry is already present in it with the form <dev-id=NULL, con-id=role>
*
* The function is called from inside omap_device_build_ss(), after
* omap_device_register.
*
* This allows drivers to get a pointer to its optional clocks based on its role
* by calling clk_get(<dev*>, <role>).
*/
static void _add_optional_clock_alias(struct omap_device *od,
struct omap_hwmod *oh)
{
int i;
struct omap_hwmod_opt_clk *oc;
for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
int ret;
if (!oc->_clk || !IS_ERR(clk_get(&od->pdev.dev, oc->role)))
return;
ret = clk_add_alias(oc->role, dev_name(&od->pdev.dev),
(char *)oc->clk, NULL);
if (ret)
pr_err("omap_device: clk_add_alias for %s failed\n",
oc->role);
}
}
static void __init tosa_init(void)
{
int dummy;
pxa2xx_mfp_config(ARRAY_AND_SIZE(tosa_pin_config));
pxa_set_ffuart_info(NULL);
pxa_set_btuart_info(NULL);
pxa_set_stuart_info(NULL);
gpio_set_wake(MFP_PIN_GPIO1, 1);
/* We can't pass to gpio-keys since it will drop the Reset altfunc */
init_gpio_reset(TOSA_GPIO_ON_RESET, 0, 0);
pm_power_off = tosa_poweroff;
arm_pm_restart = tosa_restart;
PCFR |= PCFR_OPDE;
/* enable batt_fault */
PMCR = 0x01;
dummy = gpiochip_reserve(TOSA_SCOOP_GPIO_BASE, 12);
dummy = gpiochip_reserve(TOSA_SCOOP_JC_GPIO_BASE, 12);
dummy = gpiochip_reserve(TOSA_TC6393XB_GPIO_BASE, 16);
pxa_set_mci_info(&tosa_mci_platform_data);
pxa_set_udc_info(&udc_info);
pxa_set_ficp_info(&tosa_ficp_platform_data);
pxa_set_i2c_info(NULL);
pxa_set_ac97_info(NULL);
platform_scoop_config = &tosa_pcmcia_config;
pxa2xx_set_spi_info(2, &pxa_ssp_master_info);
spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
clk_add_alias("CLK_CK3P6MI", tc6393xb_device.name, "GPIO11_CLK", NULL);
platform_add_devices(devices, ARRAY_SIZE(devices));
}
/**
* _add_optional_clock_alias - Add clock alias for hwmod optional clocks
* @od: struct omap_device *od
*
* For every optional clock present per hwmod per omap_device, this function
* adds an entry in the clocks list of the form <dev-id=dev_name, con-id=role>
* if an entry is already present in it with the form <dev-id=NULL, con-id=role>
*
* The function is called from inside omap_device_build_ss(), after
* omap_device_register.
*
* This allows drivers to get a pointer to its optional clocks based on its role
* by calling clk_get(<dev*>, <role>).
*
* No return value.
*/
static void _add_optional_clock_alias(struct omap_device *od,
struct omap_hwmod *oh)
{
int i;
for (i = 0; i < oh->opt_clks_cnt; i++) {
struct omap_hwmod_opt_clk *oc;
int r;
oc = &oh->opt_clks[i];
if (!oc->_clk)
continue;
r = clk_add_alias(oc->role, dev_name(&od->pdev.dev),
(char *)oc->clk, &od->pdev.dev);
if (r)
pr_err("omap_device: %s: clk_add_alias for %s failed\n",
dev_name(&od->pdev.dev), oc->role);
}
}
int __init __deprecated cpg_clk_init(void)
{
int i, ret = 0;
for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) {
struct clk *clk = onchip_clocks[i];
arch_init_clk_ops(&clk->ops, i);
if (clk->ops)
ret |= clk_register(clk);
}
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
clk_add_alias("fck", "sh-tmu-sh3.0", "peripheral_clk", NULL);
clk_add_alias("fck", "sh-tmu.0", "peripheral_clk", NULL);
clk_add_alias("fck", "sh-tmu.1", "peripheral_clk", NULL);
clk_add_alias("fck", "sh-tmu.2", "peripheral_clk", NULL);
clk_add_alias("fck", "sh-mtu2", "peripheral_clk", NULL);
clk_add_alias("fck", "sh-cmt-16.0", "peripheral_clk", NULL);
clk_add_alias("fck", "sh-cmt-32.0", "peripheral_clk", NULL);
clk_add_alias("sci_ick", NULL, "peripheral_clk", NULL);
return ret;
}
void __init exynos5_xyref5260_display_init(void)
{
#ifdef CONFIG_S5P_DP
int irq;
#endif
clk_add_alias("sclk_fimd", "exynos5-fb.1", "sclk_fimd1_128_extclkpl",
&s5p_device_fimd1.dev);
#ifdef CONFIG_FB_MIPI_DSIM
s5p_dsim1_set_platdata(&dsim_platform_data);
#endif
#ifdef CONFIG_S5P_DP
s5p_dp_set_platdata(&xyref5260_dp_data);
#endif
s5p_fimd1_set_platdata(&smdk5260_lcd1_pdata);
#ifdef CONFIG_BACKLIGHT_PWM
samsung_bl_set(&smdk5260_bl_gpio_info, &smdk5260_bl_data);
#endif
platform_add_devices(smdk5260_display_devices,
ARRAY_SIZE(smdk5260_display_devices));
#ifdef CONFIG_S5P_DP
irq = s5p_register_gpio_interrupt(EXYNOS5260_GPK0(0));
if (IS_ERR_VALUE(irq)) {
pr_err("%s: Failed to configure GPK0(0) GPIO\n", __func__);
return;
}
exynos5_fimd1_setup_clock(&s5p_device_fimd1.dev,
"sclk_fimd", "sclk_disp_pixel", 267 * MHZ);
#endif
#ifdef CONFIG_FB_MIPI_DSIM
/* RPLL rate is 300Mhz, 300/5=60Hz */
exynos5_fimd1_setup_clock(&s5p_device_fimd1.dev,
"sclk_fimd", "sclk_disp_pixel", 266 * MHZ);
#endif
}
int __init plat_clk_alias_init(void)
{
/* core clocks */
clk_add_alias("cpu_clk", NULL, "CLKA_SH4L2_ICK", NULL);
clk_add_alias("gpu_clk", NULL, "CLKA_IC_GPU", NULL);
clk_add_alias("module_clk", NULL, "CLKA_IC_REG_LP_ON", NULL);
clk_add_alias("tmu_fck", NULL, "CLKA_IC_REG_LP_ON", NULL);
clk_add_alias("comms_clk", NULL, "CLKA_IC_REG_LP_ON", NULL);
/* EMI clock */
clk_add_alias("emi_clk", NULL, "CLKA_SYS_EMISS", NULL);
/* fdmas clocks */
clk_add_alias("fdma_slim_clk", "stm-fdma.0", "CLKA_SLIM_FDMA_0", NULL);
clk_add_alias("fdma_slim_clk", "stm-fdma.1", "CLKA_SLIM_FDMA_1", NULL);
clk_add_alias("fdma_slim_clk", "stm-fdma.2", "CLKA_SLIM_FDMA_2", NULL);
clk_add_alias("fdma_hi_clk", NULL, "CLKA_IC_REG_LP_ON", NULL);
clk_add_alias("fdma_low_clk", NULL, "CLKA_IC_TS_DMA", NULL);
clk_add_alias("fdma_ic_clk", NULL, "CLKA_IC_REG_LP_ON", NULL);
/* SDHCI clocks */
clk_add_alias(NULL, "sdhci-stm.0", "CLKA_CARD_MMC_SS", NULL);
/* USB clocks */
clk_add_alias("usb_48_clk", NULL, "CLKB_FS1_CH3", NULL);
clk_add_alias("usb_ic_clk", NULL, "CLKA_IC_REG_LP_OFF", NULL);
/* usb_phy_clk got from external oscillator */
/* ALSA clocks */
clk_add_alias("pcm_player_clk", "snd_pcm_player.0", "CLKC_FS0_CH1",
NULL);
clk_add_alias("pcm_player_clk", "snd_pcm_player.1", "CLKC_FS0_CH2",
NULL);
clk_add_alias("pcm_player_clk", "snd_pcm_player.2", "CLKC_FS0_CH4",
NULL);
clk_add_alias("spdif_player_clk", NULL, "CLKC_FS0_CH3", NULL);
clk_add_alias("stmmaceth", NULL, "CLKA_IC_GMAC_1", NULL);
return 0;
}
static void manta_audio_setup_clocks(void)
{
struct clk *fout_epll, *mout_epll;
struct clk *sclk_audio, *sclk_spdif;
struct clk *xxti;
int ret;
fout_epll = clk_get(NULL, "fout_epll");
if (IS_ERR(fout_epll)) {
pr_err("%s:cannot get fout_epll clock\n", __func__);
return;
}
mout_epll = clk_get(NULL, "mout_epll");
if (IS_ERR(mout_epll)) {
pr_err("%s: cannot get mout_epll clock\n", __func__);
goto out1;
}
sclk_audio = clk_get(NULL, "sclk_audio");
if (IS_ERR(sclk_audio)) {
pr_err("%s: cannot get sclk_audio clock\n", __func__);
goto out2;
}
sclk_spdif = clk_get(NULL, "sclk_spdif");
if (IS_ERR(sclk_spdif)) {
pr_err("%s: cannot get sclk_spdif clock\n", __func__);
goto out3;
}
xxti = clk_get(NULL, "xxti");
if (IS_ERR(xxti)) {
pr_err("%s: cannot get xxti clock\n", __func__);
goto out4;
}
clkout = clk_get(NULL, "clkout");
if (IS_ERR(clkout)) {
pr_err("%s: cannot get clkout\n", __func__);
goto out5;
}
clk_set_parent(mout_epll, fout_epll);
clk_set_parent(sclk_audio, mout_epll);
clk_set_parent(sclk_spdif, sclk_audio);
clk_set_parent(clkout, xxti);
clk_add_alias("system_clk", "manta-i2s", "clkout", NULL);
ret = gpio_request(GPIO_ES305_CLK_EN, "ES305 clk_en");
if (ret < 0) {
pr_err("%s: error requesting ES305 clk_en gpio\n", __func__);
goto out6;
}
gpio_direction_output(GPIO_ES305_CLK_EN, 0);
clk_put(fout_epll);
clk_put(mout_epll);
clk_put(sclk_audio);
clk_put(sclk_spdif);
clk_put(xxti);
return;
out6:
clk_put(clkout);
out5:
clk_put(xxti);
out4:
clk_put(sclk_spdif);
out3:
clk_put(sclk_audio);
out2:
clk_put(mout_epll);
out1:
clk_put(fout_epll);
}
void __init exynos5_xyref5260_camera_init(void)
{
#if defined(CONFIG_VIDEO_EXYNOS_FIMC_IS)
dev_set_name(&exynos5_device_fimc_is.dev, "s5p-mipi-csis.0");
clk_add_alias("gscl_wrap0", FIMC_IS_DEV_NAME,
"gscl_wrap0", &exynos5_device_fimc_is.dev);
dev_set_name(&exynos5_device_fimc_is.dev, "s5p-mipi-csis.1");
clk_add_alias("gscl_wrap1", FIMC_IS_DEV_NAME,
"gscl_wrap1", &exynos5_device_fimc_is.dev);
dev_set_name(&exynos5_device_fimc_is.dev, FIMC_IS_DEV_NAME);
exynos_fimc_is_data.subip_info = &subip_info;
/* DVFS sceanrio setting */
SET_QOS(exynos_fimc_is_data.dvfs_data, FIMC_IS_SN_DEFAULT,
400000, 667000, 75000000, 0, 333000, 2666);
SET_QOS(exynos_fimc_is_data.dvfs_data, FIMC_IS_SN_FRONT_PREVIEW,
400000, 667000, 75000000, 0, 333000, 2666);
SET_QOS(exynos_fimc_is_data.dvfs_data, FIMC_IS_SN_FRONT_CAPTURE,
400000, 667000, 75000000, 0, 333000, 2666);
SET_QOS(exynos_fimc_is_data.dvfs_data, FIMC_IS_SN_FRONT_CAMCORDING,
400000, 667000, 75000000, 0, 333000, 2666);
SET_QOS(exynos_fimc_is_data.dvfs_data, FIMC_IS_SN_FRONT_VT1,
400000, 667000, 75000000, 0, 333000, 2666);
SET_QOS(exynos_fimc_is_data.dvfs_data, FIMC_IS_SN_FRONT_VT2,
400000, 667000, 75000000, 0, 333000, 2666);
SET_QOS(exynos_fimc_is_data.dvfs_data, FIMC_IS_SN_REAR_PREVIEW_FHD,
400000, 667000, 75000000, 0, 333000, 2666);
SET_QOS(exynos_fimc_is_data.dvfs_data, FIMC_IS_SN_REAR_PREVIEW_WHD,
400000, 667000, 75000000, 0, 333000, 2666);
SET_QOS(exynos_fimc_is_data.dvfs_data, FIMC_IS_SN_REAR_PREVIEW_UHD,
400000, 667000, 75000000, 0, 333000, 2666);
SET_QOS(exynos_fimc_is_data.dvfs_data, FIMC_IS_SN_REAR_CAPTURE,
533000, 667000, 100000000, 0, 333000, 2000);
SET_QOS(exynos_fimc_is_data.dvfs_data, FIMC_IS_SN_REAR_CAMCORDING,
400000, 667000, 75000000, 0, 333000, 2666);
SET_QOS(exynos_fimc_is_data.dvfs_data, FIMC_IS_SN_DUAL_PREVIEW,
400000, 667000, 75000000, 0, 333000, 2666);
SET_QOS(exynos_fimc_is_data.dvfs_data, FIMC_IS_SN_DUAL_CAPTURE,
400000, 667000, 75000000, 0, 333000, 2666);
SET_QOS(exynos_fimc_is_data.dvfs_data, FIMC_IS_SN_DUAL_CAMCORDING,
400000, 667000, 75000000, 0, 333000, 2666);
SET_QOS(exynos_fimc_is_data.dvfs_data, FIMC_IS_SN_HIGH_SPEED_FPS,
400000, 667000, 75000000, 0, 333000, 2666);
SET_QOS(exynos_fimc_is_data.dvfs_data, FIMC_IS_SN_DIS_ENABLE,
400000, 667000, 75000000, 0, 333000, 2666);
SET_QOS(exynos_fimc_is_data.dvfs_data, FIMC_IS_SN_MAX,
400000, 667000, 75000000, 0, 333000, 2666);
exynos_fimc_is_data.gate_info = &gate_info;
exynos_fimc_is_set_platdata(&exynos_fimc_is_data);
/* s5k3h7: normal: on */
SET_PIN(&s5k3h7, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 0,
EXYNOS5260_GPE1(2), (2 << 8), "GPE1.2 (CAM_MCLK)", PIN_FUNCTION);
SET_PIN(&s5k3h7, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 1,
EXYNOS5260_GPE0(5), (2 << 20), "GPE0.5 (CAM_FLASH_EN)", PIN_FUNCTION);
SET_PIN(&s5k3h7, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 2,
EXYNOS5260_GPF0(1), (2 << 4), "GPF0.1 (CAM_I2C0_SCL)", PIN_FUNCTION);
SET_PIN(&s5k3h7, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 3,
EXYNOS5260_GPF0(0), (2 << 0), "GPE0.0 (CAM_I2C0_SDA)", PIN_FUNCTION);
SET_PIN(&s5k3h7, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 5,
0, 0, "main_cam_io_1v8", PIN_REGULATOR_ON);
SET_PIN(&s5k3h7, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 6,
0, 0, "main_cam_sensor_a2v8", PIN_REGULATOR_ON);
SET_PIN(&s5k3h7, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 7,
0, 0, "main_cam_af_2v8", PIN_REGULATOR_ON);
SET_PIN(&s5k3h7, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 8,
EXYNOS5260_GPE0(6), 1, "GPE0.6 (CAMCORE_EN)", PIN_OUTPUT_HIGH);
SET_PIN(&s5k3h7, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 9,
EXYNOS5260_GPE0(1), 1, "GPE0.1 (MAIN_CAM_RST)", PIN_RESET);
#if defined(CONFIG_EXYNOS5260_XYREF_REV1)
SET_PIN(&s5k3h7, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 10,
EXYNOS5260_GPE1(0), (2 << 0), "GPE1.0 (CAM_FLASH_TORCH)",
PIN_FUNCTION);
SET_PIN(&s5k3h7, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 11,
0, 0, "", PIN_END);
#else
SET_PIN(&s5k3h7, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 10,
0, 0, "", PIN_END);
#endif
/* s5k3h7: normal: off */
SET_PIN(&s5k3h7, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, 0,
EXYNOS5260_GPE0(1), 1, "GPE0.1 (MAIN_CAM_RST)", PIN_RESET);
SET_PIN(&s5k3h7, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, 1,
EXYNOS5260_GPE0(1), 1, "GPE0.1 (MAIN_CAM_RST)", PIN_INPUT);
SET_PIN(&s5k3h7, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, 2,
EXYNOS5260_GPE0(6), 1, "GPE0.6 (CAMCORE_EN)", PIN_OUTPUT_LOW);
SET_PIN(&s5k3h7, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, 3,
0, 0, "main_cam_io_1v8", PIN_REGULATOR_OFF);
SET_PIN(&s5k3h7, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, 4,
0, 0, "main_cam_sensor_a2v8", PIN_REGULATOR_OFF);
SET_PIN(&s5k3h7, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, 5,
0, 0, "main_cam_af_2v8", PIN_REGULATOR_OFF);
#if defined(CONFIG_EXYNOS5260_XYREF_REV1)
SET_PIN(&s5k3h7, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, 6,
EXYNOS5260_GPE1(0), 1, "GPE1.0 (CAM_FLASH_TORCH)", PIN_INPUT);
SET_PIN(&s5k3h7, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, 7,
0, 0, "", PIN_END);
#else
SET_PIN(&s5k3h7, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, 6,
0, 0, "", PIN_END);
#endif
/* s5k6b2: normal: on */
SET_PIN(&s5k6b2, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 0,
EXYNOS5260_GPE0(4), 1, "GPE0.4 (CAM_VT_nRST)", PIN_RESET);
SET_PIN(&s5k6b2, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 1,
EXYNOS5260_GPE1(3), (2 << 12), "GPE1.3 (CAM_MCLK)", PIN_FUNCTION);
SET_PIN(&s5k6b2, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 2,
EXYNOS5260_GPF0(3), (2 << 12), "GPE0.3 (CAM_I2C1_SCL)", PIN_FUNCTION);
SET_PIN(&s5k6b2, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 3,
EXYNOS5260_GPF0(2), (2 << 8), "GPE0.2 (CAM_I2C1_SDA)", PIN_FUNCTION);
SET_PIN(&s5k6b2, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 4,
0, 0, "vt_cam_core_1v8", PIN_REGULATOR_ON);
SET_PIN(&s5k6b2, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 5,
0, 0, "vt_cam_sensor_a2v8", PIN_REGULATOR_ON);
SET_PIN(&s5k6b2, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 6,
0, 0, "", PIN_END);
/* s5k6b2: normal: off */
SET_PIN(&s5k6b2, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, 0,
EXYNOS5260_GPE0(4), 1, "GPE0.4 (CAM_VT_nRST)", PIN_RESET);
SET_PIN(&s5k6b2, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, 1,
EXYNOS5260_GPE0(4), 1, "GPE0.4 (CAM_VT_nRST)", PIN_INPUT);
SET_PIN(&s5k6b2, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, 2,
0, 0, "vt_cam_core_1v8", PIN_REGULATOR_OFF);
SET_PIN(&s5k6b2, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, 3,
0, 0, "vt_cam_sensor_a2v8", PIN_REGULATOR_OFF);
SET_PIN(&s5k6b2, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, 4,
0, 0, "", PIN_END);
exynos_fimc_is_sensor_set_platdata(&s5k3h7, &exynos_device_fimc_is_sensor0);
exynos_fimc_is_sensor_set_platdata(&s5k6b2, &exynos_device_fimc_is_sensor1);
#endif
platform_add_devices(camera_devices, ARRAY_SIZE(camera_devices));
}
static int __init migor_devices_setup(void)
{
struct clk *video_clk;
/* register board specific self-refresh code */
sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
&migor_sdram_enter_start,
&migor_sdram_enter_end,
&migor_sdram_leave_start,
&migor_sdram_leave_end);
regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
/* Let D11 LED show STATUS0 */
gpio_request(GPIO_FN_STATUS0, NULL);
/* Lit D12 LED show PDSTATUS */
gpio_request(GPIO_FN_PDSTATUS, NULL);
/* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
gpio_request(GPIO_FN_IRQ0, NULL);
__raw_writel(0x00003400, BSC_CS4BCR);
__raw_writel(0x00110080, BSC_CS4WCR);
/* KEYSC */
gpio_request(GPIO_FN_KEYOUT0, NULL);
gpio_request(GPIO_FN_KEYOUT1, NULL);
gpio_request(GPIO_FN_KEYOUT2, NULL);
gpio_request(GPIO_FN_KEYOUT3, NULL);
gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
gpio_request(GPIO_FN_KEYIN1, NULL);
gpio_request(GPIO_FN_KEYIN2, NULL);
gpio_request(GPIO_FN_KEYIN3, NULL);
gpio_request(GPIO_FN_KEYIN4, NULL);
gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
/* NAND Flash */
gpio_request(GPIO_FN_CS6A_CE2B, NULL);
__raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR);
gpio_request(GPIO_PTA1, NULL);
gpio_direction_input(GPIO_PTA1);
/* SDHI */
gpio_request(GPIO_FN_SDHICD, NULL);
gpio_request(GPIO_FN_SDHIWP, NULL);
gpio_request(GPIO_FN_SDHID3, NULL);
gpio_request(GPIO_FN_SDHID2, NULL);
gpio_request(GPIO_FN_SDHID1, NULL);
gpio_request(GPIO_FN_SDHID0, NULL);
gpio_request(GPIO_FN_SDHICMD, NULL);
gpio_request(GPIO_FN_SDHICLK, NULL);
/* Touch Panel */
gpio_request(GPIO_FN_IRQ6, NULL);
/* LCD Panel */
#ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */
gpio_request(GPIO_FN_LCDD17, NULL);
gpio_request(GPIO_FN_LCDD16, NULL);
gpio_request(GPIO_FN_LCDD15, NULL);
gpio_request(GPIO_FN_LCDD14, NULL);
gpio_request(GPIO_FN_LCDD13, NULL);
gpio_request(GPIO_FN_LCDD12, NULL);
gpio_request(GPIO_FN_LCDD11, NULL);
gpio_request(GPIO_FN_LCDD10, NULL);
gpio_request(GPIO_FN_LCDD8, NULL);
gpio_request(GPIO_FN_LCDD7, NULL);
gpio_request(GPIO_FN_LCDD6, NULL);
gpio_request(GPIO_FN_LCDD5, NULL);
gpio_request(GPIO_FN_LCDD4, NULL);
gpio_request(GPIO_FN_LCDD3, NULL);
gpio_request(GPIO_FN_LCDD2, NULL);
gpio_request(GPIO_FN_LCDD1, NULL);
gpio_request(GPIO_FN_LCDRS, NULL);
gpio_request(GPIO_FN_LCDCS, NULL);
gpio_request(GPIO_FN_LCDRD, NULL);
gpio_request(GPIO_FN_LCDWR, NULL);
gpio_request(GPIO_PTH2, NULL); /* LCD_DON */
gpio_direction_output(GPIO_PTH2, 1);
#endif
#ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */
gpio_request(GPIO_FN_LCDD15, NULL);
gpio_request(GPIO_FN_LCDD14, NULL);
gpio_request(GPIO_FN_LCDD13, NULL);
gpio_request(GPIO_FN_LCDD12, NULL);
gpio_request(GPIO_FN_LCDD11, NULL);
gpio_request(GPIO_FN_LCDD10, NULL);
gpio_request(GPIO_FN_LCDD9, NULL);
gpio_request(GPIO_FN_LCDD8, NULL);
gpio_request(GPIO_FN_LCDD7, NULL);
gpio_request(GPIO_FN_LCDD6, NULL);
gpio_request(GPIO_FN_LCDD5, NULL);
gpio_request(GPIO_FN_LCDD4, NULL);
gpio_request(GPIO_FN_LCDD3, NULL);
gpio_request(GPIO_FN_LCDD2, NULL);
gpio_request(GPIO_FN_LCDD1, NULL);
gpio_request(GPIO_FN_LCDD0, NULL);
gpio_request(GPIO_FN_LCDLCLK, NULL);
gpio_request(GPIO_FN_LCDDCK, NULL);
gpio_request(GPIO_FN_LCDVEPWC, NULL);
gpio_request(GPIO_FN_LCDVCPWC, NULL);
gpio_request(GPIO_FN_LCDVSYN, NULL);
gpio_request(GPIO_FN_LCDHSYN, NULL);
gpio_request(GPIO_FN_LCDDISP, NULL);
gpio_request(GPIO_FN_LCDDON, NULL);
#endif
/* CEU */
gpio_request(GPIO_FN_VIO_CLK2, NULL);
gpio_request(GPIO_FN_VIO_VD2, NULL);
gpio_request(GPIO_FN_VIO_HD2, NULL);
gpio_request(GPIO_FN_VIO_FLD, NULL);
gpio_request(GPIO_FN_VIO_CKO, NULL);
gpio_request(GPIO_FN_VIO_D15, NULL);
gpio_request(GPIO_FN_VIO_D14, NULL);
gpio_request(GPIO_FN_VIO_D13, NULL);
gpio_request(GPIO_FN_VIO_D12, NULL);
gpio_request(GPIO_FN_VIO_D11, NULL);
gpio_request(GPIO_FN_VIO_D10, NULL);
gpio_request(GPIO_FN_VIO_D9, NULL);
gpio_request(GPIO_FN_VIO_D8, NULL);
__raw_writew(__raw_readw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */
/* SIU: Port B */
gpio_request(GPIO_FN_SIUBOLR, NULL);
gpio_request(GPIO_FN_SIUBOBT, NULL);
gpio_request(GPIO_FN_SIUBISLD, NULL);
gpio_request(GPIO_FN_SIUBOSLD, NULL);
gpio_request(GPIO_FN_SIUMCKB, NULL);
/*
* The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to
* output. Need only SIUB, set to output for master mode (table 34.2)
*/
__raw_writew(__raw_readw(PORT_MSELCRA) | 1, PORT_MSELCRA);
/*
* Use 10 MHz VIO_CKO instead of 24 MHz to work around signal quality
* issues on Panel Board V2.1.
*/
video_clk = clk_get(NULL, "video_clk");
if (!IS_ERR(video_clk)) {
clk_set_rate(video_clk, clk_round_rate(video_clk, 10000000));
clk_put(video_clk);
}
/* Add a clock alias for ov7725 xclk source. */
clk_add_alias(NULL, "0-0021", "video_clk", NULL);
/* Register GPIOs for video sources. */
gpiod_add_lookup_table(&ov7725_gpios);
gpiod_add_lookup_table(&tw9910_gpios);
i2c_register_board_info(0, migor_i2c_devices,
ARRAY_SIZE(migor_i2c_devices));
/* Initialize CEU platform device separately to map memory first */
device_initialize(&migor_ceu_device.dev);
arch_setup_pdev_archdata(&migor_ceu_device);
dma_declare_coherent_memory(&migor_ceu_device.dev,
ceu_dma_membase, ceu_dma_membase,
ceu_dma_membase + CEU_BUFFER_MEMORY_SIZE - 1,
DMA_MEMORY_EXCLUSIVE);
platform_device_add(&migor_ceu_device);
return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
}
static void __init hwa742_dev_init(void)
{
clk_add_alias("hwa_sys_ck", NULL, "bclk", NULL);
omapfb_set_ctrl_platform_data(&nokia770_hwa742_platform_data);
}
int __init plat_clk_alias_init(void)
{
/* core clocks */
clk_add_alias("cpu_clk", NULL, "st40_clk", NULL);
clk_add_alias("module_clk", NULL, "st40_per_clk", NULL);
clk_add_alias("comms_clk", NULL, "ic_100_clk", NULL);
/* EMI clock */
/* alias not required because already registered as "emi_clk" */
/* fdmas clocks */
clk_add_alias("fdma_slim_clk", NULL, "slim_clk", NULL);
clk_add_alias("fdma_hi_clk", NULL, "ic_100_clk", NULL);
clk_add_alias("fdma_low_clk", NULL, "ic_clk", NULL);
clk_add_alias("fdma_ic_clk", NULL, "ic_100_clk", NULL);
/* USB clocks */
clk_add_alias("usb_ic_clk", NULL, "ic_100_clk", NULL);
/* usb_phy_clk generated internally to the wrapped system PLL */
/* usb_48_clk generated internally to the wrapped system PLL */
clk_add_alias("pcm_player_clk", "snd_pcm_player.0", "CLKC_FS0_CH1",
NULL);
clk_add_alias("pcm_player_clk", "snd_pcm_player.1", "CLKC_FS0_CH2",
NULL);
clk_add_alias("spdif_player_clk", NULL, "CLKC_FS0_CH3", NULL);
return 0;
}
void __init sunxi_init_clocks(void)
{
int i;
struct clk *clk;
struct factor_init_data *factor;
struct periph_init_data *periph;
#ifdef CONFIG_SUNXI_CLK_DUMMY_DEBUG
sunxi_clk_base = &dummy_reg[0];
dummy_reg_init();
#else
/* get clk register base address */
sunxi_clk_base = IO_ADDRESS(0x01c20000); //no change here
sunxi_clk_cpus_base = IO_ADDRESS(0x01F01400); // I get it from "1677 PRCM Spec"
#endif
sunxi_clk_factor_initlimits();
/* register oscs */
clk = clk_register_fixed_rate(NULL, "losc", NULL, CLK_IS_ROOT, 32768);
clk_register_clkdev(clk, "losc", NULL);
clk = clk_register_fixed_rate(NULL, "hosc", NULL, CLK_IS_ROOT, 24000000);
clk_register_clkdev(clk, "hosc", NULL);
sunxi_clk_get_factors_ops(&pll_mipi_ops);
pll_mipi_ops.get_parent = get_parent_pll_mipi;
pll_mipi_ops.set_parent = set_parent_pll_mipi;
pll_mipi_ops.enable = clk_enable_pll_mipi;
pll_mipi_ops.disable = clk_disable_pll_mipi;
/* register normal factors, based on sunxi factor framework */
for(i=0; i<ARRAY_SIZE(sunxi_factos); i++) {
factor = &sunxi_factos[i];
clk = sunxi_clk_register_factors(NULL, sunxi_clk_base, &clk_lock,factor);
clk_register_clkdev(clk, factor->name, NULL);
}
/* register fixed factors, based on clk-fixed-factor framework, such as pllx2 for ex. */
clk = clk_register_fixed_factor(NULL, "pll_audiox4", "pll_audio", 0, 8, 2);
clk_register_clkdev(clk, "pll_audiox4", NULL);
clk = clk_register_fixed_factor(NULL, "pll_videox2", "pll_video", 0, 2, 1);
clk_register_clkdev(clk, "pll_videox2", NULL);
clk = clk_register_fixed_factor(NULL, "pll_periph0x2", "pll_periph0", 0, 2, 1);
clk_register_clkdev(clk, "pll_periph0x2", NULL);
clk = clk_register_fixed_factor(NULL, "hoscd2", "hosc", 0, 1, 2);
clk_register_clkdev(clk, "hoscd2", NULL);
/* force enable only for sun8iw5 PLLs */
for(i=0;i < ARRAY_SIZE(force_enable_clks);i++)
{
clk = clk_get(NULL,force_enable_clks[i]);
if(!clk || IS_ERR(clk))
{
clk = NULL;
printk("Error not get clk %s\n",force_enable_clks[i]);
continue;
}
clk_prepare_enable(clk);
clk_put(clk);
clk=NULL;
}
/* register periph clock */
for(i=0; i<ARRAY_SIZE(sunxi_periphs_init); i++) {
periph = &sunxi_periphs_init[i];
if((unsigned int)periph->periph->gate.bus == (unsigned int)LOSC_OUT_GATE)
clk = sunxi_clk_register_periph(periph->name, periph->parent_names,
periph->num_parents,periph->flags, IO_ADDRESS(0x00000000), periph->periph);
else
clk = sunxi_clk_register_periph(periph->name, periph->parent_names,
periph->num_parents,periph->flags, sunxi_clk_base, periph->periph);
clk_register_clkdev(clk, periph->name, NULL);
}
for(i=0; i<ARRAY_SIZE(sunxi_periphs_cpus_init); i++) {
periph = &sunxi_periphs_cpus_init[i];
clk = sunxi_clk_register_periph(periph->name, periph->parent_names,
periph->num_parents,periph->flags, sunxi_clk_cpus_base , periph->periph);
clk_register_clkdev(clk, periph->name, NULL);
}
clk_add_alias("pll1",NULL,"pll_cpu0",NULL);
clk_add_alias("pll2",NULL,"pll_audio",NULL);
clk_add_alias("pll3",NULL,"pll_video",NULL);
clk_add_alias("pll4",NULL,"pll_ve",NULL);
clk_add_alias("pll5",NULL,"pll_ddr0",NULL);
clk_add_alias("pll6",NULL,"pll_periph0",NULL);
clk_add_alias("pll8",NULL,"pll_gpu",NULL);
clk_add_alias("pll9",NULL,"pll_hsic",NULL);
clk_add_alias("pll10",NULL,"pll_de",NULL);
clk_add_alias("pll6ahb1",NULL,"pll_periph0ahb1",NULL);
#ifdef CONFIG_COMMON_CLK_ENABLE_SYNCBOOT_EARLY
clk_syncboot();
#endif
}
int __init plat_clk_alias_init(void)
{
/* core clocks */
clk_add_alias("cpu_clk", NULL, "CLKA_ST40_ICK", NULL);
clk_add_alias("module_clk", NULL, "CLKA_IC_IF_100", NULL);
clk_add_alias("comms_clk", NULL, "CLKA_IC_IF_100", NULL);
/* EMI clock */
clk_add_alias("emi_clk", NULL, "CLKA_EMI_MASTER", NULL);
/* fdmas clocks */
clk_add_alias("fdma_slim_clk", "stm-fdma.0", "CLKA_FDMA0", NULL);
clk_add_alias("fdma_slim_clk", "stm-fdma.1", "CLKA_FDMA1", NULL);
clk_add_alias("fdma_hi_clk", NULL, "CLKA_IC_IF_100", NULL);
clk_add_alias("fdma_low_clk", NULL, "CLKA_IC_TS_200", NULL);
clk_add_alias("fdma_ic_clk", NULL, "CLKA_IC_IF_100", NULL);
/* USB clocks */
clk_add_alias("usb_phy_clk", NULL, "CLKE_REF", NULL);
clk_add_alias("usb_48_clk", NULL, "CLKB_FS1_CH4", NULL);
clk_add_alias("usb_ic_clk", NULL, "CLKA_IC_IF_100", NULL);
clk_add_alias("pcm_player_clk", "snd_pcm_player.0", "CLKC_FS0_CH1",
NULL);
clk_add_alias("pcm_player_clk", "snd_pcm_player.1", "CLKC_FS0_CH2",
NULL);
clk_add_alias("spdif_player_clk", NULL, "CLKC_FS0_CH3", NULL);
return 0;
}
void __init sunxi_init_clocks(void)
{
int i;
struct clk *clk;
struct factor_init_data *factor;
struct periph_init_data *periph;
#ifdef CONFIG_SUNXI_CLK_DUMMY_DEBUG
sunxi_clk_base = &dummy_reg[0];
dummy_reg_init();
#else
/* get clk register base address */
sunxi_clk_base = IO_ADDRESS(0x01c20000);
#endif
sunxi_clk_factor_initlimits();
/* register oscs */
clk = clk_register_fixed_rate(NULL, "losc", NULL, CLK_IS_ROOT, 32768);
clk_register_clkdev(clk, "losc", NULL);
clk = clk_register_fixed_rate(NULL, "hosc", NULL, CLK_IS_ROOT, 24000000);
clk_register_clkdev(clk, "hosc", NULL);
/* register normal factors, based on sunxi factor framework */
for(i=0; i<ARRAY_SIZE(sunxi_factos); i++) {
factor = &sunxi_factos[i];
clk = sunxi_clk_register_factors(NULL, sunxi_clk_base, &clk_lock,factor);
clk_register_clkdev(clk, factor->name, NULL);
}
/* register fixed factors, based on clk-fixed-factor framework, such as pllx2 for ex. */
clk = clk_register_fixed_factor(NULL, "pll_audiox8", "pll_audio", 0, 8, 1);
clk_register_clkdev(clk, "pll_audiox8", NULL);
clk = clk_register_fixed_factor(NULL, "pll_audiox4", "pll_audio", 0, 8, 2);
clk_register_clkdev(clk, "pll_audiox4", NULL);
clk = clk_register_fixed_factor(NULL, "pll_audiox2", "pll_audio", 0, 8, 4);
clk_register_clkdev(clk, "pll_audiox2", NULL);
clk = clk_register_fixed_factor(NULL, "pll_videox2", "pll_video", 0, 2, 1);
clk_register_clkdev(clk, "pll_videox2", NULL);
clk = clk_register_fixed_factor(NULL, "pll_periph0x2", "pll_periph0", 0, 2, 1);
clk_register_clkdev(clk, "pll_periph0x2", NULL);
clk = clk_register_fixed_factor(NULL, "pll_periph0d2", "pll_periph0", 0, 1, 2);
clk_register_clkdev(clk, "pll_periph0d2", NULL);
clk = clk_register_fixed_factor(NULL, "hoscd2", "hosc", 0, 1, 2);
clk_register_clkdev(clk, "hoscd2", NULL);
/* register periph clock */
for(i=0; i<ARRAY_SIZE(sunxi_periphs_init); i++) {
periph = &sunxi_periphs_init[i];
clk = sunxi_clk_register_periph(periph->name, periph->parent_names,
periph->num_parents,periph->flags, sunxi_clk_base, periph->periph);
clk_register_clkdev(clk, periph->name, NULL);
}
clk = clk_get(NULL,"ahb1");
if(!clk || IS_ERR(clk))
printk("Error not get clk ahb1\n");
else
{
struct clk *parent_clk = clk_get(NULL,"pll_periph0d2");
if(!parent_clk || IS_ERR(parent_clk))
{
printk("%d Error not get clk pll_periph0d2\n" , __LINE__);
}
else
{
printk("%d ahb1 set parent pll_periph0d2\n" , __LINE__);
clk_set_parent(clk,parent_clk);
clk_put(parent_clk);
}
clk_put(clk);
}
clk_add_alias("pll1",NULL,"pll_cpu",NULL);
clk_add_alias("pll2",NULL,"pll_audio",NULL);
clk_add_alias("pll3",NULL,"pll_video",NULL);
clk_add_alias("pll4",NULL,"pll_ve",NULL);
clk_add_alias("pll5",NULL,"pll_ddr0",NULL);
clk_add_alias("pll6",NULL,"pll_periph0",NULL);
clk_add_alias("pll6ahb0",NULL,"pll_periphahb0",NULL);
#ifdef CONFIG_COMMON_CLK_ENABLE_SYNCBOOT_EARLY
clk_syncboot();
#endif
}
static void __init hwa742_dev_init(void)
{
clk_add_alias("hwa_sys_ck", NULL, "bclk", NULL);
}
int __init plat_clk_alias_init(void)
{
/* core clocks */
clk_add_alias("cpu_clk", NULL, "CLKA_ST40_HOST", NULL);
clk_add_alias("module_clk", NULL, "CLKA_IC_100", NULL);
clk_add_alias("comms_clk", NULL, "CLKA_IC_100", NULL);
/* EMI clock */
clk_add_alias("emi_clk", NULL, "CLKA_EMI", NULL);
/* fdmas clocks */
clk_add_alias("fdma_slim_clk", NULL, "CLKA_FDMA", NULL);
clk_add_alias("fdma_hi_clk", NULL, "CLKA_IC_100", NULL);
clk_add_alias("fdma_low_clk", NULL, "CLKA_IC_200", NULL);
clk_add_alias("fdma_ic_clk", NULL, "CLKA_IC_100", NULL);
/* USB clocks */
/*
* usb_phy_clk, usb_48_clk provided in the Clockgen_south:
* not currently covered
* Reference: ADCD 'FLI7510_DS_C7510' p 199
*/
clk_add_alias("usb_ic_clk", NULL, "CLKA_IC_100", NULL);
/* LPC clock */
/*
* clk_lpc provided in the Clockgen_south
* It should be the rtc_clk @ 32,768 Khz
*/
/* Clock Gen C (Audio) */
clk_add_alias("clkc_256fs_free_run", NULL, "CLKC_FS_FREE_RUN", NULL);
clk_add_alias("clkc_256fs_dec_1", NULL, "CLKC_FS_DEC_1", NULL);
clk_add_alias("clkc_spdif_rx", NULL, "CLKC_SPDIF", NULL);
clk_add_alias("clkc_256fs_dec_2", NULL, "CLKC_FS_DEC_2", NULL);
return 0;
}
void __init exynos5_universal5410_media_init(void)
{
#if defined (CONFIG_CSI_D) || defined (CONFIG_S5K6B2_CSI_D)
s3c_i2c1_set_platdata(NULL);
#endif
#if defined (CONFIG_CSI_E) || defined (CONFIG_S5K6B2_CSI_E)
s3c_i2c1_set_platdata(NULL);
#endif
#ifdef CONFIG_VIDEO_EXYNOS_MFC
s5p_mfc_set_platdata(&universal5410_mfc_pd);
dev_set_name(&s5p_device_mfc.dev, "s3c-mfc");
clk_add_alias("mfc", "s5p-mfc-v6", "mfc", &s5p_device_mfc.dev);
s5p_mfc_setname(&s5p_device_mfc, "s5p-mfc-v6");
#endif
platform_add_devices(universal5410_media_devices,
ARRAY_SIZE(universal5410_media_devices));
s3c_set_platdata(&exynos5410_scaler_pd, sizeof(exynos5410_scaler_pd),
&exynos5_device_scaler0);
#ifdef CONFIG_VIDEO_S5K6B2
#if defined(CONFIG_S5K6B2_CSI_C)
__set_mipi_csi_config(&s5p_mipi_csis0_default_data, s5k6b2.csi_data_align);
#elif defined(CONFIG_S5K6B2_CSI_D)
__set_mipi_csi_config(&s5p_mipi_csis1_default_data, s5k6b2.csi_data_align);
#elif defined(CONFIG_S5K6B2_CSI_E)
__set_mipi_csi_config(&s5p_mipi_csis2_default_data, s5k6b2.csi_data_align);
#endif
#endif
#ifdef CONFIG_VIDEO_EXYNOS_MIPI_CSIS
s3c_set_platdata(&s5p_mipi_csis0_default_data,
sizeof(s5p_mipi_csis0_default_data), &s5p_device_mipi_csis0);
s3c_set_platdata(&s5p_mipi_csis1_default_data,
sizeof(s5p_mipi_csis1_default_data), &s5p_device_mipi_csis1);
s3c_set_platdata(&s5p_mipi_csis2_default_data,
sizeof(s5p_mipi_csis2_default_data), &s5p_device_mipi_csis2);
#endif
#ifdef CONFIG_VIDEO_EXYNOS_FIMC_LITE
universal5410_camera_gpio_cfg();
universal5410_set_camera_platdata();
s3c_set_platdata(&exynos_flite0_default_data,
sizeof(exynos_flite0_default_data), &exynos_device_flite0);
s3c_set_platdata(&exynos_flite1_default_data,
sizeof(exynos_flite1_default_data), &exynos_device_flite1);
s3c_set_platdata(&exynos_flite2_default_data,
sizeof(exynos_flite2_default_data), &exynos_device_flite2);
#endif
#if defined(CONFIG_VIDEO_EXYNOS_TV)
dev_set_name(&s5p_device_hdmi.dev, "exynos5-hdmi");
mxr_platdata.ip_ver = IP_VER_TV_5A_1;
hdmi_platdata.ip_ver = IP_VER_TV_5A_1;
s5p_tv_setup();
/* Below should be enabled after power domain is available */
#if 0
s5p_device_hdmi.dev.parent = &exynos5_device_pd[PD_DISP1].dev;
s5p_device_mixer.dev.parent = &exynos5_device_pd[PD_DISP1].dev;
#endif
#ifdef CONFIG_VIDEO_EXYNOS_HDMI_CEC
s5p_hdmi_cec_set_platdata(&hdmi_cec_data);
#endif
s3c_set_platdata(&mxr_platdata, sizeof(mxr_platdata), &s5p_device_mixer);
s5p_hdmi_set_platdata(&hdmi_platdata);
/*
* exynos5_hs_i2c2_set_platdata(NULL);
* i2c_register_board_info(6, hs_i2c_devs2, ARRAY_SIZE(hs_i2c_devs2));
*/
#endif
#ifdef CONFIG_VIDEO_EXYNOS_GSCALER
exynos5_gsc_set_ip_ver(IP_VER_GSC_5A);
exynos5_gsc_set_pm_qos_val(160000, 160000);
s3c_set_platdata(&exynos_gsc0_default_data, sizeof(exynos_gsc0_default_data),
&exynos5_device_gsc0);
s3c_set_platdata(&exynos_gsc1_default_data, sizeof(exynos_gsc1_default_data),
&exynos5_device_gsc1);
s3c_set_platdata(&exynos_gsc2_default_data, sizeof(exynos_gsc2_default_data),
&exynos5_device_gsc2);
s3c_set_platdata(&exynos_gsc3_default_data, sizeof(exynos_gsc3_default_data),
&exynos5_device_gsc3);
#endif
#ifdef CONFIG_VIDEO_EXYNOS5_FIMC_IS
dev_set_name(&exynos5_device_fimc_is.dev, "s5p-mipi-csis.0");
clk_add_alias("gscl_wrap0", FIMC_IS_MODULE_NAME, "gscl_wrap0", &exynos5_device_fimc_is.dev);
dev_set_name(&exynos5_device_fimc_is.dev, "s5p-mipi-csis.1");
clk_add_alias("gscl_wrap1", FIMC_IS_MODULE_NAME, "gscl_wrap1", &exynos5_device_fimc_is.dev);
dev_set_name(&exynos5_device_fimc_is.dev, "s5p-mipi-csis.2");
clk_add_alias("gscl_wrap2", FIMC_IS_MODULE_NAME, "gscl_wrap2", &exynos5_device_fimc_is.dev);
dev_set_name(&exynos5_device_fimc_is.dev, FIMC_IS_MODULE_NAME);
exynos5_fimc_is_data.gpio_info = &gpio_universal5410;
exynos5_fimc_is_set_platdata(&exynos5_fimc_is_data);
if (!exynos_spi_cfg_cs(spi3_csi[0].line, 3)) {
s3c64xx_spi3_set_platdata(&s3c64xx_spi3_pdata,
EXYNOS_SPI_SRCCLK_SCLK, ARRAY_SIZE(spi3_csi));
spi_register_board_info(spi3_board_info,
ARRAY_SIZE(spi3_board_info));
} else {
pr_err("%s: Error requesting gpio for SPI-CH1 CS\n", __func__);
}
#endif
#ifdef CONFIG_VIDEO_EXYNOS_FIMG2D
s5p_fimg2d_set_platdata(&fimg2d_data);
#endif
#ifdef CONFIG_VIDEO_EXYNOS_JPEG
s3c_set_platdata(&exynos5_jpeg_pd, sizeof(exynos5_jpeg_pd),
&s5p_device_jpeg);
#endif
#ifdef CONFIG_VIDEO_EXYNOS_JPEG_HX
s3c_set_platdata(&exynos5_jpeg_hx_pd, sizeof(exynos5_jpeg_hx_pd),
&exynos5_device_jpeg_hx);
#endif
}
int __init plat_clk_alias_init(void)
{
/* core clocks */
clk_add_alias("cpu_clk", NULL, "st40_clk", NULL);
clk_add_alias("module_clk", NULL,
(cpu_data->cut_major < 2) ? "st40_per_clk" : "ic_reg",
NULL);
clk_add_alias("comms_clk", NULL, "ic_reg", NULL);
/* EMI clock */
clk_add_alias("emi_clk", NULL, "emi_master", NULL);
/* fdmas clocks */
clk_add_alias("fdma_slim_clk", "stm-fdma.0", "fdma_clk0", NULL);
clk_add_alias("fdma_slim_clk", "stm-fdma.1", "fdma_clk1", NULL);
clk_add_alias("fdma_hi_clk", NULL, "ic_reg", NULL);
clk_add_alias("fdma_low_clk", NULL, "fdma_200", NULL);
clk_add_alias("fdma_ic_clk", NULL, "ic_reg", NULL);
/* USB clocks */
clk_add_alias("usb_ic_clk", NULL, "ic_reg", NULL);
/* usb_phy_clk and usb_48_clk managed internally in the wrapper */
/* ALSA clocks */
clk_add_alias("pcm_player_clk", "snd_pcm_player.0", "CLKC_FS0_CH1",
NULL);
clk_add_alias("pcm_player_clk", "snd_pcm_player.1", "CLKC_FS0_CH2",
NULL);
clk_add_alias("pcm_player_clk", "snd_pcm_player.2", "CLKC_FS0_CH3",
NULL);
clk_add_alias("pcm_player_clk", "snd_pcm_player.3", "CLKC_FS0_CH4",
NULL);
clk_add_alias("pcm_player_clk", "snd_pcm_player.4", "CLKC_FS1_CH3",
NULL);
clk_add_alias("spdif_player_clk", "snd_spdif_player.0", "CLKC_FS1_CH4",
NULL);
clk_add_alias("spdif_player_clk", "snd_spdif_player.1", "CLKC_FS1_CH3",
NULL);
return 0;
}
