C++ (Cpp) clk_get_rate_all_locked Examples

Example #1

File: tegra3_dvfs.c Project: motley-git/TF201-Kernel-Lite

static bool __init is_pllm_dvfs(struct clk *c, struct dvfs *d)
{
#ifdef CONFIG_TEGRA_PLLM_RESTRICTED
	/* Restricting PLLM usage on T30 and T33, rev A02+, allows to apply
	   maximum PLLM frequency to clock tree at minimum core voltage;
	   no need to enable dvfs on PLLM in this case */
	if ((tegra_cpu_speedo_id() == 2) || (tegra_cpu_speedo_id() == 5))
	   return false;
#endif
	/* Check if PLLM boot frequency can be applied to clock tree at
	   minimum voltage. If yes, no need to enable dvfs on PLLM */
	if (clk_get_rate_all_locked(c) <= d->freqs[0] * d->freqs_mult)
		return false;

	return true;
}

Example #2

File: tegra3_dvfs.c Project: Error-Unknown/bricked-endeavoru

static bool __init is_pllm_dvfs(struct clk *c, struct dvfs *d)
{
#ifdef CONFIG_TEGRA_PLLM_RESTRICTED
	/* Do not apply common PLLM dvfs table on T30 and T33, rev A02+ and
	   do not apply restricted PLLM dvfs table for other SKUs/revs */
	if (((tegra_cpu_speedo_id() == 2) || (tegra_cpu_speedo_id() == 5)) ==
	    (d->speedo_id == -1))
		return false;
#endif
	/* Check if PLLM boot frequency can be applied to clock tree at
	   minimum voltage. If yes, no need to enable dvfs on PLLM */
	if (clk_get_rate_all_locked(c) <= d->freqs[0] * d->freqs_mult)
		return false;

	return true;
}