static int lcdc_on(struct platform_device *pdev)
{
int ret = 0;
struct msm_fb_data_type *mfd;
unsigned long panel_pixclock_freq = 0;
#ifndef CONFIG_MSM_BUS_SCALING
unsigned long pm_qos_rate;
#endif
mfd = platform_get_drvdata(pdev);
if (lcdc_pdata && lcdc_pdata->lcdc_get_clk)
panel_pixclock_freq = lcdc_pdata->lcdc_get_clk();
if (!panel_pixclock_freq)
panel_pixclock_freq = mfd->fbi->var.pixclock;
#ifdef CONFIG_MSM_BUS_SCALING
mdp_bus_scale_update_request(2);
#else
#ifdef CONFIG_MSM_NPA_SYSTEM_BUS
pm_qos_rate = MSM_AXI_FLOW_MDP_LCDC_WVGA_2BPP;
#else
if (panel_pixclock_freq > 65000000)
/* pm_qos_rate should be in Khz */
pm_qos_rate = panel_pixclock_freq / 1000 ;
else
pm_qos_rate = 65000;
#endif
if (mfd->ebi1_clk) {
clk_set_rate(mfd->ebi1_clk, pm_qos_rate * 1000);
clk_enable(mfd->ebi1_clk);
}
#endif
mfd = platform_get_drvdata(pdev);
mfd->fbi->var.pixclock = clk_round_rate(pixel_mdp_clk,
mfd->fbi->var.pixclock);
if(firsttime)
{
firsttime=false;
}
else
ret = clk_set_rate(pixel_mdp_clk, mfd->fbi->var.pixclock);
if (ret) {
pr_err("%s: Can't set MDP LCDC pixel clock to rate %u\n",
__func__, mfd->fbi->var.pixclock);
goto out;
}
clk_enable(pixel_mdp_clk);
clk_enable(pixel_lcdc_clk);
if (lcdc_pdata && lcdc_pdata->lcdc_power_save)
lcdc_pdata->lcdc_power_save(1);
if (lcdc_pdata && lcdc_pdata->lcdc_gpio_config)
ret = lcdc_pdata->lcdc_gpio_config(1);
ret = panel_next_on(pdev);
out:
return ret;
}
mali_bool mali_clk_set_rate(unsigned int clk, unsigned int mhz)
{
unsigned long rate = 0;
mali_bool bis_vpll = MALI_TRUE;
#ifndef CONFIG_VPLL_USE_FOR_TVENC
bis_vpll = MALI_TRUE;
#endif
#if !MALI_DVFS_ENABLED
clk = mali_gpu_clk;
#endif
_mali_osk_lock_wait(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW);
if (mali_clk_get(bis_vpll) == MALI_FALSE)
return MALI_FALSE;
rate = (unsigned long)clk * (unsigned long)mhz;
MALI_DEBUG_PRINT(3,("= clk_set_rate : %d , %d \n",clk, mhz ));
if (bis_vpll)
{
clk_set_rate(fout_vpll_clock, (unsigned int)clk * GPU_MHZ);
clk_set_parent(vpll_src_clock, ext_xtal_clock);
clk_set_parent(sclk_vpll_clock, fout_vpll_clock);
clk_set_parent(mali_parent_clock, sclk_vpll_clock);
clk_set_parent(mali_clock, mali_parent_clock);
}
else
{
clk_set_parent(mali_parent_clock, mpll_clock);
clk_set_parent(mali_clock, mali_parent_clock);
}
if (clk_enable(mali_clock) < 0)
return MALI_FALSE;
#if MALI_TIMELINE_PROFILING_ENABLED
_mali_profiling_add_event( MALI_PROFILING_EVENT_TYPE_SINGLE |
MALI_PROFILING_EVENT_CHANNEL_SOFTWARE |
MALI_PROFILING_EVENT_REASON_SINGLE_SW_GPU_FREQ,
rate, 0, 0, 0, 0);
#endif
clk_set_rate(mali_clock, rate);
rate = clk_get_rate(mali_clock);
#if MALI_TIMELINE_PROFILING_ENABLED
_mali_profiling_add_event( MALI_PROFILING_EVENT_TYPE_SINGLE |
MALI_PROFILING_EVENT_CHANNEL_SOFTWARE |
MALI_PROFILING_EVENT_REASON_SINGLE_SW_GPU_FREQ,
rate, 1, 0, 0, 0);
#endif
if (bis_vpll)
mali_gpu_clk = (int)(rate / mhz);
else
mali_gpu_clk = (int)((rate + 500000) / mhz);
GPU_MHZ = mhz;
MALI_DEBUG_PRINT(3,("= clk_get_rate: %d \n",mali_gpu_clk));
mali_clk_put(MALI_FALSE);
_mali_osk_lock_signal(mali_dvfs_lock, _MALI_OSK_LOCKMODE_RW);
return MALI_TRUE;
}
/*****************************************************************************
function name : mali_clock_on
description : clock on mali by calling clk
input vars : void
output vars : NA
return value : void
calls : clk_enable
called : mali_platform_powerup
history :
1.data : 04/03/2014
author : s00250033
modify : new
*****************************************************************************/
_mali_osk_errcode_t mali_clock_on(void)
{
int err;
int core_freq = 0;
int pclk_freq = 0;
#if 0
if( IS_ERR_OR_NULL(gpu_pll) )
{
MALI_DEBUG_PRINT(1, ("****error on mali_clock_on : gpu_pll is null\n"));
return _MALI_OSK_ERR_FAULT;
}
err = clk_prepare_enable(gpu_pll);
if (0 != err)
{
MALI_DEBUG_PRINT(1, ("****error on mali_clock_on : gpu_pll enable error!\n"));
return _MALI_OSK_ERR_FAULT;
}
if( IS_ERR_OR_NULL(media_pll) )
{
MALI_DEBUG_PRINT(1, ("****error on mali_clock_on : media_pll is null\n"));
return _MALI_OSK_ERR_FAULT;
}
err = clk_prepare_enable(media_pll);
if (0 != err)
{
MALI_DEBUG_PRINT(1, ("****error on mali_clock_on : media_pll enable error!\n"));
return _MALI_OSK_ERR_FAULT;
}
#endif
if( IS_ERR_OR_NULL(media_clk_g3d))
{
MALI_DEBUG_PRINT(1, ("****error on mali_clock_on : media_clk_g3d is null\n"));
return _MALI_OSK_ERR_FAULT;
}
err = clk_prepare_enable(media_clk_g3d);
if (0 != err)
{
MALI_DEBUG_PRINT(1, ("****error on mali_clock_on : media_clk_g3d enable error!\n"));
return _MALI_OSK_ERR_FAULT;
}
err = of_property_read_u32(np, "pclk_freq",&pclk_freq);
if (err) {
MALI_DEBUG_PRINT(1, ("ERROR: get mali pclk freq failed!\n"));
return _MALI_OSK_ERR_FAULT;
}
if(0 != clk_set_rate(media_clk_g3d, (pclk_freq) * GPU_MHZ))
{
MALI_DEBUG_PRINT(1, ("ERROR: fail to set media_clk_g3d!\n"));
}
if( IS_ERR_OR_NULL(mali_clock))
{
MALI_DEBUG_PRINT(1, ("****error on mali_clock_on : mali_clock is null\n"));
return _MALI_OSK_ERR_FAULT;
}
err = of_property_read_u32(np, "mali_def_freq",&core_freq);
if (err) {
MALI_DEBUG_PRINT(1, ("ERROR: get mali default freq failed!\n"));
return _MALI_OSK_ERR_FAULT;
}
if(0 != clk_set_rate(mali_clock, core_freq * GPU_MHZ))
{
MALI_DEBUG_PRINT(1, ("ERROR: fail to set mali_clock!\n"));
}
err = clk_prepare_enable(mali_clock);
if (0 != err)
{
MALI_DEBUG_PRINT(1, ("****error on mali_clock_on : mali_clock enable error!\n"));
return _MALI_OSK_ERR_FAULT;
}
//phy_reg_writel(SOC_PERI_SCTRL_BASE_ADDR,SOC_PERI_SCTRL_SC_CLKCFG8BIT0_ADDR(0),0,31,0x01020183);
MALI_DEBUG_PRINT(3, ("mali_clock_on finish\n"));
return _MALI_OSK_ERR_OK;
}
static void __init bockw_init(void)
{
void __iomem *base;
struct clk *clk;
int i;
r8a7778_clock_init();
r8a7778_init_irq_extpin(1);
r8a7778_add_standard_devices();
platform_device_register_full(ðer_info);
platform_device_register_full(&vin0_info);
/* VIN1 has a pin conflict with Ether */
if (!IS_ENABLED(CONFIG_SH_ETH))
platform_device_register_full(&vin1_info);
platform_device_register_data(&platform_bus, "soc-camera-pdrv", 0,
&iclink0_ml86v7667,
sizeof(iclink0_ml86v7667));
platform_device_register_data(&platform_bus, "soc-camera-pdrv", 1,
&iclink1_ml86v7667,
sizeof(iclink1_ml86v7667));
i2c_register_board_info(0, i2c0_devices,
ARRAY_SIZE(i2c0_devices));
spi_register_board_info(spi_board_info,
ARRAY_SIZE(spi_board_info));
pinctrl_register_mappings(bockw_pinctrl_map,
ARRAY_SIZE(bockw_pinctrl_map));
r8a7778_pinmux_init();
platform_device_register_resndata(
&platform_bus, "sh_mmcif", -1,
mmc_resources, ARRAY_SIZE(mmc_resources),
&sh_mmcif_plat, sizeof(struct sh_mmcif_plat_data));
platform_device_register_resndata(
&platform_bus, "rcar_usb_phy", -1,
usb_phy_resources,
ARRAY_SIZE(usb_phy_resources),
&usb_phy_platform_data,
sizeof(struct rcar_phy_platform_data));
regulator_register_fixed(0, dummy_supplies,
ARRAY_SIZE(dummy_supplies));
regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers,
ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
/* for SMSC */
fpga = ioremap_nocache(FPGA, SZ_1M);
if (fpga) {
/*
* CAUTION
*
* IRQ0/1 is cascaded interrupt from FPGA.
* it should be cared in the future
* Now, it is assuming IRQ0 was used only from SMSC.
*/
u16 val = ioread16(fpga + IRQ0MR);
val &= ~(1 << 4); /* enable SMSC911x */
iowrite16(val, fpga + IRQ0MR);
platform_device_register_resndata(
&platform_bus, "smsc911x", -1,
smsc911x_resources, ARRAY_SIZE(smsc911x_resources),
&smsc911x_data, sizeof(smsc911x_data));
}
/* for SDHI */
base = ioremap_nocache(PFC, 0x200);
if (base) {
/*
* FIXME
*
* SDHI CD/WP pin needs pull-up
*/
iowrite32(ioread32(base + PUPR4) | (3 << 26), base + PUPR4);
iounmap(base);
platform_device_register_resndata(
&platform_bus, "sh_mobile_sdhi", 0,
sdhi0_resources, ARRAY_SIZE(sdhi0_resources),
&sdhi0_info, sizeof(struct sh_mobile_sdhi_info));
}
/* for Audio */
clk = clk_get(NULL, "audio_clk_b");
clk_set_rate(clk, 24576000);
clk_put(clk);
rsnd_codec_power(5, 1); /* enable ak4642 */
platform_device_register_simple(
"ak4554-adc-dac", 0, NULL, 0);
platform_device_register_simple(
"ak4554-adc-dac", 1, NULL, 0);
platform_device_register_resndata(
&platform_bus, "rcar_sound", -1,
rsnd_resources, ARRAY_SIZE(rsnd_resources),
&rsnd_info, sizeof(rsnd_info));
for (i = 0; i < ARRAY_SIZE(rsnd_card_info); i++) {
struct platform_device_info cardinfo = {
.parent = &platform_bus,
.name = "asoc-simple-card",
.id = i,
.data = &rsnd_card_info[i],
.size_data = sizeof(struct asoc_simple_card_info),
.dma_mask = DMA_BIT_MASK(32),
};
platform_device_register_full(&cardinfo);
}
}
static void __init bockw_init_late(void)
{
r8a7778_init_late();
ADD_USB_FUNC_DEVICE_IF_POSSIBLE();
}
static int sdhci_msm_probe(struct platform_device *pdev)
{
struct sdhci_host *host;
struct sdhci_pltfm_host *pltfm_host;
struct sdhci_msm_host *msm_host;
struct resource *core_memres;
int ret;
u16 host_version, core_minor;
u32 core_version, caps;
u8 core_major;
host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
if (IS_ERR(host))
return PTR_ERR(host);
pltfm_host = sdhci_priv(host);
msm_host = sdhci_pltfm_priv(pltfm_host);
msm_host->mmc = host->mmc;
msm_host->pdev = pdev;
ret = mmc_of_parse(host->mmc);
if (ret)
goto pltfm_free;
sdhci_get_of_property(pdev);
/* Setup SDCC bus voter clock. */
msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
if (!IS_ERR(msm_host->bus_clk)) {
/* Vote for max. clk rate for max. performance */
ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
if (ret)
goto pltfm_free;
ret = clk_prepare_enable(msm_host->bus_clk);
if (ret)
goto pltfm_free;
}
/* Setup main peripheral bus clock */
msm_host->pclk = devm_clk_get(&pdev->dev, "iface");
if (IS_ERR(msm_host->pclk)) {
ret = PTR_ERR(msm_host->pclk);
dev_err(&pdev->dev, "Perpheral clk setup failed (%d)\n", ret);
goto bus_clk_disable;
}
ret = clk_prepare_enable(msm_host->pclk);
if (ret)
goto bus_clk_disable;
/* Setup SDC MMC clock */
msm_host->clk = devm_clk_get(&pdev->dev, "core");
if (IS_ERR(msm_host->clk)) {
ret = PTR_ERR(msm_host->clk);
dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
goto pclk_disable;
}
/* Vote for maximum clock rate for maximum performance */
ret = clk_set_rate(msm_host->clk, INT_MAX);
if (ret)
dev_warn(&pdev->dev, "core clock boost failed\n");
ret = clk_prepare_enable(msm_host->clk);
if (ret)
goto pclk_disable;
core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
msm_host->core_mem = devm_ioremap_resource(&pdev->dev, core_memres);
if (IS_ERR(msm_host->core_mem)) {
dev_err(&pdev->dev, "Failed to remap registers\n");
ret = PTR_ERR(msm_host->core_mem);
goto clk_disable;
}
/* Reset the core and Enable SDHC mode */
writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_POWER) |
CORE_SW_RST, msm_host->core_mem + CORE_POWER);
/* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */
usleep_range(1000, 5000);
if (readl(msm_host->core_mem + CORE_POWER) & CORE_SW_RST) {
dev_err(&pdev->dev, "Stuck in reset\n");
ret = -ETIMEDOUT;
goto clk_disable;
}
/* Set HC_MODE_EN bit in HC_MODE register */
writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));
host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
SDHCI_VENDOR_VER_SHIFT));
core_version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION);
core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
CORE_VERSION_MAJOR_SHIFT;
core_minor = core_version & CORE_VERSION_MINOR_MASK;
dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
core_version, core_major, core_minor);
/*
* Support for some capabilities is not advertised by newer
* controller versions and must be explicitly enabled.
*/
if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
caps = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
writel_relaxed(caps, host->ioaddr +
CORE_VENDOR_SPEC_CAPABILITIES0);
}
ret = sdhci_add_host(host);
if (ret)
goto clk_disable;
return 0;
clk_disable:
clk_disable_unprepare(msm_host->clk);
pclk_disable:
clk_disable_unprepare(msm_host->pclk);
bus_clk_disable:
if (!IS_ERR(msm_host->bus_clk))
clk_disable_unprepare(msm_host->bus_clk);
pltfm_free:
sdhci_pltfm_free(pdev);
return ret;
}
static void __init cardhu_uart_init(void)
{
struct clk *c;
int i;
struct board_info board_info;
tegra_get_board_info(&board_info);
for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
c = tegra_get_clock_by_name(uart_parent_clk[i].name);
if (IS_ERR_OR_NULL(c)) {
pr_err("Not able to get the clock for %s\n",
uart_parent_clk[i].name);
continue;
}
uart_parent_clk[i].parent_clk = c;
uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
}
cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
cardhu_loopback_uart_pdata.parent_clk_count =
ARRAY_SIZE(uart_parent_clk);
cardhu_loopback_uart_pdata.is_loopback = true;
tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
/* UARTE is used for loopback test purpose */
tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
/* Register low speed only if it is selected */
if (!is_tegra_debug_uartport_hs()) {
uart_debug_init();
/* Clock enable for the debug channel */
if (!IS_ERR_OR_NULL(debug_uart_clk)) {
pr_info("The debug console clock name is %s\n",
debug_uart_clk->name);
c = tegra_get_clock_by_name("pll_p");
if (IS_ERR_OR_NULL(c))
pr_err("Not getting the parent clock pll_p\n");
else
clk_set_parent(debug_uart_clk, c);
clk_enable(debug_uart_clk);
clk_set_rate(debug_uart_clk, clk_get_rate(c));
} else {
pr_err("Not getting the clock %s for debug console\n",
debug_uart_clk->name);
}
}
#ifdef CONFIG_TEGRA_IRDA
if (((board_info.board_id == BOARD_E1186) ||
(board_info.board_id == BOARD_E1198)) &&
cardhu_irda_pdata.is_irda) {
cardhu_irda_pdata.parent_clk_list = uart_parent_clk;
cardhu_irda_pdata.parent_clk_count =
ARRAY_SIZE(uart_parent_clk);
tegra_uartb_device.dev.platform_data = &cardhu_irda_pdata;
}
#endif
platform_add_devices(cardhu_uart_devices,
ARRAY_SIZE(cardhu_uart_devices));
}
static int wand_set_spdif_clk_rate(struct clk *clk, unsigned long rate) {
unsigned long rate_actual;
rate_actual = clk_round_rate(clk, rate);
clk_set_rate(clk, rate_actual);
return 0;
}
void msm_camio_clk_rate_set(int rate)
{
struct clk *clk = camio_cam_clk;
clk_set_rate(clk, rate);
}
int mdss_edp_clk_enable(struct mdss_edp_drv_pdata *edp_drv)
{
int ret;
if (edp_drv->clk_on) {
pr_info("%s: edp clks are already ON\n", __func__);
return 0;
}
if (clk_set_rate(edp_drv->link_clk, edp_drv->link_rate * 27000000) < 0)
pr_err("%s: link_clk - clk_set_rate failed\n",
__func__);
if (clk_set_rate(edp_drv->aux_clk, edp_drv->aux_rate) < 0)
pr_err("%s: aux_clk - clk_set_rate failed\n",
__func__);
if (clk_set_rate(edp_drv->pixel_clk, edp_drv->pixel_rate) < 0)
pr_err("%s: pixel_clk - clk_set_rate failed\n",
__func__);
ret = clk_enable(edp_drv->aux_clk);
if (ret) {
pr_err("%s: Failed to enable aux clk\n", __func__);
goto c4;
}
ret = clk_enable(edp_drv->pixel_clk);
if (ret) {
pr_err("%s: Failed to enable pixel clk\n", __func__);
goto c3;
}
ret = clk_enable(edp_drv->ahb_clk);
if (ret) {
pr_err("%s: Failed to enable ahb clk\n", __func__);
goto c2;
}
ret = clk_enable(edp_drv->link_clk);
if (ret) {
pr_err("%s: Failed to enable link clk\n", __func__);
goto c1;
}
ret = clk_enable(edp_drv->mdp_core_clk);
if (ret) {
pr_err("%s: Failed to enable mdp_core_clk\n", __func__);
goto c0;
}
edp_drv->clk_on = 1;
return 0;
c0:
clk_disable(edp_drv->link_clk);
c1:
clk_disable(edp_drv->ahb_clk);
c2:
clk_disable(edp_drv->pixel_clk);
c3:
clk_disable(edp_drv->aux_clk);
c4:
return ret;
}
static int msm_dai_q6_auxpcm_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct msm_dai_q6_dai_data *dai_data = dev_get_drvdata(dai->dev);
int rc = 0;
struct msm_dai_auxpcm_pdata *auxpcm_pdata =
(struct msm_dai_auxpcm_pdata *) dai->dev->platform_data;
mutex_lock(&aux_pcm_mutex);
if (aux_pcm_count == 2) {
dev_dbg(dai->dev, "%s(): dai->id %d aux_pcm_count is 2. Just"
" return.\n", __func__, dai->id);
mutex_unlock(&aux_pcm_mutex);
return 0;
} else if (aux_pcm_count > 2) {
dev_err(dai->dev, "%s(): ERROR: dai->id %d"
" aux_pcm_count = %d > 2\n",
__func__, dai->id, aux_pcm_count);
mutex_unlock(&aux_pcm_mutex);
return 0;
}
aux_pcm_count++;
if (aux_pcm_count == 2) {
dev_dbg(dai->dev, "%s(): dai->id %d aux_pcm_count = %d after "
" increment\n", __func__, dai->id, aux_pcm_count);
mutex_unlock(&aux_pcm_mutex);
return 0;
}
pr_debug("%s:dai->id:%d aux_pcm_count = %d. opening afe\n",
__func__, dai->id, aux_pcm_count);
rc = afe_q6_interface_prepare();
if (IS_ERR_VALUE(rc))
dev_err(dai->dev, "fail to open AFE APR\n");
/*
* For AUX PCM Interface the below sequence of clk
* settings and afe_open is a strict requirement.
*
* Also using afe_open instead of afe_port_start_nowait
* to make sure the port is open before deasserting the
* clock line. This is required because pcm register is
* not written before clock deassert. Hence the hw does
* not get updated with new setting if the below clock
* assert/deasset and afe_open sequence is not followed.
*/
clk_reset(pcm_clk, CLK_RESET_ASSERT);
afe_open(PCM_RX, &dai_data->port_config, dai_data->rate);
afe_open(PCM_TX, &dai_data->port_config, dai_data->rate);
rc = clk_set_rate(pcm_clk, auxpcm_pdata->pcm_clk_rate);
if (rc < 0) {
pr_err("%s: clk_set_rate failed\n", __func__);
return rc;
}
clk_enable(pcm_clk);
clk_reset(pcm_clk, CLK_RESET_DEASSERT);
mutex_unlock(&aux_pcm_mutex);
return rc;
}
void msm_camio_clk_rate_set_2(struct clk *clk, int rate)
{
clk_set_rate(clk, rate);
}
static int tegra30_spdif_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct device *dev = substream->pcm->card->dev;
struct tegra30_spdif *spdif = snd_soc_dai_get_drvdata(dai);
int ret, srate, spdifclock;
if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK) {
dev_err(dev, "spdif capture is not supported\n");
return -EINVAL;
}
spdif->reg_ctrl &= ~TEGRA30_SPDIF_CTRL_BIT_MODE_MASK;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
spdif->reg_ctrl |= TEGRA30_SPDIF_CTRL_PACK_ENABLE;
spdif->reg_ctrl |= TEGRA30_SPDIF_CTRL_BIT_MODE_16BIT;
break;
default:
return -EINVAL;
}
srate = params_rate(params);
spdif->reg_ch_sta_a &= ~TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_MASK;
spdif->reg_ch_sta_b &= ~TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_MASK;
switch (srate) {
case 32000:
spdifclock = 4096000;
spdif->reg_ch_sta_a |=
TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_32000;
spdif->reg_ch_sta_b |=
TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_32000;
break;
case 44100:
spdifclock = 5644800;
spdif->reg_ch_sta_a |=
TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_44100;
spdif->reg_ch_sta_b |=
TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_44100;
break;
case 48000:
spdifclock = 6144000;
spdif->reg_ch_sta_a |=
TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_48000;
spdif->reg_ch_sta_b |=
TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_48000;
break;
case 88200:
spdifclock = 11289600;
spdif->reg_ch_sta_a |=
TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_88200;
spdif->reg_ch_sta_b |=
TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_88200;
break;
case 96000:
spdifclock = 12288000;
spdif->reg_ch_sta_a |=
TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_96000;
spdif->reg_ch_sta_b |=
TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_96000;
break;
case 176400:
spdifclock = 22579200;
spdif->reg_ch_sta_a |=
TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_176400;
spdif->reg_ch_sta_b |=
TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_176400;
break;
case 192000:
spdifclock = 24576000;
spdif->reg_ch_sta_a |=
TEGRA30_SPDIF_CH_STA_TX_A_SAMP_FREQ_192000;
spdif->reg_ch_sta_b |=
TEGRA30_SPDIF_CH_STA_TX_B_ORIG_SAMP_FREQ_192000;
break;
default:
return -EINVAL;
}
ret = clk_set_rate(spdif->clk_spdif_out, spdifclock);
if (ret) {
dev_err(dev, "Can't set SPDIF clock rate: %d\n", ret);
return ret;
}
tegra30_spdif_enable_clocks(spdif);
tegra30_spdif_write(spdif, TEGRA30_SPDIF_CH_STA_TX_A,
spdif->reg_ch_sta_a);
tegra30_spdif_write(spdif, TEGRA30_SPDIF_CH_STA_TX_B,
spdif->reg_ch_sta_b);
tegra30_spdif_disable_clocks(spdif);
ret = tegra_hdmi_setup_audio_freq_source(srate, SPDIF);
if (ret) {
dev_err(dev, "Can't set HDMI audio freq source: %d\n", ret);
return ret;
}
return 0;
}
int s3cfb_clk_on(struct platform_device *pdev, struct clk **s3cfb_clk)
{
struct clk *sclk = NULL;
struct clk *mout_fimd = NULL, *mout_mpll = NULL;
u32 rate = 0;
int ret;
sclk = clk_get(&pdev->dev, "sclk_fimd");
if (IS_ERR(sclk)) {
dev_err(&pdev->dev, "failed to get sclk for fimd\n");
goto err_clk1;
}
#if defined(CONFIG_S5PV210_SCLKFIMD_USE_VPLL)
mout_mpll = clk_get(&pdev->dev, "mout_vpll");
#else
mout_mpll = clk_get(&pdev->dev, "mout_mpll");
#endif
if (IS_ERR(mout_mpll)) {
dev_err(&pdev->dev, "failed to get mout_mpll\n");
goto err_clk1;
}
mout_fimd = clk_get(&pdev->dev, "mout_fimd");
if (IS_ERR(mout_fimd)) {
dev_err(&pdev->dev,
"failed to get mout_fimd\n");
goto err_clk2;
}
clk_set_parent(sclk, mout_fimd);
clk_set_parent(mout_fimd, mout_mpll);
rate = clk_round_rate(sclk, 166750000);
dev_dbg(&pdev->dev, "set fimd sclk rate to %d\n", rate);
if (!rate)
rate = 166750000;
#if defined(CONFIG_MACH_S5PC110_P1)
#if defined(CONFIG_TARGET_PCLK_44_46)
rate = 45000000;
#elif defined(CONFIG_TARGET_PCLK_47_6)
//P1_ATT PCLK -> 47.6MHz
rate = 48000000;
#else
rate = 54000000;
#endif
#endif
clk_set_rate(sclk, rate);
dev_dbg(&pdev->dev, "set fimd sclk rate to %d\n", rate);
clk_put(mout_mpll);
clk_put(mout_fimd);
#if defined(CONFIG_MACH_S5PC110_P1)
{
struct clk * sclk_mdnie;
struct clk * sclk_mdnie_pwm;
sclk_mdnie = clk_get(&pdev->dev, "sclk_mdnie");
if (IS_ERR(sclk)) {
dev_err(&pdev->dev, "failed to get sclk for mdnie\n");
}
else
{
#if defined(CONFIG_TARGET_PCLK_44_46)
clk_set_rate(sclk_mdnie, 45*1000000);
#elif defined(CONFIG_TARGET_PCLK_47_6)
//P1_ATT PCLK -> 47.6MHz
clk_set_rate(sclk_mdnie, 48*1000000);
#else
clk_set_rate(sclk_mdnie, 54*1000000);
#endif
clk_put(sclk_mdnie);
}
sclk_mdnie_pwm = clk_get(&pdev->dev, "sclk_mdnie_pwm");
if (IS_ERR(sclk)) {
dev_err(&pdev->dev, "failed to get sclk for mdnie pwm\n");
}
else
{
clk_set_rate(sclk_mdnie_pwm, 2400*1000); // mdnie pwm need to 24Khz*100
clk_put(sclk_mdnie_pwm);
}
}
#endif
ret = s5pv210_pd_enable("fimd_pd");
if (ret < 0) {
dev_err(&pdev->dev, "failed to enable fimd power domain\n");
goto err_clk2;
}
clk_enable(sclk);
*s3cfb_clk = sclk;
return 0;
err_clk2:
clk_put(mout_mpll);
err_clk1:
clk_put(sclk);
return -EINVAL;
}
/*
* This routine actually sets the video mode. It's in here where we
* the hardware state info->par and fix which can be affected by the
* change in par. For this driver it doesn't do much.
*/
static int unifb_set_par(struct fb_info *info)
{
int hTotal, vTotal, hSyncStart, hSyncEnd, vSyncStart, vSyncEnd;
int format;
#ifdef CONFIG_PUV3_PM
struct clk *clk_vga;
u32 pixclk = 0;
int i;
for (i = 0; i <= 10; i++) {
if (info->var.xres == unifb_modes[i].xres
&& info->var.yres == unifb_modes[i].yres
&& info->var.upper_margin == unifb_modes[i].upper_margin
&& info->var.lower_margin == unifb_modes[i].lower_margin
&& info->var.left_margin == unifb_modes[i].left_margin
&& info->var.right_margin == unifb_modes[i].right_margin
&& info->var.hsync_len == unifb_modes[i].hsync_len
&& info->var.vsync_len == unifb_modes[i].vsync_len) {
pixclk = unifb_modes[i].pixclock;
break;
}
}
/* set clock rate */
clk_vga = clk_get(info->device, "VGA_CLK");
if (clk_vga == ERR_PTR(-ENOENT))
return -ENOENT;
if (pixclk != 0) {
if (clk_set_rate(clk_vga, pixclk)) { /* set clock failed */
info->fix = unifb_fix;
info->var = unifb_default;
if (clk_set_rate(clk_vga, unifb_default.pixclock))
return -EINVAL;
}
}
#endif
info->fix.line_length = get_line_length(info->var.xres_virtual,
info->var.bits_per_pixel);
hSyncStart = info->var.xres + info->var.right_margin;
hSyncEnd = hSyncStart + info->var.hsync_len;
hTotal = hSyncEnd + info->var.left_margin;
vSyncStart = info->var.yres + info->var.lower_margin;
vSyncEnd = vSyncStart + info->var.vsync_len;
vTotal = vSyncEnd + info->var.upper_margin;
switch (info->var.bits_per_pixel) {
case 8:
format = UDE_CFG_DST8;
break;
case 16:
format = UDE_CFG_DST16;
break;
case 24:
format = UDE_CFG_DST24;
break;
case 32:
format = UDE_CFG_DST32;
break;
default:
return -EINVAL;
}
writel(info->fix.smem_start, UDE_FSA);
writel(info->var.yres, UDE_LS);
writel(get_line_length(info->var.xres,
info->var.bits_per_pixel) >> 3, UDE_PS);
/* >> 3 for hardware required. */
writel((hTotal << 16) | (info->var.xres), UDE_HAT);
writel(((hTotal - 1) << 16) | (info->var.xres - 1), UDE_HBT);
writel(((hSyncEnd - 1) << 16) | (hSyncStart - 1), UDE_HST);
writel((vTotal << 16) | (info->var.yres), UDE_VAT);
writel(((vTotal - 1) << 16) | (info->var.yres - 1), UDE_VBT);
writel(((vSyncEnd - 1) << 16) | (vSyncStart - 1), UDE_VST);
writel(UDE_CFG_GDEN_ENABLE | UDE_CFG_TIMEUP_ENABLE
| format | 0xC0000001, UDE_CFG);
return 0;
}
static void __init imx6q_clocks_init(struct device_node *ccm_node)
{
struct device_node *np;
void __iomem *base;
int i;
int ret;
clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0);
clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
/* Clock source from external clock via CLK1/2 PADs */
clk[IMX6QDL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0);
clk[IMX6QDL_CLK_ANACLK2] = imx_obtain_fixed_clock("anaclk2", 0);
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
base = of_iomap(np, 0);
WARN_ON(!base);
/* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */
if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) {
post_div_table[1].div = 1;
post_div_table[2].div = 1;
video_div_table[1].div = 1;
video_div_table[3].div = 1;
}
clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clk[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clk[IMX6QDL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clk[IMX6QDL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clk[IMX6QDL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clk[IMX6QDL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
clk[IMX6QDL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
/* type name parent_name base div_mask */
clk[IMX6QDL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "osc", base + 0x00, 0x7f);
clk[IMX6QDL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1);
clk[IMX6QDL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "osc", base + 0x10, 0x3);
clk[IMX6QDL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "osc", base + 0x70, 0x7f);
clk[IMX6QDL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f);
clk[IMX6QDL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3);
clk[IMX6QDL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3);
clk[IMX6QDL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
/* Do not bypass PLLs initially */
clk_set_parent(clk[IMX6QDL_PLL1_BYPASS], clk[IMX6QDL_CLK_PLL1]);
clk_set_parent(clk[IMX6QDL_PLL2_BYPASS], clk[IMX6QDL_CLK_PLL2]);
clk_set_parent(clk[IMX6QDL_PLL3_BYPASS], clk[IMX6QDL_CLK_PLL3]);
clk_set_parent(clk[IMX6QDL_PLL4_BYPASS], clk[IMX6QDL_CLK_PLL4]);
clk_set_parent(clk[IMX6QDL_PLL5_BYPASS], clk[IMX6QDL_CLK_PLL5]);
clk_set_parent(clk[IMX6QDL_PLL6_BYPASS], clk[IMX6QDL_CLK_PLL6]);
clk_set_parent(clk[IMX6QDL_PLL7_BYPASS], clk[IMX6QDL_CLK_PLL7]);
clk[IMX6QDL_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", base + 0x00, 13);
clk[IMX6QDL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
clk[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
clk[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
clk[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
clk[IMX6QDL_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
clk[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
/*
* Bit 20 is the reserved and read-only bit, we do this only for:
* - Do nothing for usbphy clk_enable/disable
* - Keep refcount when do usbphy clk_enable/disable, in that case,
* the clk framework may need to enable/disable usbphy's parent
*/
clk[IMX6QDL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
clk[IMX6QDL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
/*
* usbphy*_gate needs to be on after system boots up, and software
* never needs to control it anymore.
*/
clk[IMX6QDL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
clk[IMX6QDL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
clk[IMX6QDL_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
clk[IMX6QDL_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
clk[IMX6QDL_CLK_SATA_REF_100M] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
clk[IMX6QDL_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
clk[IMX6QDL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
base + 0xe0, 0, 2, 0, clk_enet_ref_table,
&imx_ccm_lock);
clk[IMX6QDL_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
clk[IMX6QDL_CLK_LVDS2_SEL] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
/*
* lvds1_gate and lvds2_gate are pseudo-gates. Both can be
* independently configured as clock inputs or outputs. We treat
* the "output_enable" bit as a gate, even though it's really just
* enabling clock output.
*/
clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate_exclusive("lvds1_gate", "lvds1_sel", base + 0x160, 10, BIT(12));
clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate_exclusive("lvds2_gate", "lvds2_sel", base + 0x160, 11, BIT(13));
clk[IMX6QDL_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10));
clk[IMX6QDL_CLK_LVDS2_IN] = imx_clk_gate_exclusive("lvds2_in", "anaclk2", base + 0x160, 13, BIT(11));
/* name parent_name reg idx */
clk[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
clk[IMX6QDL_CLK_PLL2_PFD1_594M] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
clk[IMX6QDL_CLK_PLL2_PFD2_396M] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
clk[IMX6QDL_CLK_PLL3_PFD0_720M] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
clk[IMX6QDL_CLK_PLL3_PFD1_540M] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
clk[IMX6QDL_CLK_PLL3_PFD2_508M] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
clk[IMX6QDL_CLK_PLL3_PFD3_454M] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
/* name parent_name mult div */
clk[IMX6QDL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
clk[IMX6QDL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2);
clk[IMX6QDL_CLK_GPT_3M] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
clk[IMX6QDL_CLK_VIDEO_27M] = imx_clk_fixed_factor("video_27m", "pll3_pfd1_540m", 1, 20);
if (clk_on_imx6dl() || clk_on_imx6qp()) {
clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1);
clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1);
}
clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
clk[IMX6QDL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
clk[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
np = ccm_node;
base = of_iomap(np, 0);
WARN_ON(!base);
/* name reg shift width parent_names num_parents */
clk[IMX6QDL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
clk[IMX6QDL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
clk[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
clk[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
clk[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
clk[IMX6QDL_CLK_AXI_SEL] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels));
clk[IMX6QDL_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
clk[IMX6QDL_CLK_ASRC_SEL] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
clk[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
if (clk_on_imx6q()) {
clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
}
if (clk_on_imx6qp()) {
clk[IMX6QDL_CLK_CAN_SEL] = imx_clk_mux("can_sel", base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels));
clk[IMX6QDL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels));
clk[IMX6QDL_CLK_IPG_PER_SEL] = imx_clk_mux("ipg_per_sel", base + 0x1c, 6, 1, ipg_per_sels, ARRAY_SIZE(ipg_per_sels));
clk[IMX6QDL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels));
clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels_2, ARRAY_SIZE(gpu2d_core_sels_2));
} else if (clk_on_imx6dl()) {
clk[IMX6QDL_CLK_MLB_SEL] = imx_clk_mux("mlb_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels));
} else {
clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels));
}
clk[IMX6QDL_CLK_GPU3D_CORE_SEL] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels));
if (clk_on_imx6dl())
clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
else
clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
clk[IMX6QDL_CLK_IPU1_SEL] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
clk[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_HSI_TX_SEL] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels));
clk[IMX6QDL_CLK_PCIE_AXI_SEL] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
if (clk_on_imx6qp()) {
clk[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels_2, ARRAY_SIZE(ipu1_di0_sels_2), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels_2, ARRAY_SIZE(ipu1_di1_sels_2), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels_2, ARRAY_SIZE(ipu2_di0_sels_2), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels_2, ARRAY_SIZE(ipu2_di1_sels_2), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
clk[IMX6QDL_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
clk[IMX6QDL_CLK_SSI3_SEL] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
clk[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
clk[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
clk[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
clk[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
clk[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 15, 3, enfc_sels_2, ARRAY_SIZE(enfc_sels_2));
clk[IMX6QDL_CLK_EIM_SEL] = imx_clk_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels));
clk[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels));
clk[IMX6QDL_CLK_PRE_AXI] = imx_clk_mux("pre_axi", base + 0x18, 1, 1, pre_axi_sels, ARRAY_SIZE(pre_axi_sels));
} else {
clk[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT);
clk[IMX6QDL_CLK_SSI1_SEL] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
clk[IMX6QDL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
clk[IMX6QDL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
clk[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
clk[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
clk[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
clk[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
clk[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
clk[IMX6QDL_CLK_EIM_SEL] = imx_clk_fixup_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels), imx_cscmr1_fixup);
clk[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_fixup_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels), imx_cscmr1_fixup);
}
clk[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
clk[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
clk[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
clk[IMX6QDL_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
clk[IMX6QDL_CLK_CKO] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
/* name reg shift width busy: reg, shift parent_names num_parents */
clk[IMX6QDL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
clk[IMX6QDL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
/* name parent_name reg shift width */
clk[IMX6QDL_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
clk[IMX6QDL_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
clk[IMX6QDL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
clk[IMX6QDL_CLK_ESAI_PRED] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3);
clk[IMX6QDL_CLK_ESAI_PODF] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3);
clk[IMX6QDL_CLK_ASRC_PRED] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3);
clk[IMX6QDL_CLK_ASRC_PODF] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3);
clk[IMX6QDL_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
clk[IMX6QDL_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
if (clk_on_imx6qp()) {
clk[IMX6QDL_CLK_IPG_PER] = imx_clk_divider("ipg_per", "ipg_per_sel", base + 0x1c, 0, 6);
clk[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6);
clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "can_sel", base + 0x20, 2, 6);
clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "uart_sel", base + 0x24, 0, 6);
clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0", 2, 7);
clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1", 2, 7);
} else {
clk[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6);
clk[IMX6QDL_CLK_IPG_PER] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup);
clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
}
if (clk_on_imx6dl())
clk[IMX6QDL_CLK_MLB_PODF] = imx_clk_divider("mlb_podf", "mlb_sel", base + 0x18, 23, 3);
else
clk[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3);
clk[IMX6QDL_CLK_GPU3D_CORE_PODF] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3);
if (clk_on_imx6dl())
clk[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 29, 3);
else
clk[IMX6QDL_CLK_GPU3D_SHADER] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3);
clk[IMX6QDL_CLK_IPU1_PODF] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3);
clk[IMX6QDL_CLK_IPU2_PODF] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3);
clk[IMX6QDL_CLK_LDB_DI0_PODF] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0);
clk[IMX6QDL_CLK_LDB_DI1_PODF] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0);
clk[IMX6QDL_CLK_IPU1_DI0_PRE] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3);
clk[IMX6QDL_CLK_IPU1_DI1_PRE] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3);
clk[IMX6QDL_CLK_IPU2_DI0_PRE] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3);
clk[IMX6QDL_CLK_IPU2_DI1_PRE] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3);
clk[IMX6QDL_CLK_HSI_TX_PODF] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3);
clk[IMX6QDL_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
clk[IMX6QDL_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
clk[IMX6QDL_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
clk[IMX6QDL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
clk[IMX6QDL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
clk[IMX6QDL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
clk[IMX6QDL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
clk[IMX6QDL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
clk[IMX6QDL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
clk[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
clk[IMX6QDL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
clk[IMX6QDL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
if (clk_on_imx6qp()) {
clk[IMX6QDL_CLK_EIM_PODF] = imx_clk_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3);
clk[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3);
} else {
clk[IMX6QDL_CLK_EIM_PODF] = imx_clk_fixup_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup);
clk[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_fixup_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup);
}
clk[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
clk[IMX6QDL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
clk[IMX6QDL_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
/* name parent_name reg shift width busy: reg, shift */
clk[IMX6QDL_CLK_AXI] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
clk[IMX6QDL_CLK_MMDC_CH0_AXI_PODF] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4);
if (clk_on_imx6qp()) {
clk[IMX6QDL_CLK_MMDC_CH1_AXI_CG] = imx_clk_gate("mmdc_ch1_axi_cg", "periph2", base + 0x4, 18);
clk[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "mmdc_ch1_axi_cg", base + 0x14, 3, 3, base + 0x48, 2);
} else {
clk[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
}
clk[IMX6QDL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
clk[IMX6QDL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
/* name parent_name reg shift */
clk[IMX6QDL_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2_shared("asrc", "asrc_podf", base + 0x68, 6, &share_count_asrc);
clk[IMX6QDL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc);
clk[IMX6QDL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc);
clk[IMX6QDL_CLK_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8);
clk[IMX6QDL_CLK_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10);
clk[IMX6QDL_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12);
clk[IMX6QDL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
clk[IMX6QDL_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20);
clk[IMX6QDL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
clk[IMX6QDL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
clk[IMX6QDL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
clk[IMX6QDL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
if (clk_on_imx6dl())
clk[IMX6DL_CLK_I2C4] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8);
else
clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
clk[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
clk[IMX6QDL_CLK_ESAI_EXTAL] = imx_clk_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai);
clk[IMX6QDL_CLK_ESAI_IPG] = imx_clk_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai);
clk[IMX6QDL_CLK_ESAI_MEM] = imx_clk_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai);
clk[IMX6QDL_CLK_GPT_IPG] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
clk[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
clk[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
clk[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "video_27m", base + 0x70, 4);
clk[IMX6QDL_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6);
clk[IMX6QDL_CLK_I2C2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8);
clk[IMX6QDL_CLK_I2C3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
clk[IMX6QDL_CLK_IIM] = imx_clk_gate2("iim", "ipg", base + 0x70, 12);
clk[IMX6QDL_CLK_ENFC] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14);
clk[IMX6QDL_CLK_VDOA] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26);
clk[IMX6QDL_CLK_IPU1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0);
clk[IMX6QDL_CLK_IPU1_DI0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2);
clk[IMX6QDL_CLK_IPU1_DI1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4);
clk[IMX6QDL_CLK_IPU2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6);
clk[IMX6QDL_CLK_IPU2_DI0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8);
if (clk_on_imx6qp()) {
clk[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_sel", base + 0x74, 12);
clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_sel", base + 0x74, 14);
} else {
clk[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12);
clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
}
clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2_shared("hsi_tx", "hsi_tx_podf", base + 0x74, 16, &share_count_mipi_core_cfg);
clk[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_gate2_shared("mipi_core_cfg", "video_27m", base + 0x74, 16, &share_count_mipi_core_cfg);
clk[IMX6QDL_CLK_MIPI_IPG] = imx_clk_gate2_shared("mipi_ipg", "ipg", base + 0x74, 16, &share_count_mipi_core_cfg);
if (clk_on_imx6dl())
/*
* The multiplexer and divider of the imx6q clock gpu2d get
* redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl.
*/
clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "mlb_podf", base + 0x74, 18);
else
clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "axi", base + 0x74, 18);
clk[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20);
clk[IMX6QDL_CLK_MMDC_CH1_AXI] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
clk[IMX6QDL_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
clk[IMX6QDL_CLK_OPENVG_AXI] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
clk[IMX6QDL_CLK_PCIE_AXI] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
clk[IMX6QDL_CLK_PER1_BCH] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
clk[IMX6QDL_CLK_PWM1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
clk[IMX6QDL_CLK_PWM2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
clk[IMX6QDL_CLK_PWM3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20);
clk[IMX6QDL_CLK_PWM4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22);
clk[IMX6QDL_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
clk[IMX6QDL_CLK_GPMI_BCH] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
clk[IMX6QDL_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28);
clk[IMX6QDL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
clk[IMX6QDL_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0);
clk[IMX6QDL_CLK_SATA] = imx_clk_gate2("sata", "ahb", base + 0x7c, 4);
clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_spdif);
clk[IMX6QDL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif);
clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
clk[IMX6QDL_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1);
clk[IMX6QDL_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2);
clk[IMX6QDL_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3);
clk[IMX6QDL_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
clk[IMX6QDL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26);
clk[IMX6QDL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
clk[IMX6QDL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
clk[IMX6QDL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
clk[IMX6QDL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
clk[IMX6QDL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
clk[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "eim_slow_podf", base + 0x80, 10);
clk[IMX6QDL_CLK_VDO_AXI] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
clk[IMX6QDL_CLK_VPU_AXI] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
if (clk_on_imx6qp()) {
clk[IMX6QDL_CLK_PRE0] = imx_clk_gate2("pre0", "pre_axi", base + 0x80, 16);
clk[IMX6QDL_CLK_PRE1] = imx_clk_gate2("pre1", "pre_axi", base + 0x80, 18);
clk[IMX6QDL_CLK_PRE2] = imx_clk_gate2("pre2", "pre_axi", base + 0x80, 20);
clk[IMX6QDL_CLK_PRE3] = imx_clk_gate2("pre3", "pre_axi", base + 0x80, 22);
clk[IMX6QDL_CLK_PRG0_AXI] = imx_clk_gate2_shared("prg0_axi", "ipu1_podf", base + 0x80, 24, &share_count_prg0);
clk[IMX6QDL_CLK_PRG1_AXI] = imx_clk_gate2_shared("prg1_axi", "ipu2_podf", base + 0x80, 26, &share_count_prg1);
clk[IMX6QDL_CLK_PRG0_APB] = imx_clk_gate2_shared("prg0_apb", "ipg", base + 0x80, 24, &share_count_prg0);
clk[IMX6QDL_CLK_PRG1_APB] = imx_clk_gate2_shared("prg1_apb", "ipg", base + 0x80, 26, &share_count_prg1);
}
clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
clk[IMX6QDL_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
/*
* The gpt_3m clock is not available on i.MX6Q TO1.0. Let's point it
* to clock gpt_ipg_per to ease the gpt driver code.
*/
if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0)
clk[IMX6QDL_CLK_GPT_3M] = clk[IMX6QDL_CLK_GPT_IPG_PER];
imx_check_clocks(clk, ARRAY_SIZE(clk));
clk_data.clks = clk;
clk_data.clk_num = ARRAY_SIZE(clk);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
clk_register_clkdev(clk[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL);
if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
clk_on_imx6dl()) {
clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
}
clk_set_rate(clk[IMX6QDL_CLK_PLL3_PFD1_540M], 540000000);
if (clk_on_imx6dl())
clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]);
clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]);
clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], clk[IMX6QDL_CLK_IPU1_DI1_PRE]);
clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]);
clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], clk[IMX6QDL_CLK_IPU2_DI1_PRE]);
/*
* The gpmi needs 100MHz frequency in the EDO/Sync mode,
* We can not get the 100MHz from the pll2_pfd0_352m.
* So choose pll2_pfd2_396m as enfc_sel's parent.
*/
clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]);
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
clk_prepare_enable(clk[clks_init_on[i]]);
if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]);
clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]);
}
/*
* Let's initially set up CLKO with OSC24M, since this configuration
* is widely used by imx6q board designs to clock audio codec.
*/
ret = clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]);
if (!ret)
ret = clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]);
if (ret)
pr_warn("failed to set up CLKO: %d\n", ret);
/* Audio-related clocks configuration */
clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]);
/* All existing boards with PCIe use LVDS1 */
if (IS_ENABLED(CONFIG_PCI_IMX6))
clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]);
/*
* Initialize the GPU clock muxes, so that the maximum specified clock
* rates for the respective SoC are not exceeded.
*/
if (clk_on_imx6dl()) {
clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL],
clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL],
clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
} else if (clk_on_imx6q()) {
clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL],
clk[IMX6QDL_CLK_MMDC_CH0_AXI]);
clk_set_parent(clk[IMX6QDL_CLK_GPU3D_SHADER_SEL],
clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL],
clk[IMX6QDL_CLK_PLL3_USB_OTG]);
}
imx_register_uart_clocks(uart_clks);
}
static int exynos4415_fimc_is_cfg_clk(struct platform_device *pdev)
{
struct clk *mout_isp_pll = NULL;
struct clk *mout_aclk_isp0_300 = NULL;
struct clk *dout_aclk_isp0_300 = NULL;
struct clk *mout_aclk_isp1_300 = NULL;
struct clk *dout_aclk_isp1_300 = NULL;
struct clk *aclk_isp0_300 = NULL;
struct clk *aclk_isp1_300 = NULL;
struct clk *dout_sclk_csis1 = NULL;
struct clk *dout_aclk_3aa1 = NULL;
struct clk *dout_aclk_lite_b = NULL;
struct clk *dout_pclk_isp0_a_150 = NULL;
struct clk *dout_pclk_isp0_b_150 = NULL;
struct clk *dout_pclk_isp0_b_75 = NULL;
struct clk *dout_pclk_isp1_150 = NULL;
struct clk *dout_pclk_isp1_75 = NULL;
struct clk *aclk_isp0_400 = NULL;
struct clk *aclk_isp0_400_pre = NULL;
struct clk *mout_mpll_user_top = NULL;
struct clk *sclk_pwm_isp = NULL;
struct clk *dout_spi0_isp = NULL;
struct clk *dout_spi1_isp = NULL;
struct clk *sclk_csis0 = NULL;
struct clk *sclk_csis1 = NULL;
struct clk *sclk_pxlasync_csis0_fimc = NULL;
struct clk *sclk_pxlasync_csis1_fimc = NULL;
struct clk *phyclk_rxbyte_clkhs0_s2a = NULL;
struct clk *mout_phyclk_rxbyte_clkhs0_s2a = NULL;
struct clk *phyclk_rxbyte_clkhs0_s4 = NULL;
struct clk *mout_phyclk_rxbyte_clkhs0_s4 = NULL;
/* front DPHY */
phyclk_rxbyte_clkhs0_s2a = clk_get(&pdev->dev, "phyclk_rxbyte_clkhs0_s2a");
if (IS_ERR(phyclk_rxbyte_clkhs0_s2a)) {
pr_err("%s : clk_get(phyclk_rxbyte_clkhs0_s2a) failed\n", __func__);
return PTR_ERR(phyclk_rxbyte_clkhs0_s2a);
}
mout_phyclk_rxbyte_clkhs0_s2a = clk_get(&pdev->dev, "mout_phyclk_rxbyte_clkhs0_s2a");
if (IS_ERR(mout_phyclk_rxbyte_clkhs0_s2a)) {
pr_err("%s : clk_get(mout_phyclk_rxbyte_clkhs0_s2a) failed\n", __func__);
return PTR_ERR(mout_phyclk_rxbyte_clkhs0_s2a);
}
clk_set_parent(mout_phyclk_rxbyte_clkhs0_s2a, phyclk_rxbyte_clkhs0_s2a);
clk_put(mout_phyclk_rxbyte_clkhs0_s2a);
clk_put(phyclk_rxbyte_clkhs0_s2a);
/* main DPHY */
phyclk_rxbyte_clkhs0_s4 = clk_get(&pdev->dev, "phyclk_rxbyte_clkhs0_s4");
if (IS_ERR(phyclk_rxbyte_clkhs0_s4)) {
pr_err("%s : clk_get(phyclk_rxbyte_clkhs0_s4) failed\n", __func__);
return PTR_ERR(phyclk_rxbyte_clkhs0_s4);
}
mout_phyclk_rxbyte_clkhs0_s4 = clk_get(&pdev->dev, "mout_phyclk_rxbyte_clkhs0_s4");
if (IS_ERR(mout_phyclk_rxbyte_clkhs0_s4)) {
pr_err("%s : clk_get(mout_phyclk_rxbyte_clkhs0_s4) failed\n", __func__);
return PTR_ERR(mout_phyclk_rxbyte_clkhs0_s4);
}
clk_set_parent(mout_phyclk_rxbyte_clkhs0_s4, phyclk_rxbyte_clkhs0_s4);
clk_put(mout_phyclk_rxbyte_clkhs0_s4);
clk_put(phyclk_rxbyte_clkhs0_s4);
mout_isp_pll = clk_get(&pdev->dev, "mout_isp_pll");
if (IS_ERR(mout_isp_pll)) {
pr_err("%s : clk_get(mout_isp_pll) failed\n", __func__);
return PTR_ERR(mout_isp_pll);
}
/* ack_isp0_300 */
mout_aclk_isp0_300 = clk_get(&pdev->dev, "mout_aclk_isp0_300");
if (IS_ERR(mout_aclk_isp0_300)) {
pr_err("%s : clk_get(mout_aclk_isp0_300) failed\n", __func__);
clk_put(mout_isp_pll);
return PTR_ERR(mout_aclk_isp0_300);
}
dout_aclk_isp0_300 = clk_get(&pdev->dev, "dout_aclk_isp0_300");
if (IS_ERR(dout_aclk_isp0_300)) {
pr_err("%s : clk_get(dout_aclk_isp0_300) failed\n", __func__);
clk_put(mout_isp_pll);
clk_put(mout_aclk_isp0_300);
return PTR_ERR(dout_aclk_isp0_300);
}
aclk_isp0_300 = clk_get(&pdev->dev, "aclk_isp0_300");
if (IS_ERR(aclk_isp0_300)) {
pr_err("%s : clk_get(aclk_isp0_300) failed\n", __func__);
clk_put(mout_isp_pll);
clk_put(mout_aclk_isp0_300);
clk_put(dout_aclk_isp0_300);
return PTR_ERR(aclk_isp0_300);
}
clk_set_parent(mout_aclk_isp0_300, mout_isp_pll);
clk_set_parent(aclk_isp0_300, dout_aclk_isp0_300);
clk_set_rate(dout_aclk_isp0_300, 300 * 1000000);
pr_info("dout_aclk_isp0_300 : %ld\n", clk_get_rate(dout_aclk_isp0_300));
clk_put(mout_aclk_isp0_300);
clk_put(dout_aclk_isp0_300);
clk_put(aclk_isp0_300);
/* ack_isp1_300 */
mout_aclk_isp1_300 = clk_get(&pdev->dev, "mout_aclk_isp1_300");
if (IS_ERR(mout_aclk_isp1_300)) {
pr_err("%s : clk_get(mout_aclk_isp1_300) failed\n", __func__);
clk_put(mout_isp_pll);
return PTR_ERR(mout_aclk_isp1_300);
}
dout_aclk_isp1_300 = clk_get(&pdev->dev, "dout_aclk_isp1_300");
if (IS_ERR(dout_aclk_isp1_300)) {
pr_err("%s : clk_get(dout_aclk_isp1_300) failed\n", __func__);
clk_put(mout_isp_pll);
clk_put(mout_aclk_isp1_300);
return PTR_ERR(dout_aclk_isp1_300);
}
aclk_isp1_300 = clk_get(&pdev->dev, "aclk_isp1_300");
if (IS_ERR(aclk_isp1_300)) {
pr_err("%s : clk_get(aclk_isp1_300) failed\n", __func__);
clk_put(mout_isp_pll);
clk_put(mout_aclk_isp1_300);
clk_put(dout_aclk_isp1_300);
return PTR_ERR(aclk_isp1_300);
}
clk_set_parent(mout_aclk_isp1_300, mout_isp_pll);
clk_set_parent(aclk_isp1_300, dout_aclk_isp1_300);
clk_set_rate(dout_aclk_isp1_300, 300 * 1000000);
pr_info("dout_aclk_isp1_300 : %ld\n", clk_get_rate(dout_aclk_isp1_300));
clk_put(mout_aclk_isp1_300);
clk_put(dout_aclk_isp1_300);
clk_put(aclk_isp1_300);
/* PWM */
sclk_pwm_isp = clk_get(&pdev->dev, "sclk_pwm_isp");
if (IS_ERR(sclk_pwm_isp)) {
pr_err("%s : clk_get(sclk_pwm_isp) failed\n", __func__);
return PTR_ERR(sclk_pwm_isp);
}
clk_set_parent(sclk_pwm_isp, mout_isp_pll);
clk_set_rate(sclk_pwm_isp, 75* 1000000);
pr_info("sclk_pwm_isp : %ld\n", clk_get_rate(sclk_pwm_isp));
clk_put(sclk_pwm_isp);
/* SPI0 */
dout_spi0_isp = clk_get(&pdev->dev, "dout_spi0_isp");
if (IS_ERR(dout_spi0_isp)) {
pr_err("%s : clk_get(dout_spi0_isp) failed\n", __func__);
return PTR_ERR(dout_spi0_isp);
}
clk_set_parent(dout_spi0_isp, mout_isp_pll);
clk_set_rate(dout_spi0_isp, 50* 1000000);
pr_info("dout_spi0_isp : %ld\n", clk_get_rate(dout_spi0_isp));
clk_put(dout_spi0_isp);
/* SPI1 */
dout_spi1_isp = clk_get(&pdev->dev, "dout_spi1_isp");
if (IS_ERR(dout_spi1_isp)) {
pr_err("%s : clk_get(dout_spi1_isp) failed\n", __func__);
return PTR_ERR(dout_spi1_isp);
}
clk_set_parent(dout_spi1_isp, mout_isp_pll);
clk_set_rate(dout_spi1_isp, 50* 1000000);
pr_info("dout_spi1_isp : %ld\n", clk_get_rate(dout_spi1_isp));
clk_put(dout_spi1_isp);
/* CSIS0 */
sclk_csis0 = clk_get(&pdev->dev, "sclk_csis0");
if (IS_ERR(sclk_csis0)) {
pr_err("%s : clk_get(sclk_csis0) failed\n", __func__);
return PTR_ERR(sclk_csis0);
}
clk_set_parent(sclk_csis0, mout_isp_pll);
clk_set_rate(sclk_csis0, 266 * 1000000);
pr_info("sclk_csis0 : %ld\n", clk_get_rate(sclk_csis0));
clk_put(sclk_csis0);
/* CSIS1 */
sclk_csis1 = clk_get(&pdev->dev, "sclk_csis1");
if (IS_ERR(sclk_csis1)) {
pr_err("%s : clk_get(sclk_csis1) failed\n", __func__);
return PTR_ERR(sclk_csis1);
}
clk_set_parent(sclk_csis1, mout_isp_pll);
clk_set_rate(sclk_csis1, 266 * 1000000);
pr_info("sclk_csis1 : %ld\n", clk_get_rate(sclk_csis1));
clk_put(sclk_csis1);
sclk_pxlasync_csis0_fimc = clk_get(&pdev->dev, "sclk_pxlasync_csis0_fimc");
if (IS_ERR(sclk_pxlasync_csis0_fimc)) {
pr_err("%s : clk_get(sclk_pxlasync_csis0_fimc) failed\n", __func__);
return PTR_ERR(sclk_pxlasync_csis0_fimc);
}
clk_set_parent(sclk_pxlasync_csis0_fimc, mout_isp_pll);
clk_set_rate(sclk_pxlasync_csis0_fimc, 160 * 1000000);
pr_info("sclk_pxlasync_csis0_fimc : %ld\n", clk_get_rate(sclk_pxlasync_csis0_fimc));
clk_put(sclk_pxlasync_csis0_fimc);
sclk_pxlasync_csis1_fimc = clk_get(&pdev->dev, "sclk_pxlasync_csis1_fimc");
if (IS_ERR(sclk_pxlasync_csis1_fimc)) {
pr_err("%s : clk_get(sclk_pxlasync_csis1_fimc) failed\n", __func__);
return PTR_ERR(sclk_pxlasync_csis1_fimc);
}
clk_set_parent(sclk_pxlasync_csis1_fimc, mout_isp_pll);
clk_set_rate(sclk_pxlasync_csis1_fimc, 160 * 1000000);
pr_info("sclk_pxlasync_csis1_fimc : %ld\n", clk_get_rate(sclk_pxlasync_csis1_fimc));
clk_put(sclk_pxlasync_csis1_fimc);
clk_put(mout_isp_pll);
dout_sclk_csis1 = clk_get(&pdev->dev, "dout_sclk_csis1");
if (IS_ERR(dout_sclk_csis1)) {
pr_err("%s : clk_get(dout_sclk_csis1) failed\n", __func__);
return PTR_ERR(dout_sclk_csis1);
}
clk_set_rate(dout_sclk_csis1, 300 * 1000000);
pr_info("dout_sclk_csis1 : %ld\n", clk_get_rate(dout_sclk_csis1));
clk_put(dout_sclk_csis1);
dout_aclk_3aa1 = clk_get(&pdev->dev, "dout_aclk_3aa1");
if (IS_ERR(dout_aclk_3aa1)) {
pr_err("%s : clk_get(dout_aclk_3aa1) failed\n", __func__);
return PTR_ERR(dout_aclk_3aa1);
}
clk_set_rate(dout_aclk_3aa1, 300 * 1000000);
pr_info("dout_aclk_3aa1 : %ld\n", clk_get_rate(dout_aclk_3aa1));
clk_put(dout_aclk_3aa1);
dout_aclk_lite_b = clk_get(&pdev->dev, "dout_aclk_lite_b");
if (IS_ERR(dout_aclk_lite_b)) {
pr_err("%s : clk_get(dout_aclk_lite_b) failed\n", __func__);
return PTR_ERR(dout_aclk_lite_b);
}
clk_set_rate(dout_aclk_lite_b, 300 * 1000000);
pr_info("dout_aclk_lite_b : %ld\n", clk_get_rate(dout_aclk_lite_b));
clk_put(dout_aclk_lite_b);
dout_pclk_isp0_a_150 = clk_get(&pdev->dev, "dout_pclk_isp0_a_150");
if (IS_ERR(dout_pclk_isp0_a_150)) {
pr_err("%s : clk_get(dout_pclk_isp0_a_150) failed\n", __func__);
return PTR_ERR(dout_pclk_isp0_a_150);
}
clk_set_rate(dout_pclk_isp0_a_150, 150* 1000000);
pr_info("dout_pclk_isp0_a_150 : %ld\n", clk_get_rate(dout_pclk_isp0_a_150));
clk_put(dout_pclk_isp0_a_150);
dout_pclk_isp0_b_150 = clk_get(&pdev->dev, "dout_pclk_isp0_b_150");
if (IS_ERR(dout_pclk_isp0_b_150)) {
pr_err("%s : clk_get(dout_pclk_isp0_b_150) failed\n", __func__);
return PTR_ERR(dout_pclk_isp0_b_150);
}
clk_set_rate(dout_pclk_isp0_b_150, 150* 1000000);
pr_info("dout_pclk_isp0_b_150 : %ld\n", clk_get_rate(dout_pclk_isp0_b_150));
clk_put(dout_pclk_isp0_b_150);
dout_pclk_isp0_b_75 = clk_get(&pdev->dev, "dout_pclk_isp0_b_75");
if (IS_ERR(dout_pclk_isp0_b_75)) {
pr_err("%s : clk_get(dout_pclk_isp0_b_75) failed\n", __func__);
return PTR_ERR(dout_pclk_isp0_b_75);
}
clk_set_rate(dout_pclk_isp0_b_75, 75* 1000000);
pr_info("dout_pclk_isp0_b_75 : %ld\n", clk_get_rate(dout_pclk_isp0_b_75));
clk_put(dout_pclk_isp0_b_75);
/* aclk_isp_400 */
aclk_isp0_400 = clk_get(&pdev->dev, "aclk_isp0_400");
if (IS_ERR(aclk_isp0_400)) {
pr_err("%s : clk_get(aclk_isp0_400) failed\n", __func__);
return PTR_ERR(aclk_isp0_400);
}
aclk_isp0_400_pre = clk_get(&pdev->dev, "aclk_isp0_400_pre");
if (IS_ERR(aclk_isp0_400_pre)) {
pr_err("%s : clk_get(aclk_isp0_400_pre) failed\n", __func__);
clk_put(aclk_isp0_400);
return PTR_ERR(aclk_isp0_400_pre);
}
mout_mpll_user_top = clk_get(&pdev->dev, "mout_mpll_user_top");
if (IS_ERR(mout_mpll_user_top)) {
pr_err("%s : clk_get(mout_mpll_user_top) failed\n", __func__);
clk_put(aclk_isp0_400);
clk_put(aclk_isp0_400_pre);
return PTR_ERR(mout_mpll_user_top);
}
clk_set_parent(aclk_isp0_400, aclk_isp0_400_pre);
clk_set_parent(aclk_isp0_400_pre, mout_mpll_user_top);
clk_set_rate(aclk_isp0_400_pre, 400 * 1000000);
pr_info("aclk_isp0_400_pre : %ld\n", clk_get_rate(aclk_isp0_400_pre));
clk_put(aclk_isp0_400);
clk_put(aclk_isp0_400_pre);
clk_put(mout_mpll_user_top);
dout_pclk_isp1_150 = clk_get(&pdev->dev, "dout_pclk_isp1_150");
if (IS_ERR(dout_pclk_isp1_150)) {
pr_err("%s : clk_get(dout_pclk_isp1_150) failed\n", __func__);
return PTR_ERR(dout_pclk_isp1_150);
}
clk_set_rate(dout_pclk_isp1_150, 150* 1000000);
pr_info("dout_pclk_isp1_150 : %ld\n", clk_get_rate(dout_pclk_isp1_150));
clk_put(dout_pclk_isp1_150);
dout_pclk_isp1_75 = clk_get(&pdev->dev, "dout_pclk_isp1_75");
if (IS_ERR(dout_pclk_isp1_75)) {
pr_err("%s : clk_get(dout_pclk_isp1_75) failed\n", __func__);
return PTR_ERR(dout_pclk_isp1_75);
}
clk_set_rate(dout_pclk_isp1_75, 75* 1000000);
pr_info("dout_pclk_isp1_75 : %ld\n", clk_get_rate(dout_pclk_isp1_75));
clk_put(dout_pclk_isp1_75);
#ifdef CLOCK_OUT_DEBUG
/*
* clock out top debug
* writel(((1 << 16) | 0x18), EXYNOS4415_CLKOUT_CMU_TOP);
* writel((0x1 << 8), EXYNOS_PMU_DEBUG);
*/
/* clock out isp sub debug */
writel(((1 << 16) | 0x5), EXYNOS4415_CLKOUT_CMU_ISP);
writel((0x5 << 8), EXYNOS_PMU_DEBUG);
while(1) {
pr_info(".");
msleep(1000);
}
#endif
return 0;
}
static __devinit int asoc_dmic_probe(struct platform_device *pdev)
{
struct tegra_dmic *dmic;
struct resource *dmic_resource, *dmic_region;
int ret = 0;
char *dmic_clk_name;
long unsigned parent_rate;
dmic = devm_kzalloc(&pdev->dev, sizeof(struct tegra_dmic),
GFP_KERNEL);
if (!dmic)
return -ENOMEM;
platform_set_drvdata(pdev, dmic);
dmic->dev = &pdev->dev;
tegra_dmic_init_params(dmic);
mutex_init(&dmic->mutex);
switch (pdev->id) {
case TEGRA_DMIC_FRONT:
dmic_clk_name = "dmic0";
break;
case TEGRA_DMIC_BACK:
dmic_clk_name = "dmic1";
break;
default:
ret = -EINVAL;
goto err_free_dmic;
}
dmic->clk = clk_get(dmic->dev, dmic_clk_name);
if (IS_ERR(dmic->clk)) {
dev_err(dmic->dev, "cant get dmic clk\n");
ret = -ENODEV;
goto err_put_clk;
}
dmic->parent = clk_get(dmic->dev, "pll_a_out0");
if (IS_ERR(dmic->parent)) {
dev_err(dmic->dev, "cant get dmic parent\n");
ret = -ENODEV;
goto err_put_clk;
}
parent_rate = clk_get_rate(dmic->parent);
ret = clk_set_rate(dmic->clk, parent_rate);
if (ret < 0) {
dev_err(dmic->dev, "can't set dmic clk rate\n");
goto err_put_clk;
}
dmic_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!dmic_resource) {
dev_err(&pdev->dev, "No memory 0 resource\n");
ret = -ENODEV;
goto err_put_clk;
}
dmic_region = devm_request_mem_region(&pdev->dev,
dmic_resource->start, resource_size(dmic_resource),
pdev->name);
if (!dmic_region) {
dev_err(&pdev->dev, "Memory region 0 already claimed\n");
ret = -EBUSY;
goto err_put_clk;
}
dmic->io_base = devm_ioremap(&pdev->dev, dmic_resource->start,
resource_size(dmic_resource));
if (!dmic->io_base) {
dev_err(&pdev->dev, "ioremap 0 failed\n");
ret = -ENOMEM;
goto err_put_clk;
}
ret = snd_soc_register_dai(&pdev->dev, &tegra_dmic_dai[pdev->id]);
if (ret) {
dev_err(&pdev->dev, "dai registration failed\n");
ret = -EBUSY;
goto err_put_clk;
}
tegra_dmic_debug_add(dmic, pdev->id);
return 0;
err_put_clk:
if (dmic->parent)
clk_put(dmic->parent);
if (dmic->clk)
clk_put(dmic->clk);
err_free_dmic:
kfree(dmic);
return ret;
}
int exynos3_fimc_is_cfg_clk(struct platform_device *pdev)
{
//int cfg;
/*parent*/
struct clk *sclk_mpll_pre_div = NULL;
struct clk *xusbxti = NULL;
/*mcuisp*/
struct clk *dout_aclk_400 = NULL;
struct clk *aclk_400_mcuisp = NULL;
struct clk *aclk_mcuisp_div0 = NULL;
struct clk *aclk_mcuisp_div1 = NULL;
/*ack_266*/
struct clk *mout_aclk_266_0 = NULL;
struct clk *dout_aclk_266 = NULL;
struct clk *aclk_266 = NULL;
struct clk *aclk_div0 = NULL;
struct clk *aclk_div1 = NULL;
struct clk *aclk_div2 = NULL;
/*function sclk*/
// struct clk *sclk_pwm_isp = NULL;
struct clk *sclk_uart_isp = NULL;
struct clk *sclk_spi1_isp = NULL;
struct clk *dout_sclk_spi1_isp = NULL;
struct clk *sclk_spi0_isp = NULL;
struct clk *dout_sclk_spi0_isp = NULL;
/*MCLK*/
struct clk *sclk_cam1 = NULL;
unsigned long mcu_isp_400;
unsigned long isp_266;
unsigned long isp_uart;
// unsigned long isp_pwm;
unsigned long isp_spi1;
unsigned long isp_spi0;
unsigned long isp_cam1;
pr_info(" %s\n",__func__);
/* initialize Clocks */
/*
* HACK: hard clock setting to preventing
* ISP init fail problem
*/
#if 0
writel(0x31, EXYNOS5_CLKDIV_ISP0);
writel(0x31, EXYNOS5_CLKDIV_ISP1);
writel(0x1, EXYNOS5_CLKDIV_ISP2);
cfg = readl(EXYNOS5_CLKDIV2_RATIO0);
cfg |= (0x1 < 6);
writel(0x1, EXYNOS5_CLKDIV2_RATIO0);
#endif
/* 0. Parent*/
sclk_mpll_pre_div = clk_get(&pdev->dev, "sclk_mpll_pre_div");
if (IS_ERR(sclk_mpll_pre_div)) {
pr_err("%s : clk_get(sclk_mpll_pre_div) failed\n", __func__);
return PTR_ERR(sclk_mpll_pre_div);
}
//clk_set_rate(sclk_mpll_pre_div, 800 * 1000000);
pr_info("sclk_mpll_pre_div : %ld\n", clk_get_rate(sclk_mpll_pre_div));
xusbxti = clk_get(&pdev->dev, "xusbxti");
if (IS_ERR(xusbxti)) {
pr_err("%s : clk_get(xxti) failed\n", __func__);
return PTR_ERR(xusbxti);
}
pr_info("xusbxti : %ld\n", clk_get_rate(xusbxti));
/* 1. MCUISP and DIV*/
/*
mout_mpll
sclk_mpll_mif
sclk_mpll_pre_div
dout_aclk_400
aclk_400_mcuisp
*/
dout_aclk_400 = clk_get(&pdev->dev, "dout_aclk_400");
if (IS_ERR(dout_aclk_400)) {
pr_err("%s : clk_get(dout_aclk_400) failed\n", __func__);
return PTR_ERR(dout_aclk_400);
}
clk_set_parent(dout_aclk_400, sclk_mpll_pre_div);
clk_set_rate(dout_aclk_400, 400 * 1000000);
aclk_400_mcuisp = clk_get(&pdev->dev, "aclk_400_mcuisp");
if (IS_ERR(aclk_400_mcuisp)) {
pr_err("%s : clk_get(aclk_400_mcuisp) failed\n", __func__);
return PTR_ERR(aclk_400_mcuisp);
}
clk_set_parent(aclk_400_mcuisp, dout_aclk_400);
/*mcuisp div*/
aclk_mcuisp_div0 = clk_get(&pdev->dev, "aclk_mcuisp_div0");
if (IS_ERR(aclk_mcuisp_div0)) {
pr_err("%s : clk_get(aclk_mcuisp_div0) failed\n", __func__);
return PTR_ERR(aclk_mcuisp_div0);
}
aclk_mcuisp_div1 = clk_get(&pdev->dev, "aclk_mcuisp_div1");
if (IS_ERR(aclk_mcuisp_div1)) {
pr_err("%s : clk_get(aclk_mcuisp_div1) failed\n", __func__);
return PTR_ERR(aclk_mcuisp_div1);
}
clk_set_rate(aclk_mcuisp_div0, 200 * 1000000);
clk_set_rate(aclk_mcuisp_div1, 100 * 1000000);
mcu_isp_400 = clk_get_rate(aclk_400_mcuisp);
pr_info("mcu_isp_400 : %ld\n", mcu_isp_400);
mcu_isp_400 = clk_get_rate(aclk_mcuisp_div0);
pr_info("mcu_isp_400_div0 : %ld\n", mcu_isp_400);
mcu_isp_400 = clk_get_rate(aclk_mcuisp_div1);
pr_info("aclk_mcuisp_div1 : %ld\n", mcu_isp_400);
//clk_put(sclk_mpll_pre_div);
clk_put(dout_aclk_400);
clk_put(aclk_400_mcuisp);
clk_put(aclk_mcuisp_div0);
clk_put(aclk_mcuisp_div1);
/* 2. ACLK_266_ISP */
/*
sclk_mpll_pre_div/mout_vpll : TODO. if we use vpll for 300M later, we will select this clk.
mout_aclk_266_0
dout_aclk_266
aclk_266
*/
mout_aclk_266_0 = clk_get(&pdev->dev, "mout_aclk_266_0");
if (IS_ERR(mout_aclk_266_0)) {
pr_err("%s : clk_get(mout_aclk_266_0) failed\n", __func__);
return PTR_ERR(mout_aclk_266_0);
}
dout_aclk_266 = clk_get(&pdev->dev, "dout_aclk_266");
if (IS_ERR(dout_aclk_266)) {
pr_err("%s : clk_get(dout_aclk_266) failed\n", __func__);
return PTR_ERR(dout_aclk_266);
}
aclk_266 = clk_get(&pdev->dev, "aclk_266");
if (IS_ERR(aclk_266)) {
pr_err("%s : clk_get(aclk_266) failed\n", __func__);
return PTR_ERR(aclk_266);
}
clk_set_parent(dout_aclk_266, mout_aclk_266_0);
clk_set_parent(aclk_266, dout_aclk_266);
// clk_set_rate(dout_aclk_266, 134 * 1000000);
clk_set_rate(dout_aclk_266, 266 * 1000000);
isp_266 = clk_get_rate(aclk_266);
pr_info("isp_266 : %ld\n", isp_266);
clk_put(mout_aclk_266_0);
clk_put(dout_aclk_266);
clk_put(aclk_266);
/* ISP_DIV0 */
aclk_div0 = clk_get(&pdev->dev, "aclk_div0");
if (IS_ERR(aclk_div0)) {
pr_err("%s : clk_get(isp_div0) failed\n", __func__);
return PTR_ERR(aclk_div0);
}
//clk_set_rate(aclk_div0, 135 * 1000000);
clk_set_rate(aclk_div0, 50 * 1000000);
pr_info("aclk_div0 : %ld\n", clk_get_rate(aclk_div0));
/* ISP_DIV1 */
aclk_div1 = clk_get(&pdev->dev, "aclk_div1");
if (IS_ERR(aclk_div1)) {
pr_err("%s : clk_get(isp_div1) failed\n", __func__);
return PTR_ERR(aclk_div1);
}
clk_set_rate(aclk_div1, 50 * 1000000);
pr_info("aclk_div1 : %ld\n", clk_get_rate(aclk_div1));
/* ISP_DIV2*/
aclk_div2 = clk_get(&pdev->dev, "aclk_div2");
if (IS_ERR(aclk_div2)) {
pr_err("%s : clk_get(mpwm_div) failed\n", __func__);
return PTR_ERR(aclk_div2);
}
clk_set_rate(aclk_div2, 50 * 1000000);
pr_info("aclk_div2 : %ld\n", clk_get_rate(aclk_div2));
clk_put(aclk_div0);
clk_put(aclk_div1);
clk_put(aclk_div2);
/* 3. SCLK_ISP_BLK */
/*UART, SPI, PWM, all from sclk_mpll_pre_div*/
/* UART-ISP */
sclk_uart_isp = clk_get(&pdev->dev, "sclk_uart_isp");
if (IS_ERR(sclk_uart_isp)) {
pr_err("%s : clk_get(sclk_uart_isp) failed\n", __func__);
return PTR_ERR(sclk_uart_isp);
}
clk_set_parent(sclk_uart_isp, sclk_mpll_pre_div);
clk_set_rate(sclk_uart_isp, 67 * 1000000);
isp_uart = clk_get_rate(sclk_uart_isp);
pr_info("isp_uart : %ld\n", isp_uart);
//clk_enable(sclk_uart_isp);//jmq.enable uart when config
clk_put(sclk_uart_isp);
/* SPI1-ISP */
sclk_spi1_isp = clk_get(&pdev->dev, "sclk_spi1_isp");
if (IS_ERR(sclk_spi1_isp)) {
pr_err("%s : clk_get(sclk_spi1_isp) failed\n", __func__);
return PTR_ERR(sclk_spi1_isp);
}
dout_sclk_spi1_isp = clk_get(&pdev->dev, "dout_sclk_spi1_isp");
if (IS_ERR(dout_sclk_spi1_isp)) {
pr_err("%s : clk_get(dout_sclk_spi1_isp) failed\n", __func__);
return PTR_ERR(dout_sclk_spi1_isp);
}
clk_set_parent(dout_sclk_spi1_isp, sclk_mpll_pre_div);
clk_set_parent(sclk_spi1_isp, dout_sclk_spi1_isp);
clk_set_rate(sclk_spi1_isp, 100 * 1000000);
isp_spi1 = clk_get_rate(sclk_spi1_isp);
pr_info("isp_spi1 : %ld\n", isp_spi1);
clk_put(sclk_spi1_isp);
clk_put(dout_sclk_spi1_isp);
/* SPI0-ISP */
sclk_spi0_isp = clk_get(&pdev->dev, "sclk_spi0_isp");
if (IS_ERR(sclk_spi0_isp)) {
pr_err("%s : clk_get(sclk_spi0_isp) failed\n", __func__);
return PTR_ERR(sclk_spi0_isp);
}
dout_sclk_spi0_isp = clk_get(&pdev->dev, "dout_sclk_spi0_isp");
if (IS_ERR(dout_sclk_spi0_isp)) {
pr_err("%s : clk_get(dout_sclk_spi0_isp) failed\n", __func__);
return PTR_ERR(dout_sclk_spi0_isp);
}
clk_set_parent(dout_sclk_spi0_isp, sclk_mpll_pre_div);
clk_set_parent(sclk_spi0_isp, dout_sclk_spi0_isp);
clk_set_rate(sclk_spi0_isp, 100 * 1000000);
isp_spi0 = clk_get_rate(sclk_spi0_isp);
pr_info("isp_spi0 : %ld\n", isp_spi0);
clk_put(sclk_spi0_isp);
clk_put(dout_sclk_spi0_isp);
/* CAM1 */
sclk_cam1 = clk_get(&pdev->dev, "sclk_cam1");
if (IS_ERR(sclk_cam1)) {
pr_err("%s : clk_get(sclk_cam1) failed\n", __func__);
return PTR_ERR(sclk_cam1);
}
clk_set_parent(sclk_cam1, xusbxti);//from where?
clk_set_rate(sclk_cam1, 24 * 1000000);
//clk_set_rate(sclk_cam1, 26 * 1000000);
isp_cam1 = clk_get_rate(sclk_cam1);
pr_info("isp_cam1 : %ld\n", isp_cam1);
//put the parent
clk_put(sclk_mpll_pre_div);
clk_put(xusbxti);
/*FLite*/
/*MIPI*/
return 0;
}
static int __init arch_setup(void)
{
struct clk *clk;
bool cn12_enabled = false;
/* register board specific self-refresh code */
sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF |
SUSP_SH_RSTANDBY,
&ecovec24_sdram_enter_start,
&ecovec24_sdram_enter_end,
&ecovec24_sdram_leave_start,
&ecovec24_sdram_leave_end);
/* enable STATUS0, STATUS2 and PDSTATUS */
gpio_request(GPIO_FN_STATUS0, NULL);
gpio_request(GPIO_FN_STATUS2, NULL);
gpio_request(GPIO_FN_PDSTATUS, NULL);
/* enable SCIFA0 */
gpio_request(GPIO_FN_SCIF0_TXD, NULL);
gpio_request(GPIO_FN_SCIF0_RXD, NULL);
/* enable debug LED */
gpio_request(GPIO_PTG0, NULL);
gpio_request(GPIO_PTG1, NULL);
gpio_request(GPIO_PTG2, NULL);
gpio_request(GPIO_PTG3, NULL);
gpio_direction_output(GPIO_PTG0, 0);
gpio_direction_output(GPIO_PTG1, 0);
gpio_direction_output(GPIO_PTG2, 0);
gpio_direction_output(GPIO_PTG3, 0);
__raw_writew((__raw_readw(PORT_HIZA) & ~(0x1 << 1)) , PORT_HIZA);
/* enable SH-Eth */
gpio_request(GPIO_PTA1, NULL);
gpio_direction_output(GPIO_PTA1, 1);
mdelay(20);
gpio_request(GPIO_FN_RMII_RXD0, NULL);
gpio_request(GPIO_FN_RMII_RXD1, NULL);
gpio_request(GPIO_FN_RMII_TXD0, NULL);
gpio_request(GPIO_FN_RMII_TXD1, NULL);
gpio_request(GPIO_FN_RMII_REF_CLK, NULL);
gpio_request(GPIO_FN_RMII_TX_EN, NULL);
gpio_request(GPIO_FN_RMII_RX_ER, NULL);
gpio_request(GPIO_FN_RMII_CRS_DV, NULL);
gpio_request(GPIO_FN_MDIO, NULL);
gpio_request(GPIO_FN_MDC, NULL);
gpio_request(GPIO_FN_LNKSTA, NULL);
/* enable USB */
__raw_writew(0x0000, 0xA4D80000);
__raw_writew(0x0000, 0xA4D90000);
gpio_request(GPIO_PTB3, NULL);
gpio_request(GPIO_PTB4, NULL);
gpio_request(GPIO_PTB5, NULL);
gpio_direction_input(GPIO_PTB3);
gpio_direction_output(GPIO_PTB4, 0);
gpio_direction_output(GPIO_PTB5, 0);
__raw_writew(0x0600, 0xa40501d4);
__raw_writew(0x0600, 0xa4050192);
if (gpio_get_value(GPIO_PTB3)) {
printk(KERN_INFO "USB1 function is selected\n");
usb1_common_device.name = "r8a66597_udc";
} else {
printk(KERN_INFO "USB1 host is selected\n");
usb1_common_device.name = "r8a66597_hcd";
}
/* enable LCDC */
gpio_request(GPIO_FN_LCDD23, NULL);
gpio_request(GPIO_FN_LCDD22, NULL);
gpio_request(GPIO_FN_LCDD21, NULL);
gpio_request(GPIO_FN_LCDD20, NULL);
gpio_request(GPIO_FN_LCDD19, NULL);
gpio_request(GPIO_FN_LCDD18, NULL);
gpio_request(GPIO_FN_LCDD17, NULL);
gpio_request(GPIO_FN_LCDD16, NULL);
gpio_request(GPIO_FN_LCDD15, NULL);
gpio_request(GPIO_FN_LCDD14, NULL);
gpio_request(GPIO_FN_LCDD13, NULL);
gpio_request(GPIO_FN_LCDD12, NULL);
gpio_request(GPIO_FN_LCDD11, NULL);
gpio_request(GPIO_FN_LCDD10, NULL);
gpio_request(GPIO_FN_LCDD9, NULL);
gpio_request(GPIO_FN_LCDD8, NULL);
gpio_request(GPIO_FN_LCDD7, NULL);
gpio_request(GPIO_FN_LCDD6, NULL);
gpio_request(GPIO_FN_LCDD5, NULL);
gpio_request(GPIO_FN_LCDD4, NULL);
gpio_request(GPIO_FN_LCDD3, NULL);
gpio_request(GPIO_FN_LCDD2, NULL);
gpio_request(GPIO_FN_LCDD1, NULL);
gpio_request(GPIO_FN_LCDD0, NULL);
gpio_request(GPIO_FN_LCDDISP, NULL);
gpio_request(GPIO_FN_LCDHSYN, NULL);
gpio_request(GPIO_FN_LCDDCK, NULL);
gpio_request(GPIO_FN_LCDVSYN, NULL);
gpio_request(GPIO_FN_LCDDON, NULL);
gpio_request(GPIO_FN_LCDLCLK, NULL);
__raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA);
gpio_request(GPIO_PTE6, NULL);
gpio_request(GPIO_PTU1, NULL);
gpio_request(GPIO_PTA2, NULL);
gpio_direction_input(GPIO_PTE6);
gpio_direction_output(GPIO_PTU1, 0);
gpio_direction_output(GPIO_PTA2, 0);
/* I/O buffer drive ability is high */
__raw_writew((__raw_readw(IODRIVEA) & ~0x00c0) | 0x0080 , IODRIVEA);
if (gpio_get_value(GPIO_PTE6)) {
/* DVI */
lcdc_info.clock_source = LCDC_CLK_EXTERNAL;
lcdc_info.ch[0].clock_divider = 1;
lcdc_info.ch[0].lcd_modes = ecovec_dvi_modes;
lcdc_info.ch[0].num_modes = ARRAY_SIZE(ecovec_dvi_modes);
/* No backlight */
gpio_backlight_data.fbdev = NULL;
gpio_set_value(GPIO_PTA2, 1);
gpio_set_value(GPIO_PTU1, 1);
} else {
/* Panel */
lcdc_info.clock_source = LCDC_CLK_PERIPHERAL;
lcdc_info.ch[0].clock_divider = 2;
lcdc_info.ch[0].lcd_modes = ecovec_lcd_modes;
lcdc_info.ch[0].num_modes = ARRAY_SIZE(ecovec_lcd_modes);
/* FIXME
*
* LCDDON control is needed for Panel,
* but current sh_mobile_lcdc driver doesn't control it.
* It is temporary correspondence
*/
gpio_request(GPIO_PTF4, NULL);
gpio_direction_output(GPIO_PTF4, 1);
/* enable TouchScreen */
i2c_register_board_info(0, &ts_i2c_clients, 1);
irq_set_irq_type(IRQ0, IRQ_TYPE_LEVEL_LOW);
}
/* enable CEU0 */
gpio_request(GPIO_FN_VIO0_D15, NULL);
gpio_request(GPIO_FN_VIO0_D14, NULL);
gpio_request(GPIO_FN_VIO0_D13, NULL);
gpio_request(GPIO_FN_VIO0_D12, NULL);
gpio_request(GPIO_FN_VIO0_D11, NULL);
gpio_request(GPIO_FN_VIO0_D10, NULL);
gpio_request(GPIO_FN_VIO0_D9, NULL);
gpio_request(GPIO_FN_VIO0_D8, NULL);
gpio_request(GPIO_FN_VIO0_D7, NULL);
gpio_request(GPIO_FN_VIO0_D6, NULL);
gpio_request(GPIO_FN_VIO0_D5, NULL);
gpio_request(GPIO_FN_VIO0_D4, NULL);
gpio_request(GPIO_FN_VIO0_D3, NULL);
gpio_request(GPIO_FN_VIO0_D2, NULL);
gpio_request(GPIO_FN_VIO0_D1, NULL);
gpio_request(GPIO_FN_VIO0_D0, NULL);
gpio_request(GPIO_FN_VIO0_VD, NULL);
gpio_request(GPIO_FN_VIO0_CLK, NULL);
gpio_request(GPIO_FN_VIO0_FLD, NULL);
gpio_request(GPIO_FN_VIO0_HD, NULL);
/* enable CEU1 */
gpio_request(GPIO_FN_VIO1_D7, NULL);
gpio_request(GPIO_FN_VIO1_D6, NULL);
gpio_request(GPIO_FN_VIO1_D5, NULL);
gpio_request(GPIO_FN_VIO1_D4, NULL);
gpio_request(GPIO_FN_VIO1_D3, NULL);
gpio_request(GPIO_FN_VIO1_D2, NULL);
gpio_request(GPIO_FN_VIO1_D1, NULL);
gpio_request(GPIO_FN_VIO1_D0, NULL);
gpio_request(GPIO_FN_VIO1_FLD, NULL);
gpio_request(GPIO_FN_VIO1_HD, NULL);
gpio_request(GPIO_FN_VIO1_VD, NULL);
gpio_request(GPIO_FN_VIO1_CLK, NULL);
/* enable KEYSC */
gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
gpio_request(GPIO_FN_KEYOUT3, NULL);
gpio_request(GPIO_FN_KEYOUT2, NULL);
gpio_request(GPIO_FN_KEYOUT1, NULL);
gpio_request(GPIO_FN_KEYOUT0, NULL);
gpio_request(GPIO_FN_KEYIN0, NULL);
/* enable user debug switch */
gpio_request(GPIO_PTR0, NULL);
gpio_request(GPIO_PTR4, NULL);
gpio_request(GPIO_PTR5, NULL);
gpio_request(GPIO_PTR6, NULL);
gpio_direction_input(GPIO_PTR0);
gpio_direction_input(GPIO_PTR4);
gpio_direction_input(GPIO_PTR5);
gpio_direction_input(GPIO_PTR6);
/* SD-card slot CN11 */
#if defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
/* enable SDHI0 on CN11 (needs DS2.4 set to ON) */
gpio_request(GPIO_FN_SDHI0WP, NULL);
gpio_request(GPIO_FN_SDHI0CMD, NULL);
gpio_request(GPIO_FN_SDHI0CLK, NULL);
gpio_request(GPIO_FN_SDHI0D3, NULL);
gpio_request(GPIO_FN_SDHI0D2, NULL);
gpio_request(GPIO_FN_SDHI0D1, NULL);
gpio_request(GPIO_FN_SDHI0D0, NULL);
#else
/* enable MSIOF0 on CN11 (needs DS2.4 set to OFF) */
gpio_request(GPIO_FN_MSIOF0_TXD, NULL);
gpio_request(GPIO_FN_MSIOF0_RXD, NULL);
gpio_request(GPIO_FN_MSIOF0_TSCK, NULL);
gpio_request(GPIO_PTM4, NULL); /* software CS control of TSYNC pin */
gpio_direction_output(GPIO_PTM4, 1); /* active low CS */
gpio_request(GPIO_PTB6, NULL); /* 3.3V power control */
gpio_direction_output(GPIO_PTB6, 0); /* disable power by default */
spi_register_board_info(spi_bus, ARRAY_SIZE(spi_bus));
#endif
/* MMC/SD-card slot CN12 */
#if defined(CONFIG_MMC_SH_MMCIF) || defined(CONFIG_MMC_SH_MMCIF_MODULE)
/* enable MMCIF (needs DS2.6,7 set to OFF,ON) */
gpio_request(GPIO_FN_MMC_D7, NULL);
gpio_request(GPIO_FN_MMC_D6, NULL);
gpio_request(GPIO_FN_MMC_D5, NULL);
gpio_request(GPIO_FN_MMC_D4, NULL);
gpio_request(GPIO_FN_MMC_D3, NULL);
gpio_request(GPIO_FN_MMC_D2, NULL);
gpio_request(GPIO_FN_MMC_D1, NULL);
gpio_request(GPIO_FN_MMC_D0, NULL);
gpio_request(GPIO_FN_MMC_CLK, NULL);
gpio_request(GPIO_FN_MMC_CMD, NULL);
cn12_enabled = true;
#elif defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
/* enable SDHI1 on CN12 (needs DS2.6,7 set to ON,OFF) */
gpio_request(GPIO_FN_SDHI1WP, NULL);
gpio_request(GPIO_FN_SDHI1CMD, NULL);
gpio_request(GPIO_FN_SDHI1CLK, NULL);
gpio_request(GPIO_FN_SDHI1D3, NULL);
gpio_request(GPIO_FN_SDHI1D2, NULL);
gpio_request(GPIO_FN_SDHI1D1, NULL);
gpio_request(GPIO_FN_SDHI1D0, NULL);
cn12_enabled = true;
#endif
if (cn12_enabled)
/* I/O buffer drive ability is high for CN12 */
__raw_writew((__raw_readw(IODRIVEA) & ~0x3000) | 0x2000,
IODRIVEA);
/* enable FSI */
gpio_request(GPIO_FN_FSIMCKB, NULL);
gpio_request(GPIO_FN_FSIIBSD, NULL);
gpio_request(GPIO_FN_FSIOBSD, NULL);
gpio_request(GPIO_FN_FSIIBBCK, NULL);
gpio_request(GPIO_FN_FSIIBLRCK, NULL);
gpio_request(GPIO_FN_FSIOBBCK, NULL);
gpio_request(GPIO_FN_FSIOBLRCK, NULL);
gpio_request(GPIO_FN_CLKAUDIOBO, NULL);
/* set SPU2 clock to 83.4 MHz */
clk = clk_get(NULL, "spu_clk");
if (!IS_ERR(clk)) {
clk_set_rate(clk, clk_round_rate(clk, 83333333));
clk_put(clk);
}
/* change parent of FSI B */
clk = clk_get(NULL, "fsib_clk");
if (!IS_ERR(clk)) {
/* 48kHz dummy clock was used to make sure 1/1 divide */
clk_set_rate(&sh7724_fsimckb_clk, 48000);
clk_set_parent(clk, &sh7724_fsimckb_clk);
clk_set_rate(clk, 48000);
clk_put(clk);
}
gpio_request(GPIO_PTU0, NULL);
gpio_direction_output(GPIO_PTU0, 0);
mdelay(20);
/* enable motion sensor */
gpio_request(GPIO_FN_INTC_IRQ1, NULL);
gpio_direction_input(GPIO_FN_INTC_IRQ1);
/* set VPU clock to 166 MHz */
clk = clk_get(NULL, "vpu_clk");
if (!IS_ERR(clk)) {
clk_set_rate(clk, clk_round_rate(clk, 166000000));
clk_put(clk);
}
/* enable IrDA */
gpio_request(GPIO_FN_IRDA_OUT, NULL);
gpio_request(GPIO_FN_IRDA_IN, NULL);
gpio_request(GPIO_PTU5, NULL);
gpio_direction_output(GPIO_PTU5, 0);
/* Register gpio lookup tables for cameras and video decoder */
gpiod_add_lookup_table(&tw9910_gpios);
gpiod_add_lookup_table(&mt9t112_0_gpios);
gpiod_add_lookup_table(&mt9t112_1_gpios);
/* enable I2C device */
i2c_register_board_info(0, i2c0_devices,
ARRAY_SIZE(i2c0_devices));
i2c_register_board_info(1, i2c1_devices,
ARRAY_SIZE(i2c1_devices));
#if defined(CONFIG_VIDEO_SH_VOU) || defined(CONFIG_VIDEO_SH_VOU_MODULE)
/* VOU */
gpio_request(GPIO_FN_DV_D15, NULL);
gpio_request(GPIO_FN_DV_D14, NULL);
gpio_request(GPIO_FN_DV_D13, NULL);
gpio_request(GPIO_FN_DV_D12, NULL);
gpio_request(GPIO_FN_DV_D11, NULL);
gpio_request(GPIO_FN_DV_D10, NULL);
gpio_request(GPIO_FN_DV_D9, NULL);
gpio_request(GPIO_FN_DV_D8, NULL);
gpio_request(GPIO_FN_DV_CLKI, NULL);
gpio_request(GPIO_FN_DV_CLK, NULL);
gpio_request(GPIO_FN_DV_VSYNC, NULL);
gpio_request(GPIO_FN_DV_HSYNC, NULL);
/* AK8813 power / reset sequence */
gpio_request(GPIO_PTG4, NULL);
gpio_request(GPIO_PTU3, NULL);
/* Reset */
gpio_direction_output(GPIO_PTG4, 0);
/* Power down */
gpio_direction_output(GPIO_PTU3, 1);
udelay(10);
/* Power up, reset */
gpio_set_value(GPIO_PTU3, 0);
udelay(10);
/* Remove reset */
gpio_set_value(GPIO_PTG4, 1);
#endif
/* Initialize CEU platform devices separately to map memory first */
device_initialize(&ecovec_ceu_devices[0]->dev);
arch_setup_pdev_archdata(ecovec_ceu_devices[0]);
dma_declare_coherent_memory(&ecovec_ceu_devices[0]->dev,
ceu0_dma_membase, ceu0_dma_membase,
ceu0_dma_membase +
CEU_BUFFER_MEMORY_SIZE - 1,
DMA_MEMORY_EXCLUSIVE);
platform_device_add(ecovec_ceu_devices[0]);
device_initialize(&ecovec_ceu_devices[1]->dev);
arch_setup_pdev_archdata(ecovec_ceu_devices[1]);
dma_declare_coherent_memory(&ecovec_ceu_devices[1]->dev,
ceu1_dma_membase, ceu1_dma_membase,
ceu1_dma_membase +
CEU_BUFFER_MEMORY_SIZE - 1,
DMA_MEMORY_EXCLUSIVE);
platform_device_add(ecovec_ceu_devices[1]);
gpiod_add_lookup_table(&cn12_power_gpiod_table);
#if defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
gpiod_add_lookup_table(&sdhi0_power_gpiod_table);
#endif
return platform_add_devices(ecovec_devices,
ARRAY_SIZE(ecovec_devices));
}
/* Exynos5260 */
int exynos5260_fimc_is_cfg_clk(struct platform_device *pdev)
{
/* top */
struct clk *sclk_bustop_pll = NULL;
struct clk *mout_isp1_media_266 = NULL;
struct clk *sclk_memtop_pll = NULL;
/* isp */
struct clk *aclk_isp_266 = NULL;
struct clk *aclk_isp_266_user = NULL;
struct clk *pclk_isp_133 = NULL;
struct clk *pclk_isp_66 = NULL;
struct clk *sclk_mpwm_isp = NULL;
/* mcuctl */
struct clk *aclk_isp_400 = NULL;
struct clk *aclk_ca5_clkin = NULL;
struct clk *aclk_ca5_atclkin = NULL;
struct clk *pclk_ca5_pclkdbg = NULL;
#ifdef USE_UART_DEBUG
struct clk *sclk_uart_isp = NULL;
struct clk *sclk_uart_isp_div = NULL;
unsigned long isp_uart;
#endif
pr_info("%s\n", __func__);
/* 0. TOP */
sclk_memtop_pll = clk_get(&pdev->dev, "sclk_memtop_pll");
if (IS_ERR(sclk_memtop_pll))
return PTR_ERR(sclk_memtop_pll);
mout_isp1_media_266 = clk_get(&pdev->dev, "mout_isp1_media_266");
if (IS_ERR(mout_isp1_media_266)) {
clk_put(sclk_memtop_pll);
return PTR_ERR(mout_isp1_media_266);
}
aclk_isp_266 = clk_get(&pdev->dev, "aclk_isp_266");
if (IS_ERR(aclk_isp_266)) {
clk_put(sclk_memtop_pll);
clk_put(mout_isp1_media_266);
return PTR_ERR(aclk_isp_266);
}
clk_set_parent(mout_isp1_media_266, sclk_memtop_pll);
clk_set_parent(aclk_isp_266, mout_isp1_media_266);
clk_set_rate(aclk_isp_266, 300 * 1000000);
clk_put(sclk_memtop_pll);
clk_put(mout_isp1_media_266);
sclk_bustop_pll = clk_get(&pdev->dev, "sclk_bustop_pll");
if (IS_ERR(sclk_bustop_pll))
return PTR_ERR(sclk_bustop_pll);
aclk_isp_400 = clk_get(&pdev->dev, "aclk_isp_400");
if (IS_ERR(aclk_isp_400)) {
clk_put(sclk_bustop_pll);
return PTR_ERR(aclk_isp_400);
}
clk_set_parent(aclk_isp_400, sclk_bustop_pll);
clk_set_rate(aclk_isp_400, 400 * 1000000);
/* 1. MCUISP: aclk_isp_400 */
aclk_ca5_clkin = clk_get(&pdev->dev, "aclk_ca5_clkin");
if (IS_ERR(aclk_ca5_clkin)) {
clk_put(aclk_isp_400);
return PTR_ERR(aclk_ca5_clkin);
}
aclk_ca5_atclkin = clk_get(&pdev->dev, "aclk_ca5_atclkin");
if (IS_ERR(aclk_ca5_atclkin)) {
clk_put(aclk_isp_400);
clk_put(aclk_ca5_clkin);
return PTR_ERR(aclk_ca5_atclkin);
}
pclk_ca5_pclkdbg = clk_get(&pdev->dev, "pclk_ca5_pclkdbg");
if (IS_ERR(pclk_ca5_pclkdbg)) {
clk_put(aclk_isp_400);
clk_put(aclk_ca5_clkin);
clk_put(aclk_ca5_atclkin);
return PTR_ERR(pclk_ca5_pclkdbg);
}
clk_set_parent(aclk_ca5_clkin, aclk_isp_400);
clk_set_rate(aclk_ca5_atclkin, 200 * 1000000);
clk_set_rate(pclk_ca5_pclkdbg, 100 * 1000000);
clk_put(aclk_isp_400);
clk_put(aclk_ca5_clkin);
clk_put(aclk_ca5_atclkin);
clk_put(pclk_ca5_pclkdbg);
/* 2. ACLK_ISP: aclk_isp_266 */
aclk_isp_266_user = clk_get(&pdev->dev, "aclk_isp_266_user");
if (IS_ERR(aclk_isp_266_user)) {
clk_put(aclk_isp_266);
return PTR_ERR(aclk_isp_266_user);
}
pclk_isp_133 = clk_get(&pdev->dev, "pclk_isp_133");
if (IS_ERR(pclk_isp_133)) {
clk_put(aclk_isp_266);
clk_put(aclk_isp_266_user);
return PTR_ERR(pclk_isp_133);
}
pclk_isp_66 = clk_get(&pdev->dev, "pclk_isp_66");
if (IS_ERR(pclk_isp_66)) {
clk_put(aclk_isp_266);
clk_put(aclk_isp_266_user);
clk_put(pclk_isp_133);
return PTR_ERR(pclk_isp_66);
}
sclk_mpwm_isp = clk_get(&pdev->dev, "sclk_mpwm_isp");
if (IS_ERR(sclk_mpwm_isp)) {
clk_put(aclk_isp_266);
clk_put(aclk_isp_266_user);
clk_put(pclk_isp_133);
clk_put(pclk_isp_66);
return PTR_ERR(sclk_mpwm_isp);
}
clk_set_parent(aclk_isp_266_user, aclk_isp_266);
clk_set_rate(pclk_isp_133 , 150 * 1000000);
clk_set_rate(pclk_isp_66 , 75 * 1000000);
clk_set_rate(sclk_mpwm_isp, 75 * 1000000);
clk_put(aclk_isp_266);
clk_put(aclk_isp_266_user);
clk_put(pclk_isp_133);
clk_put(pclk_isp_66);
clk_put(sclk_mpwm_isp);
return 0;
}
static int
kbase_devfreq_target(struct device *dev, unsigned long *target_freq, u32 flags)
{
struct kbase_device *kbdev = dev_get_drvdata(dev);
struct dev_pm_opp *opp;
unsigned long freq = 0;
unsigned long voltage;
int err;
freq = *target_freq;
rcu_read_lock();
opp = devfreq_recommended_opp(dev, &freq, flags);
voltage = dev_pm_opp_get_voltage(opp);
rcu_read_unlock();
if (IS_ERR_OR_NULL(opp)) {
dev_err(dev, "Failed to get opp (%ld)\n", PTR_ERR(opp));
return PTR_ERR(opp);
}
/*
* Only update if there is a change of frequency
*/
if (kbdev->current_freq == freq) {
*target_freq = freq;
return 0;
}
#ifdef CONFIG_REGULATOR
if (kbdev->regulator && kbdev->current_voltage != voltage
&& kbdev->current_freq < freq) {
err = regulator_set_voltage(kbdev->regulator, voltage, voltage);
if (err) {
dev_err(dev, "Failed to increase voltage (%d)\n", err);
return err;
}
}
#endif
err = clk_set_rate(kbdev->clock, freq);
if (err) {
dev_err(dev, "Failed to set clock %lu (target %lu)\n",
freq, *target_freq);
return err;
}
#ifdef CONFIG_REGULATOR
if (kbdev->regulator && kbdev->current_voltage != voltage
&& kbdev->current_freq > freq) {
err = regulator_set_voltage(kbdev->regulator, voltage, voltage);
if (err) {
dev_err(dev, "Failed to decrease voltage (%d)\n", err);
return err;
}
}
#endif
*target_freq = freq;
kbdev->current_voltage = voltage;
kbdev->current_freq = freq;
kbase_pm_reset_dvfs_utilisation(kbdev);
return err;
}
int exynos3470_fimc_is_cfg_clk(struct platform_device *pdev)
{
int ret = 0;
struct clk *sclk_vpll = NULL;
struct clk *mout_mpll = NULL;
struct clk *pre_aclk_400_mcuisp = NULL;
struct clk *aclk_400_mcuisp = NULL;
struct clk *aclk_400_mcuisp_div0 = NULL;
struct clk *aclk_400_mcuisp_div1 = NULL;
struct clk *pre_aclk_266 = NULL;
struct clk *aclk_266 = NULL;
struct clk *aclk_266_div0 = NULL;
struct clk *aclk_266_div1 = NULL;
struct clk *aclk_266_div2 = NULL;
#ifdef USE_UART_DEBUG
struct clk *sclk_uart_isp = NULL;
#endif
pr_debug("(%s) ++++\n", __func__);
/* VPLL should be lock to 900 MHz before configuring clock.
* Because ISP PLL is shared with G3D.
*/
ret = mali_dvfs_level_lock();
if (ret < 0) {
pr_err("mali_dvfs_level_lock was fail(%d)\n", ret);
return -EINVAL;
}
/* 1. MCUISP */
mout_mpll = clk_get(&pdev->dev, "mout_mpll");
if (IS_ERR(mout_mpll)) {
pr_err("fail to get 'mout_mpll'\n");
return PTR_ERR(mout_mpll);
}
pre_aclk_400_mcuisp = clk_get(&pdev->dev, "pre_aclk_400_mcuisp");
if (IS_ERR(pre_aclk_400_mcuisp)) {
clk_put(mout_mpll);
pr_err("fail to get 'pre_aclk_400_mcuisp'\n");
return PTR_ERR(pre_aclk_400_mcuisp);
}
clk_set_parent(pre_aclk_400_mcuisp, mout_mpll);
clk_set_rate(pre_aclk_400_mcuisp, 400 * 1000000);
aclk_400_mcuisp = clk_get(&pdev->dev, "aclk_400_mcuisp");
if (IS_ERR(aclk_400_mcuisp)) {
clk_put(mout_mpll);
clk_put(pre_aclk_400_mcuisp);
pr_err("fail to get 'aclk_400_mcuisp'\n");
return PTR_ERR(aclk_400_mcuisp);
}
clk_set_parent(aclk_400_mcuisp, pre_aclk_400_mcuisp);
aclk_400_mcuisp_div0 = clk_get(&pdev->dev, "aclk_400_mcuisp_div0");
if (IS_ERR(aclk_400_mcuisp_div0)) {
clk_put(mout_mpll);
clk_put(pre_aclk_400_mcuisp);
clk_put(aclk_400_mcuisp);
pr_err("fail to get 'aclk_400_mcuisp_div0'\n");
return PTR_ERR(aclk_400_mcuisp_div0);
}
clk_set_rate(aclk_400_mcuisp_div0, 200 * 1000000);
aclk_400_mcuisp_div1 = clk_get(&pdev->dev, "aclk_400_mcuisp_div1");
if (IS_ERR(aclk_400_mcuisp_div1)) {
clk_put(mout_mpll);
clk_put(pre_aclk_400_mcuisp);
clk_put(aclk_400_mcuisp);
clk_put(aclk_400_mcuisp_div0);
pr_err("fail to get 'aclk_400_mcuisp_div1'\n");
return PTR_ERR(aclk_400_mcuisp_div1);
}
clk_set_rate(aclk_400_mcuisp_div1, 100 * 1000000);
pr_info("aclk_400_mcuisp : %ld\n", clk_get_rate(aclk_400_mcuisp));
pr_info("aclk_400_mcuisp_div0 : %ld\n", clk_get_rate(aclk_400_mcuisp_div0));
pr_info("aclk_400_mcuisp_div1 : %ld\n", clk_get_rate(aclk_400_mcuisp_div1));
clk_put(mout_mpll);
clk_put(pre_aclk_400_mcuisp);
clk_put(aclk_400_mcuisp);
clk_put(aclk_400_mcuisp_div0);
clk_put(aclk_400_mcuisp_div1);
/* 2. ACLK_ISP */
sclk_vpll = clk_get(&pdev->dev, "sclk_vpll");
if (IS_ERR(sclk_vpll)) {
pr_err("fail to get 'sclk_vpll'\n");
return PTR_ERR(sclk_vpll);
}
pre_aclk_266 = clk_get(&pdev->dev, "pre_aclk_266");
if (IS_ERR(pre_aclk_266)) {
clk_put(sclk_vpll);
pr_err("fail to get 'pre_aclk_266'\n");
return PTR_ERR(pre_aclk_266);
}
clk_set_parent(pre_aclk_266, sclk_vpll);
clk_set_rate(pre_aclk_266, 300 * 1000000);
aclk_266 = clk_get(&pdev->dev, "aclk_266");
if (IS_ERR(aclk_266)) {
clk_put(sclk_vpll);
clk_put(pre_aclk_266);
pr_err("fail to get 'aclk_266'\n");
return PTR_ERR(aclk_266);
}
clk_set_parent(aclk_266, pre_aclk_266);
aclk_266_div0 = clk_get(&pdev->dev, "aclk_266_div0");
if (IS_ERR(aclk_266_div0)) {
clk_put(sclk_vpll);
clk_put(pre_aclk_266);
clk_put(aclk_266);
pr_err("fail to get 'aclk_266_div0'\n");
return PTR_ERR(aclk_266_div0);
}
clk_set_rate(aclk_266_div0, 150 * 1000000);
aclk_266_div1 = clk_get(&pdev->dev, "aclk_266_div1");
if (IS_ERR(aclk_266_div1)) {
clk_put(sclk_vpll);
clk_put(pre_aclk_266);
clk_put(aclk_266);
clk_put(aclk_266_div0);
pr_err("fail to get 'aclk_266_div1'\n");
return PTR_ERR(aclk_266_div1);
}
clk_set_rate(aclk_266_div1, 75 * 1000000);
aclk_266_div2 = clk_get(&pdev->dev, "aclk_266_div2");
if (IS_ERR(aclk_266_div2)) {
clk_put(sclk_vpll);
clk_put(pre_aclk_266);
clk_put(aclk_266);
clk_put(aclk_266_div0);
clk_put(aclk_266_div1);
pr_err("fail to get 'aclk_266_div2'\n");
return PTR_ERR(aclk_266_div2);
}
clk_set_rate(aclk_266_div2, 75 * 1000000);
pr_info("aclk_266 : %ld\n", clk_get_rate(aclk_266));
pr_info("aclk_266_div0 : %ld\n", clk_get_rate(aclk_266_div0));
pr_info("aclk_266_div1 : %ld\n", clk_get_rate(aclk_266_div1));
pr_info("aclk_266_div2 : %ld\n", clk_get_rate(aclk_266_div2));
clk_put(sclk_vpll);
clk_put(pre_aclk_266);
clk_put(aclk_266);
clk_put(aclk_266_div0);
clk_put(aclk_266_div1);
clk_put(aclk_266_div2);
#ifdef USE_UART_DEBUG
/* 3. UART-ISP */
/* change special clock source to mout_mpll_user_top */
mout_mpll = clk_get(&pdev->dev, "mout_mpll_user_top");
if (IS_ERR(mout_mpll)) {
pr_err("fail to get 'mout_mpll_user_top'\n");
return PTR_ERR(mout_mpll);
}
sclk_uart_isp = clk_get(&pdev->dev, "sclk_uart_isp");
if (IS_ERR(sclk_uart_isp)) {
clk_put(mout_mpll);
pr_err("fail to get 'sclk_uart_isp'\n");
return PTR_ERR(sclk_uart_isp);
}
clk_set_parent(sclk_uart_isp, mout_mpll);
clk_set_rate(sclk_uart_isp, 50 * 1000000);
pr_debug("sclk_uart_isp : %ld\n", clk_get_rate(sclk_uart_isp));
clk_put(mout_mpll);
clk_put(sclk_uart_isp);
#endif
pr_debug("(%s) ----\n", __func__);
return 0;
}
int __init mx23_clocks_init(void __iomem *regs)
{
clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000);
clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000);
clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll", FRAC, 0);
clks[ref_emi] = mxs_clk_ref("ref_emi", "pll", FRAC, 1);
clks[ref_pix] = mxs_clk_ref("ref_pix", "pll", FRAC, 2);
clks[ref_io] = mxs_clk_ref("ref_io", "pll", FRAC, 3);
clks[saif_sel] = mxs_clk_mux("saif_sel", CLKSEQ, 0, 1, sel_pll, ARRAY_SIZE(sel_pll));
clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 1, 1, sel_pix, ARRAY_SIZE(sel_pix));
clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 4, 1, sel_io, ARRAY_SIZE(sel_io));
clks[ssp_sel] = mxs_clk_mux("ssp_sel", CLKSEQ, 5, 1, sel_io, ARRAY_SIZE(sel_io));
clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 6, 1, emi_sels, ARRAY_SIZE(emi_sels));
clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 7, 1, cpu_sels, ARRAY_SIZE(cpu_sels));
clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu));
clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28);
clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29);
clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 29);
clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31);
clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", PIX, 0, 12, 29);
clks[ssp_div] = mxs_clk_div("ssp_div", "ssp_sel", SSP, 0, 9, 29);
clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29);
clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28);
clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29);
clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 6, 29);
clks[saif_div] = mxs_clk_frac("saif_div", "saif_sel", SAIF, 0, 16, 29);
clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750);
clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768);
clks[adc] = mxs_clk_fixed_factor("adc", "clk32k", 1, 16);
clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll", 1, 4);
clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26);
clks[dri] = mxs_clk_gate("dri", "ref_xtal", XTAL, 28);
clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29);
clks[filt] = mxs_clk_gate("filt", "ref_xtal", XTAL, 30);
clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31);
clks[ssp] = mxs_clk_gate("ssp", "ssp_div", SSP, 31);
clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31);
clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31);
clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31);
clks[saif] = mxs_clk_gate("saif", "saif_div", SAIF, 31);
clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", PIX, 31);
clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31);
clks[lcdif_comp] = mxs_clk_lcdif("lcdif_comp", clks[ref_pix],
clks[lcdif_div], clks[lcdif]);
clk_set_rate(clks[ref_io], 480000000);
clk_set_parent(clks[ssp_sel], clks[ref_io]);
clk_set_rate(clks[ssp_div], 96000000);
clk_set_parent(clks[lcdif_sel], clks[ref_pix]);
clkdev_add_physbase(clks[ssp], IMX_SSP1_BASE, NULL);
clkdev_add_physbase(clks[ssp], IMX_SSP2_BASE, NULL);
clkdev_add_physbase(clks[xbus], IMX_DBGUART_BASE, NULL);
clkdev_add_physbase(clks[hbus], IMX_OCOTP_BASE, NULL);
clkdev_add_physbase(clks[uart], IMX_UART1_BASE, NULL);
clkdev_add_physbase(clks[uart], IMX_UART2_BASE, NULL);
clkdev_add_physbase(clks[gpmi], MXS_GPMI_BASE, NULL);
if (IS_ENABLED(CONFIG_DRIVER_VIDEO_STM))
clkdev_add_physbase(clks[lcdif_comp], IMX_FB_BASE, NULL);
return 0;
}
static int s3c_camif_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct s3c_camif_plat_data *pdata = dev->platform_data;
struct s3c_camif_drvdata *drvdata;
struct camif_dev *camif;
struct resource *mres;
int ret = 0;
camif = devm_kzalloc(dev, sizeof(*camif), GFP_KERNEL);
if (!camif)
return -ENOMEM;
spin_lock_init(&camif->slock);
mutex_init(&camif->lock);
camif->dev = dev;
if (!pdata || !pdata->gpio_get || !pdata->gpio_put) {
dev_err(dev, "wrong platform data\n");
return -EINVAL;
}
camif->pdata = *pdata;
drvdata = (void *)platform_get_device_id(pdev)->driver_data;
camif->variant = drvdata->variant;
mres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
camif->io_base = devm_ioremap_resource(dev, mres);
if (IS_ERR(camif->io_base))
return PTR_ERR(camif->io_base);
ret = camif_request_irqs(pdev, camif);
if (ret < 0)
return ret;
ret = pdata->gpio_get();
if (ret < 0)
return ret;
ret = s3c_camif_create_subdev(camif);
if (ret < 0)
goto err_sd;
ret = camif_clk_get(camif);
if (ret < 0)
goto err_clk;
platform_set_drvdata(pdev, camif);
clk_set_rate(camif->clock[CLK_CAM],
camif->pdata.sensor.clock_frequency);
dev_info(dev, "sensor clock frequency: %lu\n",
clk_get_rate(camif->clock[CLK_CAM]));
/*
* Set initial pixel format, resolution and crop rectangle.
* Must be done before a sensor subdev is registered as some
* settings are overrode with values from sensor subdev.
*/
s3c_camif_set_defaults(camif);
pm_runtime_enable(dev);
ret = pm_runtime_get_sync(dev);
if (ret < 0)
goto err_pm;
/* Initialize contiguous memory allocator */
camif->alloc_ctx = vb2_dma_contig_init_ctx(dev);
if (IS_ERR(camif->alloc_ctx)) {
ret = PTR_ERR(camif->alloc_ctx);
goto err_alloc;
}
ret = camif_media_dev_init(camif);
if (ret < 0)
goto err_mdev;
ret = camif_register_sensor(camif);
if (ret < 0)
goto err_sens;
ret = v4l2_device_register_subdev(&camif->v4l2_dev, &camif->subdev);
if (ret < 0)
goto err_sens;
mutex_lock(&camif->media_dev.graph_mutex);
ret = v4l2_device_register_subdev_nodes(&camif->v4l2_dev);
if (ret < 0)
goto err_unlock;
ret = camif_register_video_nodes(camif);
if (ret < 0)
goto err_unlock;
ret = camif_create_media_links(camif);
if (ret < 0)
goto err_unlock;
mutex_unlock(&camif->media_dev.graph_mutex);
ret = media_device_register(&camif->media_dev);
if (ret < 0)
goto err_sens;
pm_runtime_put(dev);
return 0;
err_unlock:
mutex_unlock(&camif->media_dev.graph_mutex);
err_sens:
v4l2_device_unregister(&camif->v4l2_dev);
media_device_unregister(&camif->media_dev);
media_device_cleanup(&camif->media_dev);
camif_unregister_media_entities(camif);
err_mdev:
vb2_dma_contig_cleanup_ctx(camif->alloc_ctx);
err_alloc:
pm_runtime_put(dev);
pm_runtime_disable(dev);
err_pm:
camif_clk_put(camif);
err_clk:
s3c_camif_unregister_subdev(camif);
err_sd:
pdata->gpio_put();
return ret;
}
int msm_cam_clk_enable(struct device *dev, struct msm_cam_clk_info *clk_info,
struct clk **clk_ptr, int num_clk, int enable)
{
int i;
int rc = 0;
if (enable) {
for (i = 0; i < num_clk; i++) {
clk_ptr[i] = clk_get(dev, clk_info[i].clk_name);
if (IS_ERR(clk_ptr[i])) {
pr_err("%s get failed\n", clk_info[i].clk_name);
rc = PTR_ERR(clk_ptr[i]);
goto cam_clk_get_err;
}
if (clk_info[i].clk_rate >= 0) {
rc = clk_set_rate(clk_ptr[i],
clk_info[i].clk_rate);
if (rc < 0) {
pr_err("%s set failed\n",
clk_info[i].clk_name);
goto cam_clk_set_err;
}
}
rc = clk_prepare(clk_ptr[i]);
if (rc < 0) {
pr_err("%s prepare failed\n",
clk_info[i].clk_name);
goto cam_clk_prepare_err;
}
rc = clk_enable(clk_ptr[i]);
if (rc < 0) {
pr_err("%s enable failed\n",
clk_info[i].clk_name);
goto cam_clk_enable_err;
}
}
} else {
for (i = num_clk - 1; i >= 0; i--) {
if (clk_ptr[i] != NULL) {
clk_disable(clk_ptr[i]);
clk_unprepare(clk_ptr[i]);
clk_put(clk_ptr[i]);
}
}
}
return rc;
cam_clk_enable_err:
clk_unprepare(clk_ptr[i]);
cam_clk_prepare_err:
cam_clk_set_err:
clk_put(clk_ptr[i]);
cam_clk_get_err:
for (i--; i >= 0; i--) {
if (clk_ptr[i] != NULL) {
clk_disable(clk_ptr[i]);
clk_unprepare(clk_ptr[i]);
clk_put(clk_ptr[i]);
}
}
return rc;
}
_mali_osk_errcode_t mali_platform_init(_mali_osk_resource_t *resource)
{
unsigned long rate;
int clk_div;
int mali_used = 0;
//get mali ahb clock
h_ahb_mali = clk_get(NULL, "ahb_mali");
if(!h_ahb_mali){
MALI_PRINT(("try to get ahb mali clock failed!\n"));
}
//get mali clk
h_mali_clk = clk_get(NULL, "mali");
if(!h_mali_clk){
MALI_PRINT(("try to get mali clock failed!\n"));
}
h_ve_pll = clk_get(NULL, "ve_pll");
if(!h_ve_pll){
MALI_PRINT(("try to get ve pll clock failed!\n"));
}
//set mali parent clock
if(clk_set_parent(h_mali_clk, h_ve_pll)){
MALI_PRINT(("try to set mali clock source failed!\n"));
}
//set mali clock
rate = clk_get_rate(h_ve_pll);
if(!script_parser_fetch("mali_para", "mali_used", &mali_used, 1)) {
if (mali_used == 1) {
if (!script_parser_fetch("mali_para", "mali_clkdiv", &clk_div, 1)) {
if (clk_div > 0) {
pr_info("mali: use config clk_div %d\n", clk_div);
mali_clk_div = clk_div;
}
}
}
}
pr_info("mali: clk_div %d\n", mali_clk_div);
rate /= mali_clk_div;
if(clk_set_rate(h_mali_clk, rate)){
MALI_PRINT(("try to set mali clock failed!\n"));
}
if(clk_reset(h_mali_clk,0)){
MALI_PRINT(("try to reset release failed!\n"));
}
MALI_PRINT(("mali clock set completed, clock is %d Mhz\n", rate));
#if USING_MALI_PMM
if( resource == NULL )
{
/* Nothing to set up for the system */
}
else if( resource->type == PMU )
{
if( (resource->base == 0) ||
(resource->description == NULL) )
{
/* NOTE: We currently don't care about any other resource settings */
MALI_PRINT_ERROR(("PLATFORM mali400-pmu: Missing PMU set up information\n"));
MALI_ERROR(_MALI_OSK_ERR_INVALID_ARGS);
}
MALI_DEBUG_ASSERT( pmu_info == NULL );
pmu_info = (platform_pmu_t *)_mali_osk_malloc(sizeof(*pmu_info));
MALI_CHECK_NON_NULL( pmu_info, _MALI_OSK_ERR_NOMEM );
/* All values get 0 as default */
_mali_osk_memset(pmu_info, 0, sizeof(*pmu_info));
pmu_info->reg_base_addr = resource->base;
pmu_info->reg_size = (u32)PMU_REGISTER_ADDRESS_SPACE_SIZE;
pmu_info->name = resource->description;
pmu_info->irq_num = resource->irq;
if( _MALI_OSK_ERR_OK != _mali_osk_mem_reqregion(pmu_info->reg_base_addr, pmu_info->reg_size, pmu_info->name) )
{
MALI_PRINT_ERROR(("PLATFORM mali400-pmu: Could not request register region (0x%08X - 0x%08X) for %s\n",
pmu_info->reg_base_addr, pmu_info->reg_base_addr + pmu_info->reg_size - 1, pmu_info->name));
goto cleanup;
}
else
{
MALI_DEBUG_PRINT( 4, ("PLATFORM mali400-pmu: Success: request_mem_region: (0x%08X - 0x%08X) for %s\n",
pmu_info->reg_base_addr, pmu_info->reg_base_addr + pmu_info->reg_size - 1, pmu_info->name));
}
pmu_info->reg_mapped = _mali_osk_mem_mapioregion( pmu_info->reg_base_addr, pmu_info->reg_size, pmu_info->name );
if( 0 == pmu_info->reg_mapped )
{
MALI_PRINT_ERROR(("PLATFORM mali400-pmu: Could not ioremap registers for %s .\n", pmu_info->name));
_mali_osk_mem_unreqregion( pmu_info->reg_base_addr, pmu_info->reg_size );
goto cleanup;
}
else
{
MALI_DEBUG_PRINT( 4, ("PLATFORM mali400-pmu: Success: ioremap_nocache: Internal ptr: (0x%08X - 0x%08X) for %s\n",
(u32) pmu_info->reg_mapped,
((u32)pmu_info->reg_mapped)+ pmu_info->reg_size - 1,
pmu_info->name));
}
MALI_DEBUG_PRINT( 4, ("PLATFORM mali400-pmu: Success: Mapping registers to %s\n", pmu_info->name));
#if PMU_TEST
pmu_test(pmu_info, (MALI_PMM_CORE_GP));
pmu_test(pmu_info, (MALI_PMM_CORE_GP|MALI_PMM_CORE_L2|MALI_PMM_CORE_PP0));
#endif
MALI_DEBUG_PRINT( 4, ("PLATFORM mali400-pmu: Initialized - %s\n", pmu_info->name) );
}
else
{
/* Didn't expect a different resource */
MALI_ERROR(_MALI_OSK_ERR_INVALID_ARGS);
}
MALI_SUCCESS;
cleanup:
_mali_osk_free(pmu_info);
pmu_info = NULL;
MALI_ERROR(_MALI_OSK_ERR_NOMEM);
#else
/* Nothing to do when not using PMM - as mali already on */
MALI_SUCCESS;
#endif
}
int exynos5_fimc_is_cfg_clk(struct platform_device *pdev)
{
struct clk *aclk_mcuisp = NULL;
struct clk *aclk_266 = NULL;
struct clk *aclk_mcuisp_div0 = NULL;
struct clk *aclk_mcuisp_div1 = NULL;
struct clk *aclk_266_div0 = NULL;
struct clk *aclk_266_div1 = NULL;
struct clk *aclk_266_mpwm = NULL;
struct clk *sclk_uart_isp = NULL;
struct clk *sclk_uart_isp_div = NULL;
struct clk *mout_mpll = NULL;
struct clk *sclk_mipi = NULL;
struct clk *cam_src = NULL;
struct clk *cam_A_clk = NULL;
unsigned long mcu_isp_400;
unsigned long isp_266;
unsigned long isp_uart;
unsigned long mipi;
unsigned long epll;
/*
* initialize Clocks
*/
printk(KERN_DEBUG "exynos5_fimc_is_cfg_clk\n");
/* 1. MCUISP */
aclk_mcuisp = clk_get(&pdev->dev, "aclk_400_isp");
if (IS_ERR(aclk_mcuisp))
return PTR_ERR(aclk_mcuisp);
aclk_mcuisp_div0 = clk_get(&pdev->dev, "aclk_400_isp_div0");
if (IS_ERR(aclk_mcuisp_div0))
return PTR_ERR(aclk_mcuisp_div0);
aclk_mcuisp_div1 = clk_get(&pdev->dev, "aclk_400_isp_div1");
if (IS_ERR(aclk_mcuisp_div1))
return PTR_ERR(aclk_mcuisp_div1);
clk_set_rate(aclk_mcuisp_div0, 400 * 1000000);
clk_set_rate(aclk_mcuisp_div1, 400 * 1000000);
mcu_isp_400 = clk_get_rate(aclk_mcuisp);
printk(KERN_DEBUG "mcu_isp_400 : %ld\n", mcu_isp_400);
mcu_isp_400 = clk_get_rate(aclk_mcuisp_div0);
printk(KERN_DEBUG "mcu_isp_400_div0 : %ld\n", mcu_isp_400);
mcu_isp_400 = clk_get_rate(aclk_mcuisp_div1);
printk(KERN_DEBUG "aclk_mcuisp_div1 : %ld\n", mcu_isp_400);
clk_put(aclk_mcuisp);
clk_put(aclk_mcuisp_div0);
clk_put(aclk_mcuisp_div1);
/* 2. ACLK_ISP */
aclk_266 = clk_get(&pdev->dev, "aclk_266_isp");
if (IS_ERR(aclk_266))
return PTR_ERR(aclk_266);
aclk_266_div0 = clk_get(&pdev->dev, "aclk_266_isp_div0");
if (IS_ERR(aclk_266_div0))
return PTR_ERR(aclk_266_div0);
aclk_266_div1 = clk_get(&pdev->dev, "aclk_266_isp_div1");
if (IS_ERR(aclk_266_div1))
return PTR_ERR(aclk_266_div1);
aclk_266_mpwm = clk_get(&pdev->dev, "aclk_266_isp_divmpwm");
if (IS_ERR(aclk_266_mpwm))
return PTR_ERR(aclk_266_mpwm);
clk_set_rate(aclk_266_div0, 134 * 1000000);
clk_set_rate(aclk_266_div1, 68 * 1000000);
isp_266 = clk_get_rate(aclk_266);
printk(KERN_DEBUG "isp_266 : %ld\n", isp_266);
isp_266 = clk_get_rate(aclk_266_div0);
printk(KERN_DEBUG "isp_266_div0 : %ld\n", isp_266);
isp_266 = clk_get_rate(aclk_266_div1);
printk(KERN_DEBUG "isp_266_div1 : %ld\n", isp_266);
isp_266 = clk_get_rate(aclk_266_mpwm);
printk(KERN_DEBUG "isp_266_mpwm : %ld\n", isp_266);
clk_put(aclk_266);
clk_put(aclk_266_div0);
clk_put(aclk_266_div1);
clk_put(aclk_266_mpwm);
/* 3. UART-ISP */
sclk_uart_isp = clk_get(&pdev->dev, "sclk_uart_src_isp");
if (IS_ERR(sclk_uart_isp))
return PTR_ERR(sclk_uart_isp);
sclk_uart_isp_div = clk_get(&pdev->dev, "sclk_uart_isp");
if (IS_ERR(sclk_uart_isp_div))
return PTR_ERR(sclk_uart_isp_div);
clk_set_parent(sclk_uart_isp_div, sclk_uart_isp);
clk_set_rate(sclk_uart_isp_div, 50 * 1000000);
isp_uart = clk_get_rate(sclk_uart_isp);
printk(KERN_DEBUG "isp_uart : %ld\n", isp_uart);
isp_uart = clk_get_rate(sclk_uart_isp_div);
printk(KERN_DEBUG "isp_uart_div : %ld\n", isp_uart);
clk_put(sclk_uart_isp);
clk_put(sclk_uart_isp_div);
/* MIPI-CSI */
mout_mpll = clk_get(&pdev->dev, "mout_mpll_user");
if (IS_ERR(mout_mpll))
return PTR_ERR(mout_mpll);
sclk_mipi = clk_get(&pdev->dev, "sclk_gscl_wrap");
if (IS_ERR(sclk_mipi))
return PTR_ERR(sclk_mipi);
clk_set_parent(sclk_mipi, mout_mpll);
clk_set_rate(sclk_mipi, 266 * 1000000);
mipi = clk_get_rate(mout_mpll);
printk(KERN_DEBUG "mipi_src : %ld\n", mipi);
mipi = clk_get_rate(sclk_mipi);
printk(KERN_DEBUG "mipi_div : %ld\n", mipi);
clk_put(mout_mpll);
clk_put(sclk_mipi);
/* camera A */
cam_src = clk_get(&pdev->dev, "xxti");
if (IS_ERR(cam_src))
return PTR_ERR(cam_src);
cam_A_clk = clk_get(&pdev->dev, "sclk_cam0");
if (IS_ERR(cam_A_clk))
return PTR_ERR(cam_A_clk);
epll = clk_get_rate(cam_src);
printk(KERN_DEBUG "epll : %ld\n", epll);
clk_set_parent(cam_A_clk, cam_src);
clk_set_rate(cam_A_clk, 24 * 1000000);
clk_put(cam_src);
clk_put(cam_A_clk);
return 0;
}
static int msm_csiphy_lane_config(struct csiphy_device *csiphy_dev,
struct msm_camera_csiphy_params *csiphy_params)
{
int rc = 0;
int j = 0, curr_lane = 0;
uint32_t val = 0, clk_rate = 0, round_rate = 0;
uint8_t lane_cnt = 0;
uint16_t lane_mask = 0;
void __iomem *csiphybase;
uint8_t csiphy_id = csiphy_dev->pdev->id;
int32_t lane_val = 0, lane_right = 0, num_lanes = 0;
struct clk **csid_phy_clk_ptr;
int ratio = 1;
csiphybase = csiphy_dev->base;
if (!csiphybase) {
pr_err("%s: csiphybase NULL\n", __func__);
return -EINVAL;
}
csiphy_dev->lane_mask[csiphy_id] |= csiphy_params->lane_mask;
lane_mask = csiphy_dev->lane_mask[csiphy_id];
lane_cnt = csiphy_params->lane_cnt;
if (csiphy_params->lane_cnt < 1 || csiphy_params->lane_cnt > 4) {
pr_err("%s: unsupported lane cnt %d\n",
__func__, csiphy_params->lane_cnt);
return rc;
}
csid_phy_clk_ptr = csiphy_dev->csiphy_clk;
if (!csid_phy_clk_ptr) {
pr_err("csiphy_timer_src_clk get failed\n");
return -EINVAL;
}
clk_rate = (csiphy_params->csiphy_clk > 0)
? csiphy_params->csiphy_clk :
csiphy_dev->csiphy_max_clk;
round_rate = clk_round_rate(
csid_phy_clk_ptr[csiphy_dev->csiphy_clk_index],
clk_rate);
if (round_rate >= csiphy_dev->csiphy_max_clk)
round_rate = csiphy_dev->csiphy_max_clk;
else {
ratio = csiphy_dev->csiphy_max_clk/round_rate;
csiphy_params->settle_cnt = csiphy_params->settle_cnt/ratio;
}
CDBG("set from usr csiphy_clk clk_rate = %u round_rate = %u\n",
clk_rate, round_rate);
rc = clk_set_rate(
csid_phy_clk_ptr[csiphy_dev->csiphy_clk_index],
round_rate);
if (rc < 0) {
pr_err("csiphy_timer_src_clk set failed\n");
return rc;
}
CDBG("%s csiphy_params, mask = 0x%x cnt = %d\n",
__func__,
csiphy_params->lane_mask,
csiphy_params->lane_cnt);
CDBG("%s csiphy_params, settle cnt = 0x%x csid %d\n",
__func__, csiphy_params->settle_cnt,
csiphy_params->csid_core);
if (csiphy_dev->hw_version >= CSIPHY_VERSION_V30) {
val = msm_camera_io_r(csiphy_dev->clk_mux_base);
if (csiphy_params->combo_mode &&
(csiphy_params->lane_mask & 0x18) == 0x18) {
val &= ~0xf0;
val |= csiphy_params->csid_core << 4;
} else {
val &= ~0xf;
val |= csiphy_params->csid_core;
}
msm_camera_io_w(val, csiphy_dev->clk_mux_base);
CDBG("%s clk mux addr %p val 0x%x\n", __func__,
csiphy_dev->clk_mux_base, val);
mb();
}
msm_camera_io_w(0x1, csiphybase + csiphy_dev->ctrl_reg->
csiphy_reg.mipi_csiphy_glbl_t_init_cfg0_addr);
msm_camera_io_w(0x1, csiphybase + csiphy_dev->ctrl_reg->
csiphy_reg.mipi_csiphy_t_wakeup_cfg0_addr);
if (csiphy_dev->hw_version < CSIPHY_VERSION_V30) {
val = 0x3;
msm_camera_io_w((lane_mask << 2) | val,
csiphybase +
csiphy_dev->ctrl_reg->
csiphy_reg.mipi_csiphy_glbl_pwr_cfg_addr);
msm_camera_io_w(0x10, csiphybase +
csiphy_dev->ctrl_reg->csiphy_reg.
mipi_csiphy_lnck_cfg2_addr);
msm_camera_io_w(csiphy_params->settle_cnt,
csiphybase +
csiphy_dev->ctrl_reg->csiphy_reg.
mipi_csiphy_lnck_cfg3_addr);
msm_camera_io_w(0x24,
csiphybase + csiphy_dev->ctrl_reg->
csiphy_reg.mipi_csiphy_interrupt_mask0_addr);
msm_camera_io_w(0x24,
csiphybase + csiphy_dev->ctrl_reg->
csiphy_reg.mipi_csiphy_interrupt_clear0_addr);
} else {
val = 0x1;
msm_camera_io_w((lane_mask << 1) | val,
csiphybase +
csiphy_dev->ctrl_reg->
csiphy_reg.mipi_csiphy_glbl_pwr_cfg_addr);
msm_camera_io_w(csiphy_params->combo_mode <<
csiphy_dev->ctrl_reg->csiphy_reg.
mipi_csiphy_mode_config_shift,
csiphybase +
csiphy_dev->ctrl_reg->csiphy_reg.
mipi_csiphy_glbl_reset_addr);
}
lane_mask &= 0x1f;
while (lane_mask & 0x1f) {
if (!(lane_mask & 0x1)) {
j++;
lane_mask >>= 1;
continue;
}
msm_camera_io_w(0x10,
csiphybase + csiphy_dev->ctrl_reg->csiphy_reg.
mipi_csiphy_lnn_cfg2_addr + 0x40*j);
msm_camera_io_w(csiphy_params->settle_cnt,
csiphybase + csiphy_dev->ctrl_reg->csiphy_reg.
mipi_csiphy_lnn_cfg3_addr + 0x40*j);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_reg.
mipi_csiphy_interrupt_mask_val, csiphybase +
csiphy_dev->ctrl_reg->csiphy_reg.
mipi_csiphy_interrupt_mask_addr + 0x4*j);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_reg.
mipi_csiphy_interrupt_mask_val, csiphybase +
csiphy_dev->ctrl_reg->csiphy_reg.
mipi_csiphy_interrupt_clear_addr + 0x4*j);
if (csiphy_dev->is_3_1_20nm_hw == 1) {
if (j > CLK_LANE_OFFSET) {
lane_right = 0x8;
num_lanes = (lane_cnt - curr_lane)
<< NUM_LANES_OFFSET;
if (lane_cnt < curr_lane) {
pr_err("%s: Lane_cnt is less than curr_lane number\n",
__func__);
return -EINVAL;
}
lane_val = lane_right|num_lanes;
} else if (j == 1) {
lane_val = 0x4;
}
if (csiphy_params->combo_mode == 1) {
/*
* In the case of combo mode, the clock is always
* 4th lane for the second sensor.
* So check whether the sensor is of one lane
* sensor and curr_lane for 0.
*/
if (curr_lane == 0 &&
((csiphy_params->lane_mask &
0x18) == 0x18))
lane_val = 0x4;
}
msm_camera_io_w(lane_val, csiphybase +
csiphy_dev->ctrl_reg->csiphy_reg.
mipi_csiphy_lnn_misc1_addr + 0x40*j);
msm_camera_io_w(0x17, csiphybase +
csiphy_dev->ctrl_reg->csiphy_reg.
mipi_csiphy_lnn_test_imp + 0x40*j);
curr_lane++;
}
j++;
lane_mask >>= 1;
}
int s3cfb_clk_on(struct platform_device *pdev, struct clk **s3cfb_clk)
{
struct clk *sclk = NULL;
struct clk *mout_fimd = NULL, *mout_mpll = NULL;
u32 rate = 0;
int ret;
sclk = clk_get(&pdev->dev, "sclk_fimd");
if (IS_ERR(sclk)) {
dev_err(&pdev->dev, "failed to get sclk for fimd\n");
goto err_clk1;
}
mout_mpll = clk_get(&pdev->dev, "mout_mpll");
if (IS_ERR(mout_mpll)) {
dev_err(&pdev->dev, "failed to get mout_mpll\n");
goto err_clk1;
}
mout_fimd = clk_get(&pdev->dev, "mout_fimd");
if (IS_ERR(mout_fimd)) {
dev_err(&pdev->dev,
"failed to get mout_fimd\n");
goto err_clk2;
}
clk_set_parent(mout_fimd, mout_mpll);
rate = clk_round_rate(sclk, 133400000);
dev_dbg(&pdev->dev, "set fimd sclk rate to %d\n", rate);
printk("LCD rate:%d",rate);
if (!rate)
rate = 133400000;
clk_set_rate(sclk, rate);
dev_dbg(&pdev->dev, "set fimd sclk rate to %d\n", rate);
clk_put(mout_mpll);
clk_put(mout_fimd);
ret = s5pv210_pd_enable("fimd_pd");
if (ret < 0) {
dev_err(&pdev->dev, "failed to enable fimd power domain\n");
goto err_clk2;
}
clk_enable(sclk);
*s3cfb_clk = sclk;
return 0;
err_clk2:
clk_put(mout_mpll);
err_clk1:
clk_put(sclk);
return -EINVAL;
}
int msm_camio_vfe_clk_rate_set(int rate)
{
struct clk *clk = camio_vfe_clk;
return clk_set_rate(clk, rate);
}