void esai_clk_sel_gate_on()
{
// source from PLL3_508
HW_CCM_CSCMR2.B.ESAI_CLK_SEL = 1;
clock_gating_config(REGS_ESAI_BASE, CLOCK_ON);
}
/*!
* @brief SPDIF clock configuration
*
* Use the default setting as follow:
* CDCDR[spdif0_clk_sel](PLL3)->CDCDR[spdif0_clk_pred](div2)->CDCDR[spdif0_clk_podf](div8)-> spdif0_clk_root, so
* the freqency of spdif0_clk should be 480/2/8 = 30MHz.
*/
void spdif_clk_cfg(void)
{
HW_CCM_CDCDR.B.SPDIF0_CLK_SEL = 3; // PLL3
HW_CCM_CDCDR.B.SPDIF0_CLK_PODF = 7; // div 8
HW_CCM_CDCDR.B.SPDIF0_CLK_PRED = 1; // div 2
clock_gating_config(SPDIF_BASE_ADDR, CLOCK_ON);
return;
}
void epit_init(uint32_t instance, uint32_t clock_src, uint32_t prescaler,
uint32_t reload_mode, uint32_t load_val, uint32_t low_power_mode)
{
uint32_t control_reg_tmp = 0;
uint32_t base = REGS_EPIT_BASE(instance);
// enable the source clocks to the EPIT port
clock_gating_config(base, CLOCK_ON);
// start with a known state by disabling and reseting the module
HW_EPIT_CR_WR(instance, BM_EPIT_CR_SWR);
// wait for the reset to complete
while ((HW_EPIT_CR(instance).B.SWR) != 0) ;
// set the reference source clock for the counter
control_reg_tmp |= BF_EPIT_CR_CLKSRC(clock_src);
// set the counter clock prescaler value - 0 to 4095
control_reg_tmp |= BF_EPIT_CR_PRESCALAR(prescaler-1);
// set the reload mode
if (reload_mode == SET_AND_FORGET)
{
control_reg_tmp |= BM_EPIT_CR_RLD;
}
// set behavior for low power mode
if (low_power_mode & WAIT_MODE_EN)
{
control_reg_tmp |= BM_EPIT_CR_WAITEN;
}
if (low_power_mode & STOP_MODE_EN)
{
control_reg_tmp |= BM_EPIT_CR_STOPEN;
}
// make the counter start from a known value when enabled, this is loaded from
// EPITLR register if RLD=reload_mode=1 or 0xFFFFFFFF if RLD=reload_mode=0
control_reg_tmp |= BM_EPIT_CR_IOVW | BM_EPIT_CR_ENMOD;
// finally write the control register
HW_EPIT_CR_WR(instance, control_reg_tmp);
// initialize the load register especially if RLD=reload_mode=SET_AND_FORGET=1
// and if the value is different from 0 which is the lowest counter value
if (load_val != 0)
{
HW_EPIT_LR_WR(instance, load_val);
}
}
int i2c_init(uint32_t base, uint32_t baud)
{
int instance;
// Accept either an instance or base address for the base param.
if (base >= 1 && base <= HW_I2C_INSTANCE_COUNT)
{
instance = base;
}
else
{
instance = REGS_I2C_INSTANCE(base);
}
// enable the source clocks to the I2C port
clock_gating_config(REGS_I2C_BASE(instance), CLOCK_ON);
// Set iomux configuration
i2c_iomux_config(instance);
// reset I2C
HW_I2C_I2CR_WR(instance, 0);
// Set clock.
set_i2c_clock(instance, baud);
// set an I2C slave address
// HW_I2C_IADR_WR(instance, IMX6_DEFAULT_SLAVE_ID);
// clear the status register
HW_I2C_I2SR_WR(instance, 0);
// enable the I2C controller
HW_I2C_I2CR_WR(instance, BM_I2C_I2CR_IEN);
return 0;
}
void uart_init(uint32_t instance, uint32_t baudrate, uint8_t parity,
uint8_t stopbits, uint8_t datasize, uint8_t flowcontrol)
{
uint32_t base = REGS_UART_BASE(instance);
/* configure the I/O for the port */
uart_iomux_config(instance);
/* enable the source clocks to the UART port */
clock_gating_config(base, CLOCK_ON);
/* Wait for UART to finish transmitting before changing the configuration */
while (!(HW_UART_UTS(instance).B.TXEMPTY)) ;
/* Disable UART */
HW_UART_UCR1_CLR(instance,BM_UART_UCR1_UARTEN );
/* Configure FIFOs trigger level to half-full and half-empty */
HW_UART_UFCR_WR(instance, BF_UART_UFCR_RXTL(16) | UART_UFCR_RFDIV | BF_UART_UFCR_TXTL(16));
/* Setup One Millisecond timer */
HW_UART_ONEMS_WR(instance, uart_get_reffreq(instance) / 1000);
/* Set parity */
if (parity == PARITY_NONE)
HW_UART_UCR2_CLR(instance,(BM_UART_UCR2_PREN| BM_UART_UCR2_PROE));
else if (parity == PARITY_ODD)
HW_UART_UCR2_SET(instance,(BM_UART_UCR2_PREN| BM_UART_UCR2_PROE));
else { /* parity == PARITY_EVEN */
HW_UART_UCR2_SET(instance, BM_UART_UCR2_PREN);
HW_UART_UCR2_CLR(instance, BM_UART_UCR2_PROE);
}
/* Set stop bit */
if (stopbits == STOPBITS_ONE)
HW_UART_UCR2_CLR(instance, BM_UART_UCR2_STPB);
else /* stopbits == STOPBITS_TWO */
HW_UART_UCR2_SET(instance, BM_UART_UCR2_STPB);
/* Set data size */
if (datasize == EIGHTBITS)
HW_UART_UCR2_SET(instance, BM_UART_UCR2_WS);
else /* stopbits == STOPBITS_TWO */
HW_UART_UCR2_CLR(instance, BM_UART_UCR2_WS);
/* Configure the flow control */
if (flowcontrol == FLOWCTRL_ON) {
/* transmit done when RTS asserted */
HW_UART_UCR2_CLR(instance, BM_UART_UCR2_IRTS );
/* CTS controlled by the receiver */
HW_UART_UCR2_SET(instance, BM_UART_UCR2_CTSC );
} else { /* flowcontrol == FLOWCTRL_OFF */
/* Ignore RTS */
HW_UART_UCR2_SET(instance, BM_UART_UCR2_IRTS);
/* CTS controlled by the CTS bit */
HW_UART_UCR2_CLR(instance, BM_UART_UCR2_CTSC);
}
/* the reference manual says that this bit must always be set */
HW_UART_UCR3_SET(instance, BM_UART_UCR3_RXDMUXSEL);
/* Enable UART */
HW_UART_UCR1_SET(instance, BM_UART_UCR1_UARTEN);
/* Enable FIFOs and does software reset to clear status flags, reset
the transmit and receive state machine, and reset the FIFOs */
HW_UART_UCR2_SET(instance, BM_UART_UCR2_TXEN | BM_UART_UCR2_RXEN | BM_UART_UCR2_SRST);
/* Set the numerator value minus one of the BRM ratio */
HW_UART_UBIR_WR(instance, (baudrate / 100) - 1);
/* Set the denominator value minus one of the BRM ratio */
HW_UART_UBMR_WR(instance, ((uart_get_reffreq(instance) / 1600) - 1));
/* Optional: prevent the UART to enter debug state. Useful when debugging
the code with a JTAG and without active IRQ */
HW_UART_UTS_SET(instance, BM_UART_UTS_DBGEN);
}
