/** * If the PLL settings are in place switch the CPU core frequency to the max. value */ static int pcm038_power_init(void) { uint32_t spctl0; int ret; spctl0 = get_pll_spctl10(); /* PLL registers already set to their final values? */ if (spctl0 == SPCTL0_VAL && MPCTL0 == MPCTL0_VAL) { console_flush(); ret = pmic_power(); if (ret == 0) { /* wait for required power level to run the CPU at 400 MHz */ udelay(100000); CSCR = CSCR_VAL_FINAL; PCDR0 = 0x130410c3; PCDR1 = 0x09030911; /* Clocks have changed. Notify clients */ clock_notifier_call_chain(); } else { printf("Failed to initialize PMIC. Will continue with low CPU speed\n"); } } /* clock gating enable */ GPCR = 0x00050f08; return 0; }
/** * If the PLL settings are in place switch the CPU core frequency to the max. value */ static int pcm038_power_init(void) { uint32_t spctl0 = get_pll_spctl10(); struct mc13xxx *mc13xxx = mc13xxx_get(); /* PLL registers already set to their final values? */ if (spctl0 == SPCTL0_VAL && readl(MX27_CCM_BASE_ADDR + MX27_MPCTL0) == MPCTL0_VAL) { console_flush(); if (mc13xxx) { mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(0), MC13783_SWX_VOLTAGE(MC13783_SWX_VOLTAGE_1_450) | MC13783_SWX_VOLTAGE_DVS(MC13783_SWX_VOLTAGE_1_450) | MC13783_SWX_VOLTAGE_STANDBY(MC13783_SWX_VOLTAGE_1_450)); mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(4), MC13783_SW1A_MODE(MC13783_SWX_MODE_NO_PULSE_SKIP) | MC13783_SW1A_MODE_STANDBY(MC13783_SWX_MODE_NO_PULSE_SKIP) | MC13783_SW1A_SOFTSTART | MC13783_SW1B_MODE(MC13783_SWX_MODE_NO_PULSE_SKIP) | MC13783_SW1B_MODE_STANDBY(MC13783_SWX_MODE_NO_PULSE_SKIP) | MC13783_SW1B_SOFTSTART | MC13783_SW_PLL_FACTOR(32)); /* Setup VMMC voltage */ if (IS_ENABLED(CONFIG_MCI_IMX)) { u32 val; mc13xxx_reg_read(mc13xxx, MC13783_REG_REG_SETTING(1), &val); /* VMMC1 = 3.00 V */ val &= ~(7 << 6); val |= 6 << 6; mc13xxx_reg_write(mc13xxx, MC13783_REG_REG_SETTING(1), val); mc13xxx_reg_read(mc13xxx, MC13783_REG_REG_MODE(1), &val); /* Enable VMMC1 */ val |= 1 << 18; mc13xxx_reg_write(mc13xxx, MC13783_REG_REG_MODE(1), val); } /* wait for required power level to run the CPU at 400 MHz */ udelay(100000); writel(CSCR_VAL_FINAL, MX27_CCM_BASE_ADDR + MX27_CSCR); writel(0x130410c3, MX27_CCM_BASE_ADDR + MX27_PCDR0); writel(0x09030911, MX27_CCM_BASE_ADDR + MX27_PCDR1); /* Clocks have changed. Notify clients */ clock_notifier_call_chain(); } else { pr_err("Failed to initialize PMIC. Will continue with low CPU speed\n"); } } /* clock gating enable */ writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR); return 0; }
static int imx51_babbage_late_init(void) { if (!of_machine_is_compatible("fsl,imx51-babbage")) return 0; babbage_power_init(); console_flush(); imx51_init_lowlevel(800); clock_notifier_call_chain(); armlinux_set_bootparams((void *)0x90000100); armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE); imx51_bbu_internal_mmc_register_handler("mmc", "/dev/mmc0", BBU_HANDLER_FLAG_DEFAULT, (void *)flash_header_imx51_babbage_start, flash_header_imx51_babbage_end - flash_header_imx51_babbage_start, 0); return 0; }
static int f3s_devices_init(void) { imx51_iim_register_fec_ethaddr(); imx51_add_fec(&fec_info); imx51_add_mmc0(NULL); spi_register_board_info(mx51_babbage_spi_board_info, ARRAY_SIZE(mx51_babbage_spi_board_info)); imx51_add_spi0(&spi_0_data); babbage_power_init(); console_flush(); imx51_init_lowlevel(); clock_notifier_call_chain(); armlinux_set_bootparams((void *)0x90000100); armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE); return 0; }
static int neso_pll(void) { void *vram = (void *)0xffff4c00; void (*pllfunc)(void) = vram; printf("initialising PLLs\n"); memcpy(vram, &neso_pll_init, 0x100); console_flush(); pllfunc(); /* clock gating enable */ GPCR = 0x00050f08; PCDR0 = 0x130410c3; PCDR1 = 0x09030911; /* Clocks have changed. Notify clients */ clock_notifier_call_chain(); return 0; }
static int neso_pll(void) { void *vram = (void *)0xffff4c00; void (*pllfunc)(void) = vram; printf("initialising PLLs\n"); memcpy(vram, &neso_pll_init, 0x100); console_flush(); pllfunc(); /* clock gating enable */ writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR); writel(0x130410c3, MX27_CCM_BASE_ADDR + MX27_PCDR0); writel(0x09030911, MX27_CCM_BASE_ADDR + MX27_PCDR1); /* Clocks have changed. Notify clients */ clock_notifier_call_chain(); return 0; }
static int pcm038_power_init(void) { int ret; printf("initialising PLLs\n"); console_flush(); ret = pmic_power(); if (ret) { printf("Failed to initialize PMIC. Will continue with low CPU speed\n"); return 0; } /* wait for good power level */ udelay(100000); #define CSCR_VAL CSCR_USB_DIV(3) | \ CSCR_SD_CNT(3) | \ CSCR_MSHC_SEL | \ CSCR_H264_SEL | \ CSCR_SSI1_SEL | \ CSCR_SSI2_SEL | \ CSCR_MCU_SEL | \ CSCR_ARM_SRC_MPLL | \ CSCR_SP_SEL | \ CSCR_ARM_DIV(0) | \ CSCR_FPM_EN | \ CSCR_SPEN | \ CSCR_MPEN /* * pll clock initialization - see section 3.4.3 of the i.MX27 manual */ MPCTL0 = IMX_PLL_PD(0) | IMX_PLL_MFD(51) | IMX_PLL_MFI(7) | IMX_PLL_MFN(35); /* MPLL = 399 MHz */ SPCTL0 = IMX_PLL_PD(1) | IMX_PLL_MFD(12) | IMX_PLL_MFI(9) | IMX_PLL_MFN(3); /* SPLL = 240 MHz */ /* * ARM clock = (399 MHz / 2) / (ARM divider = 1) = 200 MHz * AHB clock = (399 MHz / 3) / (AHB divider = 2) = 66.5 MHz * System clock (HCLK) = 133 MHz */ pll_wait(); CSCR = CSCR_VAL | CSCR_AHB_DIV(1) | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART; pll_wait(); /* clock gating enable */ GPCR = 0x00050f08; PCDR0 = 0x130410c3; PCDR1 = 0x09030911; /* Clocks have changed. Notify clients */ clock_notifier_call_chain(); return 0; }
void imx53_init_lowlevel(unsigned int cpufreq_mhz) { imx53_init_lowlevel_early(cpufreq_mhz); clock_notifier_call_chain(); }
static void babbage_power_init(struct mc13xxx *mc13xxx) { u32 val; /* Write needed to Power Gate 2 register */ mc13xxx_reg_read(mc13xxx, MC13892_REG_POWER_MISC, &val); val &= ~0x10000; mc13xxx_reg_write(mc13xxx, MC13892_REG_POWER_MISC, val); /* Write needed to update Charger 0 */ mc13xxx_reg_write(mc13xxx, MC13892_REG_CHARGE, 0x0023807F); /* power up the system first */ mc13xxx_reg_write(mc13xxx, MC13892_REG_POWER_MISC, 0x00200000); if (imx_silicon_revision() < IMX_CHIP_REV_3_0) { /* Set core voltage to 1.1V */ mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_0, &val); val &= ~0x1f; val |= 0x14; mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_0, val); /* Setup VCC (SW2) to 1.25 */ mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_1, &val); val &= ~0x1f; val |= 0x1a; mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_1, val); /* Setup 1V2_DIG1 (SW3) to 1.25 */ mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_2, &val); val &= ~0x1f; val |= 0x1a; mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_2, val); } else { /* Setup VCC (SW2) to 1.225 */ mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_1, &val); val &= ~0x1f; val |= 0x19; mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_1, val); /* Setup 1V2_DIG1 (SW3) to 1.2 */ mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_2, &val); val &= ~0x1f; val |= 0x18; mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_2, val); } if (mc13xxx_revision(mc13xxx) < MC13892_REVISION_2_0) { /* Set switchers in PWM mode for Atlas 2.0 and lower */ /* Setup the switcher mode for SW1 & SW2*/ mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_4, &val); val &= ~0x3c0f; val |= 0x1405; mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_4, val); /* Setup the switcher mode for SW3 & SW4 */ mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_5, &val); val &= ~0xf0f; val |= 0x505; mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_5, val); } else { /* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */ /* Setup the switcher mode for SW1 & SW2*/ mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_4, &val); val &= ~0x3c0f; val |= 0x2008; mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_4, val); /* Setup the switcher mode for SW3 & SW4 */ mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_5, &val); val &= ~0xf0f; val |= 0x808; mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_5, val); } /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.5V */ mc13xxx_reg_read(mc13xxx, MC13892_REG_SETTING_0, &val); val &= ~0x34030; val |= 0x10020; mc13xxx_reg_write(mc13xxx, MC13892_REG_SETTING_0, val); /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ mc13xxx_reg_read(mc13xxx, MC13892_REG_SETTING_1, &val); val &= ~0x1FC; val |= 0x1F4; mc13xxx_reg_write(mc13xxx, MC13892_REG_SETTING_1, val); /* Configure VGEN3 and VCAM regulators to use external PNP */ val = 0x208; mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val); udelay(200); /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ val = 0x49249; mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val); udelay(200); pr_info("initialized PMIC\n"); console_flush(); imx51_init_lowlevel(800); clock_notifier_call_chain(); }