void nuc900_clock_source(struct device *dev, unsigned char *src)
{
unsigned int clkval;
const char *dev_id;
BUG_ON(!src);
clkval = 0;
mutex_lock(&clksel_sem);
if (dev)
dev_id = dev_name(dev);
else
dev_id = "cpufreq";
if (strcmp(src, "pll0") == 0)
clkval = PLL0;
else if (strcmp(src, "pll1") == 0)
clkval = PLL1;
else if (strcmp(src, "ext") == 0)
clkval = EXT;
else if (strcmp(src, "oth") == 0)
clkval = OTHER;
clock_source_select(dev_id, clkval);
mutex_unlock(&clksel_sem);
}
/***********************************************************************************************************************
* Function name: operating_frequency_set
* Description : Configures the clock settings for each of the device clocks
* Arguments : none
* Return value : none
***********************************************************************************************************************/
static void operating_frequency_set (void)
{
/* Used for constructing value to write to SCKCR register. */
uint32_t temp_clock = 0;
/*
Default settings:
Clock Description Frequency
----------------------------------------
Input Clock Frequency............ 24 MHz
PLL frequency (x10).............. 240 MHz
Internal Clock Frequency......... 120 MHz
Peripheral Clock Frequency A..... 120 MHz
Peripheral Clock Frequency B..... 60 MHz
Peripheral Clock Frequency C..... 60 MHz
Peripheral Clock Frequency D..... 60 MHz
External Bus Clock Frequency..... 120 MHz
Flash IF Clock Frequency......... 60 MHz
USB Clock Frequency.............. 48 MHz */
/* Protect off. */
SYSTEM.PRCR.WORD = 0xA50B;
/* Select the clock based upon user's choice. */
clock_source_select();
/* Figure out setting for FCK bits. */
#if BSP_CFG_FCK_DIV == 1
/* Do nothing since FCK bits should be 0. */
#elif BSP_CFG_FCK_DIV == 2
temp_clock |= 0x10000000;
#elif BSP_CFG_FCK_DIV == 4
temp_clock |= 0x20000000;
#elif BSP_CFG_FCK_DIV == 8
temp_clock |= 0x30000000;
#elif BSP_CFG_FCK_DIV == 16
temp_clock |= 0x40000000;
#elif BSP_CFG_FCK_DIV == 32
temp_clock |= 0x50000000;
#elif BSP_CFG_FCK_DIV == 64
temp_clock |= 0x60000000;
#else
#error "Error! Invalid setting for BSP_CFG_FCK_DIV in r_bsp_config.h"
#endif
/* Figure out setting for ICK bits. */
#if BSP_CFG_ICK_DIV == 1
/* Do nothing since ICK bits should be 0. */
#elif BSP_CFG_ICK_DIV == 2
temp_clock |= 0x01000000;
#elif BSP_CFG_ICK_DIV == 4
temp_clock |= 0x02000000;
#elif BSP_CFG_ICK_DIV == 8
temp_clock |= 0x03000000;
#elif BSP_CFG_ICK_DIV == 16
temp_clock |= 0x04000000;
#elif BSP_CFG_ICK_DIV == 32
temp_clock |= 0x05000000;
#elif BSP_CFG_ICK_DIV == 64
temp_clock |= 0x06000000;
#else
#error "Error! Invalid setting for BSP_CFG_ICK_DIV in r_bsp_config.h"
#endif
/* Figure out setting for BCK bits. */
#if BSP_CFG_BCK_DIV == 1
/* Do nothing since BCK bits should be 0. */
#elif BSP_CFG_BCK_DIV == 2
temp_clock |= 0x00010000;
#elif BSP_CFG_BCK_DIV == 4
temp_clock |= 0x00020000;
#elif BSP_CFG_BCK_DIV == 8
temp_clock |= 0x00030000;
#elif BSP_CFG_BCK_DIV == 16
temp_clock |= 0x00040000;
#elif BSP_CFG_BCK_DIV == 32
temp_clock |= 0x00050000;
#elif BSP_CFG_BCK_DIV == 64
temp_clock |= 0x00060000;
#else
#error "Error! Invalid setting for BSP_CFG_BCK_DIV in r_bsp_config.h"
#endif
/* Configure PSTOP1 bit for BCLK output. */
#if BSP_CFG_BCLK_OUTPUT == 0
/* Set PSTOP1 bit */
temp_clock |= 0x00800000;
#elif BSP_CFG_BCLK_OUTPUT == 1
/* Clear PSTOP1 bit */
temp_clock &= ~0x00800000;
#elif BSP_CFG_BCLK_OUTPUT == 2
/* Clear PSTOP1 bit */
temp_clock &= ~0x00800000;
/* Set BCLK divider bit */
SYSTEM.BCKCR.BIT.BCLKDIV = 1;
#else
#error "Error! Invalid setting for BSP_CFG_BCLK_OUTPUT in r_bsp_config.h"
#endif
/* Configure PSTOP0 bit for SDCLK output. */
#if BSP_CFG_SDCLK_OUTPUT == 0
/* Set PSTOP0 bit */
temp_clock |= 0x00400000;
#elif BSP_CFG_SDCLK_OUTPUT == 1
/* Clear PSTOP0 bit */
temp_clock &= ~0x00400000;
#else
#error "Error! Invalid setting for BSP_CFG_SDCLK_OUTPUT in r_bsp_config.h"
#endif
/* Figure out setting for PCKA bits. */
#if BSP_CFG_PCKA_DIV == 1
/* Do nothing since PCKA bits should be 0. */
#elif BSP_CFG_PCKA_DIV == 2
temp_clock |= 0x00001000;
#elif BSP_CFG_PCKA_DIV == 4
temp_clock |= 0x00002000;
#elif BSP_CFG_PCKA_DIV == 8
temp_clock |= 0x00003000;
#elif BSP_CFG_PCKA_DIV == 16
temp_clock |= 0x00004000;
#elif BSP_CFG_PCKA_DIV == 32
temp_clock |= 0x00005000;
#elif BSP_CFG_PCKA_DIV == 64
temp_clock |= 0x00006000;
#else
#error "Error! Invalid setting for BSP_CFG_PCKA_DIV in r_bsp_config.h"
#endif
/* Figure out setting for PCKB bits. */
#if BSP_CFG_PCKB_DIV == 1
/* Do nothing since PCKB bits should be 0. */
#elif BSP_CFG_PCKB_DIV == 2
temp_clock |= 0x00000100;
#elif BSP_CFG_PCKB_DIV == 4
temp_clock |= 0x00000200;
#elif BSP_CFG_PCKB_DIV == 8
temp_clock |= 0x00000300;
#elif BSP_CFG_PCKB_DIV == 16
temp_clock |= 0x00000400;
#elif BSP_CFG_PCKB_DIV == 32
temp_clock |= 0x00000500;
#elif BSP_CFG_PCKB_DIV == 64
temp_clock |= 0x00000600;
#else
#error "Error! Invalid setting for BSP_CFG_PCKB_DIV in r_bsp_config.h"
#endif
/* Figure out setting for PCKC bits. */
#if BSP_CFG_PCKC_DIV == 1
/* Do nothing since PCKA bits should be 0. */
#elif BSP_CFG_PCKC_DIV == 2
temp_clock |= 0x00000010;
#elif BSP_CFG_PCKC_DIV == 4
temp_clock |= 0x00000020;
#elif BSP_CFG_PCKC_DIV == 8
temp_clock |= 0x00000030;
#elif BSP_CFG_PCKC_DIV == 16
temp_clock |= 0x00000040;
#elif BSP_CFG_PCKC_DIV == 32
temp_clock |= 0x00000050;
#elif BSP_CFG_PCKC_DIV == 64
temp_clock |= 0x00000060;
#else
#error "Error! Invalid setting for BSP_CFG_PCKC_DIV in r_bsp_config.h"
#endif
/* Figure out setting for PCKD bits. */
#if BSP_CFG_PCKD_DIV == 1
/* Do nothing since PCKD bits should be 0. */
#elif BSP_CFG_PCKD_DIV == 2
temp_clock |= 0x00000001;
#elif BSP_CFG_PCKD_DIV == 4
temp_clock |= 0x00000002;
#elif BSP_CFG_PCKD_DIV == 8
temp_clock |= 0x00000003;
#elif BSP_CFG_PCKD_DIV == 16
temp_clock |= 0x00000004;
#elif BSP_CFG_PCKD_DIV == 32
temp_clock |= 0x00000005;
#elif BSP_CFG_PCKD_DIV == 64
temp_clock |= 0x00000006;
#else
#error "Error! Invalid setting for BSP_CFG_PCKD_DIV in r_bsp_config.h"
#endif
/* Set SCKCR register. */
SYSTEM.SCKCR.LONG = temp_clock;
/* Re-init temp_clock to use to set SCKCR2. */
temp_clock = 0;
/* Figure out setting for UCK bits. */
#if BSP_CFG_UCK_DIV == 2
temp_clock |= 0x00000011;
#elif BSP_CFG_UCK_DIV == 3
temp_clock |= 0x00000021;
#elif BSP_CFG_UCK_DIV == 4
temp_clock |= 0x00000031;
#elif BSP_CFG_UCK_DIV == 5
temp_clock |= 0x00000041;
#else
#error "Error! Invalid setting for BSP_CFG_UCK_DIV in r_bsp_config.h"
#endif
/* Set SCKCR2 register. */
SYSTEM.SCKCR2.WORD = (uint16_t)temp_clock;
/* Choose clock source. Default for r_bsp_config.h is PLL. */
SYSTEM.SCKCR3.WORD = ((uint16_t)BSP_CFG_CLOCK_SOURCE) << 8;
#if (BSP_CFG_CLOCK_SOURCE != 0)
/* We can now turn LOCO off since it is not going to be used. */
SYSTEM.LOCOCR.BYTE = 0x01;
#endif
/* Protect on. */
SYSTEM.PRCR.WORD = 0xA500;
}
/***********************************************************************************************************************
* Function name: operating_frequency_set
* Description : Configures the clock settings for each of the device clocks
* Arguments : none
* Return value : none
***********************************************************************************************************************/
static void operating_frequency_set (void)
{
/* Used for constructing value to write to SCKCR and CKOCR registers. */
uint32_t temp_clock = 0;
/*
Default settings:
Clock Description Frequency
----------------------------------------
Input Clock Frequency............ 16 MHz
PLL frequency (x3)............... 48 MHz
Internal Clock Frequency......... 24 MHz
Peripheral Clock Frequency....... 24 MHz
Clock Out Frequency.............. 1 MHz */
/* Protect off. */
SYSTEM.PRCR.WORD = 0xA50F;
/* Select the clock based upon user's choice. */
clock_source_select();
/* Figure out setting for FCK bits. */
#if BSP_CFG_FCK_DIV == 1
/* Do nothing since FCK bits should be 0. */
#elif BSP_CFG_FCK_DIV == 2
temp_clock |= 0x10000000;
#elif BSP_CFG_FCK_DIV == 4
temp_clock |= 0x20000000;
#elif BSP_CFG_FCK_DIV == 8
temp_clock |= 0x30000000;
#elif BSP_CFG_FCK_DIV == 16
temp_clock |= 0x40000000;
#elif BSP_CFG_FCK_DIV == 32
temp_clock |= 0x50000000;
#elif BSP_CFG_FCK_DIV == 64
temp_clock |= 0x60000000;
#else
#error "Error! Invalid setting for BSP_CFG_FCK_DIV in r_bsp_config.h"
#endif
/* Figure out setting for ICK bits. */
#if BSP_CFG_ICK_DIV == 1
/* Do nothing since ICK bits should be 0. */
#elif BSP_CFG_ICK_DIV == 2
temp_clock |= 0x01000000;
#elif BSP_CFG_ICK_DIV == 4
temp_clock |= 0x02000000;
#elif BSP_CFG_ICK_DIV == 8
temp_clock |= 0x03000000;
#elif BSP_CFG_ICK_DIV == 16
temp_clock |= 0x04000000;
#elif BSP_CFG_ICK_DIV == 32
temp_clock |= 0x05000000;
#elif BSP_CFG_ICK_DIV == 64
temp_clock |= 0x06000000;
#else
#error "Error! Invalid setting for BSP_CFG_ICK_DIV in r_bsp_config.h"
#endif
/* Figure out setting for PCKB bits. */
#if BSP_CFG_PCKB_DIV == 1
/* Do nothing since PCKB bits should be 0. */
#elif BSP_CFG_PCKB_DIV == 2
temp_clock |= 0x00000100;
#elif BSP_CFG_PCKB_DIV == 4
temp_clock |= 0x00000200;
#elif BSP_CFG_PCKB_DIV == 8
temp_clock |= 0x00000300;
#elif BSP_CFG_PCKB_DIV == 16
temp_clock |= 0x00000400;
#elif BSP_CFG_PCKB_DIV == 32
temp_clock |= 0x00000500;
#elif BSP_CFG_PCKB_DIV == 64
temp_clock |= 0x00000600;
#else
#error "Error! Invalid setting for BSP_CFG_PCKB_DIV in r_bsp_config.h"
#endif
/* Figure out setting for PCKD bits. */
#if BSP_CFG_PCKD_DIV == 1
/* Do nothing since PCKD bits should be 0. */
#elif BSP_CFG_PCKD_DIV == 2
temp_clock |= 0x00000001;
#elif BSP_CFG_PCKD_DIV == 4
temp_clock |= 0x00000002;
#elif BSP_CFG_PCKD_DIV == 8
temp_clock |= 0x00000003;
#elif BSP_CFG_PCKD_DIV == 16
temp_clock |= 0x00000004;
#elif BSP_CFG_PCKD_DIV == 32
temp_clock |= 0x00000005;
#elif BSP_CFG_PCKD_DIV == 64
temp_clock |= 0x00000006;
#else
#error "Error! Invalid setting for BSP_CFG_PCKD_DIV in r_bsp_config.h"
#endif
/* Set SCKCR register. */
SYSTEM.SCKCR.LONG = temp_clock;
/* Choose clock source. Default for r_bsp_config.h is PLL. */
SYSTEM.SCKCR3.WORD = ((uint16_t)BSP_CFG_CLOCK_SOURCE) << 8;
#if (BSP_CFG_CLOCK_SOURCE != 0)
/* We can now turn LOCO off since it is not going to be used. */
SYSTEM.LOCOCR.BYTE = 0x01;
#endif
/* Protect on. */
SYSTEM.PRCR.WORD = 0xA500;
}
