int socfpga_dwmmc_init(u32 regbase, int bus_width, int index)
{
struct dwmci_host *host;
unsigned long clk = cm_get_mmc_controller_clk_hz();
if (clk == 0) {
printf("%s: MMC clock is zero!", __func__);
return -EINVAL;
}
/* calloc for zero init */
host = calloc(1, sizeof(struct dwmci_host));
if (!host) {
printf("%s: calloc() failed!\n", __func__);
return -ENOMEM;
}
host->name = "SOCFPGA DWMMC";
host->ioaddr = (void *)regbase;
host->buswidth = bus_width;
host->clksel = socfpga_dwmci_clksel;
host->dev_index = index;
/* fixed clock divide by 4 which due to the SDMMC wrapper */
host->bus_hz = clk;
host->fifoth_val = MSIZE(0x2) |
RX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2 - 1) |
TX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2);
return add_dwmci(host, host->bus_hz, 400000);
}
static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
{
/* FIXME: probe from DT eventually too/ */
const unsigned long clk = cm_get_mmc_controller_clk_hz();
struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
int fifo_depth;
if (clk == 0) {
printf("DWMMC: MMC clock is zero!");
return -EINVAL;
}
fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"fifo-depth", 0);
if (fifo_depth < 0) {
printf("DWMMC: Can't get FIFO depth\n");
return -EINVAL;
}
host->name = dev->name;
host->ioaddr = (void *)dev_get_addr(dev);
host->buswidth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"bus-width", 4);
host->clksel = socfpga_dwmci_clksel;
/*
* TODO([email protected]): Remove the need for this hack.
* We only have one dwmmc block on gen5 SoCFPGA.
*/
host->dev_index = 0;
/* Fixed clock divide by 4 which due to the SDMMC wrapper */
host->bus_hz = clk;
host->fifoth_val = MSIZE(0x2) |
RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
"drvsel", 3);
priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
"smplsel", 0);
host->priv = priv;
return 0;
}
void cm_print_clock_quick_summary(void)
{
printf("CLOCK: EOSC1 clock %d KHz\n",
(CONFIG_HPS_CLK_OSC1_HZ / 1000));
printf("CLOCK: EOSC2 clock %d KHz\n",
(CONFIG_HPS_CLK_OSC2_HZ / 1000));
printf("CLOCK: F2S_SDR_REF clock %d KHz\n",
(CONFIG_HPS_CLK_F2S_SDR_REF_HZ / 1000));
printf("CLOCK: F2S_PER_REF clock %d KHz\n",
(CONFIG_HPS_CLK_F2S_PER_REF_HZ / 1000));
printf("CLOCK: MPU clock %ld MHz\n",
(cm_get_mpu_clk_hz() / 1000000));
printf("CLOCK: DDR clock %ld MHz\n",
(cm_get_sdram_clk_hz() / 1000000));
printf("CLOCK: UART clock %ld KHz\n",
(cm_get_l4_sp_clk_hz() / 1000));
printf("CLOCK: MMC clock %ld KHz\n",
(cm_get_mmc_controller_clk_hz() / 1000));
printf("CLOCK: QSPI clock %ld KHz\n",
(cm_get_qspi_controller_clk_hz() / 1000));
}
void cm_derive_clocks_for_drivers(void)
{
cm_l4_sp_clock = cm_get_l4_sp_clk_hz();
cm_sdmmc_clock = cm_get_mmc_controller_clk_hz();
cm_qspi_clock = cm_get_qspi_controller_clk_hz();
}
static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx)
{
/* FIXME: probe from DT eventually too/ */
const unsigned long clk = cm_get_mmc_controller_clk_hz();
struct dwmci_host *host;
struct dwmci_socfpga_priv_data *priv;
fdt_addr_t reg_base;
int bus_width, fifo_depth;
if (clk == 0) {
printf("DWMMC%d: MMC clock is zero!", idx);
return -EINVAL;
}
/* Get the register address from the device node */
reg_base = fdtdec_get_addr(blob, node, "reg");
if (!reg_base) {
printf("DWMMC%d: Can't get base address\n", idx);
return -EINVAL;
}
/* Get the bus width from the device node */
bus_width = fdtdec_get_int(blob, node, "bus-width", 0);
if (bus_width <= 0) {
printf("DWMMC%d: Can't get bus-width\n", idx);
return -EINVAL;
}
fifo_depth = fdtdec_get_int(blob, node, "fifo-depth", 0);
if (fifo_depth < 0) {
printf("DWMMC%d: Can't get FIFO depth\n", idx);
return -EINVAL;
}
/* Allocate the host */
host = calloc(1, sizeof(*host));
if (!host)
return -ENOMEM;
/* Allocate the priv */
priv = calloc(1, sizeof(*priv));
if (!priv) {
free(host);
return -ENOMEM;
}
host->name = "SOCFPGA DWMMC";
host->ioaddr = (void *)reg_base;
host->buswidth = bus_width;
host->clksel = socfpga_dwmci_clksel;
host->dev_index = idx;
/* Fixed clock divide by 4 which due to the SDMMC wrapper */
host->bus_hz = clk;
host->fifoth_val = MSIZE(0x2) |
RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
priv->drvsel = fdtdec_get_uint(blob, node, "drvsel", 3);
priv->smplsel = fdtdec_get_uint(blob, node, "smplsel", 0);
host->priv = priv;
return add_dwmci(host, host->bus_hz, 400000);
}
