// qemu seems to use 24-hour GWT and the values are BCD encoded
void
cmostime(struct rtcdate *r)
{
struct rtcdate t1, t2;
int sb, bcd;
sb = cmos_read(CMOS_STATB);
bcd = (sb & (1 << 2)) == 0;
// make sure CMOS doesn't modify time while we read it
for(;;) {
fill_rtcdate(&t1);
if(cmos_read(CMOS_STATA) & CMOS_UIP)
continue;
fill_rtcdate(&t2);
if(memcmp(&t1, &t2, sizeof(t1)) == 0)
break;
}
// convert
if(bcd) {
#define CONV(x) (t1.x = ((t1.x >> 4) * 10) + (t1.x & 0xf))
CONV(second);
CONV(minute);
CONV(hour );
CONV(day );
CONV(month );
CONV(year );
#undef CONV
}
*r = t1;
r->year += 2000;
}
static inline __attribute__((unused)) int do_normal_boot(void)
{
unsigned char byte;
if (cmos_error() || !cmos_chksum_valid()) {
/* Invalid CMOS checksum detected!
* Force fallback boot...
*/
byte = cmos_read(RTC_BOOT_BYTE);
byte &= boot_set_fallback(byte) & 0x0f;
byte |= 0xf << 4;
cmos_write(byte, RTC_BOOT_BYTE);
}
/* The RTC_BOOT_BYTE is now o.k. see where to go. */
byte = cmos_read(RTC_BOOT_BYTE);
/* Are we attempting to boot normally? */
if (boot_use_normal(byte)) {
/* Are we already at the max count? */
if (boot_count(byte) < CONFIG_MAX_REBOOT_CNT)
byte = increment_boot_count(byte);
else
byte = boot_set_fallback(byte);
}
/* Save the boot byte */
cmos_write(byte, RTC_BOOT_BYTE);
/* Return selected code path for this boot attempt */
return boot_use_normal(byte);
}
static int cmos_error(void)
{
unsigned char reg_d;
/* See if the cmos error condition has been flagged */
reg_d = cmos_read(RTC_REG_D);
return (reg_d & RTC_VRT) == 0;
}
static void test_cmos(void)
{
uint8_t cmos;
cmos = cmos_read(CMOS_FLOPPY);
g_assert(cmos == 0x40);
}
static int cmos_read_bcd ( int port )
{
int in = cmos_read(port) ;
if ( cmos_bcd() )
return (in >> 4) * 10 + (in & 15) ;
else
return in ;
void bootblock_mainboard_init(void)
{
uint8_t recovery_enabled;
unsigned char addr;
unsigned char byte;
bootblock_northbridge_init();
bootblock_southbridge_init();
/* Recovery jumper is connected to SP5100 GPIO61, and clears the GPIO when placed in the Recovery position */
byte = pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x56);
byte |= 0x1 << 4; /* Set GPIO61 to input mode */
pci_io_write_config8(PCI_DEV(0, 0x14, 0), 0x56, byte);
recovery_enabled = (!(pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x57) & 0x1));
if (recovery_enabled) {
#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
/* Clear NVRAM checksum */
for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {
cmos_write(0x0, addr);
}
/* Set fallback boot */
byte = cmos_read(RTC_BOOT_BYTE);
byte &= 0xfc;
cmos_write(byte, RTC_BOOT_BYTE);
#else
/* FIXME
* Figure out how to recover if the option table is not available
*/
#endif
}
}
static void prepare_mrc_cache(struct pei_data *pei_data)
{
struct mrc_data_container *mrc_cache;
u16 c1, c2, checksum, seed_checksum;
// preset just in case there is an error
pei_data->mrc_input = NULL;
pei_data->mrc_input_len = 0;
/* Read scrambler seeds from CMOS */
pei_data->scrambler_seed = cmos_read32(CMOS_OFFSET_MRC_SEED);
printk(BIOS_DEBUG, "Read scrambler seed 0x%08x from CMOS 0x%02x\n",
pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
pei_data->scrambler_seed_s3 = cmos_read32(CMOS_OFFSET_MRC_SEED_S3);
printk(BIOS_DEBUG, "Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n",
pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
/* Compute seed checksum and compare */
c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed,
sizeof(u32));
c2 = compute_ip_checksum((u8*)&pei_data->scrambler_seed_s3,
sizeof(u32));
checksum = add_ip_checksums(sizeof(u32), c1, c2);
seed_checksum = cmos_read(CMOS_OFFSET_MRC_SEED_CHK);
seed_checksum |= cmos_read(CMOS_OFFSET_MRC_SEED_CHK+1) << 8;
if (checksum != seed_checksum) {
printk(BIOS_ERR, "%s: invalid seed checksum\n", __func__);
pei_data->scrambler_seed = 0;
pei_data->scrambler_seed_s3 = 0;
return;
}
if ((mrc_cache = find_current_mrc_cache()) == NULL) {
/* error message printed in find_current_mrc_cache */
return;
}
pei_data->mrc_input = mrc_cache->mrc_data;
pei_data->mrc_input_len = mrc_cache->mrc_data_size;
printk(BIOS_DEBUG, "%s: at %p, size %x checksum %04x\n",
__func__, pei_data->mrc_input,
pei_data->mrc_input_len, mrc_cache->mrc_checksum);
}
void cmos_post_log(void)
{
u8 code = 0;
#if CONFIG_CMOS_POST_EXTRA
u32 extra = 0;
#endif
spin_lock(&cmos_post_lock);
/* Get post code from other bank */
switch (cmos_read(CMOS_POST_BANK_OFFSET)) {
case CMOS_POST_BANK_0_MAGIC:
code = cmos_read(CMOS_POST_BANK_1_OFFSET);
#if CONFIG_CMOS_POST_EXTRA
extra = cmos_read32(CMOS_POST_BANK_1_EXTRA);
#endif
break;
case CMOS_POST_BANK_1_MAGIC:
code = cmos_read(CMOS_POST_BANK_0_OFFSET);
#if CONFIG_CMOS_POST_EXTRA
extra = cmos_read32(CMOS_POST_BANK_0_EXTRA);
#endif
break;
}
spin_unlock(&cmos_post_lock);
/* Check last post code in previous boot against normal list */
switch (code) {
case POST_OS_BOOT:
case POST_OS_RESUME:
case POST_ENTER_ELF_BOOT:
case 0:
break;
default:
printk(BIOS_WARNING, "POST: Unexpected post code "
"in previous boot: 0x%02x\n", code);
#if CONFIG_ELOG
elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code);
#if CONFIG_CMOS_POST_EXTRA
if (extra)
elog_add_event_dword(ELOG_TYPE_POST_EXTRA, extra);
#endif
#endif
}
}
void
podulebus_readcmos(struct podulebus_attach_args *pa, u_int8_t *c)
{
int i;
for (i = 0; i < 4; i++)
c[i] = cmos_read(PODULE_CMOS_BASE +
pa->pa_slotnum * PODULE_CMOS_PERSLOT + i);
}
int cmos_year() {
// algorthm patended my microsoft. beware!
// don't read the code below, ah! you already
// did it. no problem, they can still brainwash you...
int off = bcd2int(cmos_read(0x9));
if(off >= 70 )
return 1990 + off;
else
return 2000 + off;
}
unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def)
{
#if CONFIG_USE_OPTION_TABLE
unsigned byte;
byte = cmos_read(start/8);
return (byte >> (start & 7U)) & ((1U << size) - 1U);
#else
return def;
#endif
}
static int cmos_chksum_valid(void)
{
#if CONFIG_USE_OPTION_TABLE
unsigned char addr;
u16 sum, old_sum;
sum = 0;
/* Compute the cmos checksum */
for(addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {
sum += cmos_read(addr);
}
/* Read the stored checksum */
old_sum = cmos_read(LB_CKS_LOC) << 8;
old_sum |= cmos_read(LB_CKS_LOC+1);
return sum == old_sum;
#else
return 0;
#endif
}
static void cmos_get_date_time(struct tm *date)
{
int sec, min, hour, mday, mon, year;
time_t ts;
struct tm dummy;
sec = cmos_read(RTC_SECONDS);
min = cmos_read(RTC_MINUTES);
hour = cmos_read(RTC_HOURS);
mday = cmos_read(RTC_DAY_OF_MONTH);
mon = cmos_read(RTC_MONTH);
year = cmos_read(RTC_YEAR);
sec = bcd2dec(sec);
min = bcd2dec(min);
hour = bcd2dec(hour);
mday = bcd2dec(mday);
mon = bcd2dec(mon);
year = bcd2dec(year);
ts = time(NULL);
localtime_r(&ts, &dummy);
date->tm_isdst = dummy.tm_isdst;
date->tm_sec = sec;
date->tm_min = min;
date->tm_hour = hour;
date->tm_mday = mday;
date->tm_mon = mon - 1;
date->tm_year = base_year + year - 1900;
date->tm_gmtoff = 0;
ts = mktime(date);
}
static void fill_rtcdate(struct rtcdate *r)
{
r->second = cmos_read(SECS);
r->minute = cmos_read(MINS);
r->hour = cmos_read(HOURS);
r->day = cmos_read(DAY);
r->month = cmos_read(MONTH);
r->year = cmos_read(YEAR);
}
static void cmos_get_date_time(struct tm *date)
{
int base_year = 2000, hour_offset;
int sec, min, hour, mday, mon, year;
time_t ts;
struct tm dummy;
sec = cmos_read(RTC_SECONDS);
min = cmos_read(RTC_MINUTES);
hour = cmos_read(RTC_HOURS);
mday = cmos_read(RTC_DAY_OF_MONTH);
mon = cmos_read(RTC_MONTH);
year = cmos_read(RTC_YEAR);
if ((cmos_read(RTC_REG_B) & REG_B_DM) == 0) {
sec = bcd2dec(sec);
min = bcd2dec(min);
hour = bcd2dec(hour);
mday = bcd2dec(mday);
mon = bcd2dec(mon);
year = bcd2dec(year);
hour_offset = 80;
} else {
hour_offset = 0x80;
}
if ((cmos_read(0x0B) & REG_B_24H) == 0) {
if (hour >= hour_offset) {
hour -= hour_offset;
hour += 12;
}
}
ts = time(NULL);
localtime_r(&ts, &dummy);
date->tm_isdst = dummy.tm_isdst;
date->tm_sec = sec;
date->tm_min = min;
date->tm_hour = hour;
date->tm_mday = mday;
date->tm_mon = mon - 1;
date->tm_year = base_year + year - 1900;
date->tm_gmtoff = 0;
ts = mktime(date);
}
void post_log_extra(u32 value)
{
spin_lock(&cmos_post_lock);
switch (cmos_read(CMOS_POST_BANK_OFFSET)) {
case CMOS_POST_BANK_0_MAGIC:
cmos_write32(CMOS_POST_BANK_0_EXTRA, value);
break;
case CMOS_POST_BANK_1_MAGIC:
cmos_write32(CMOS_POST_BANK_1_EXTRA, value);
break;
}
spin_unlock(&cmos_post_lock);
}
static void cmos_post_code(u8 value)
{
spin_lock(&cmos_post_lock);
switch (cmos_read(CMOS_POST_BANK_OFFSET)) {
case CMOS_POST_BANK_0_MAGIC:
cmos_write(value, CMOS_POST_BANK_0_OFFSET);
break;
case CMOS_POST_BANK_1_MAGIC:
cmos_write(value, CMOS_POST_BANK_1_OFFSET);
break;
}
spin_unlock(&cmos_post_lock);
}
static void get_timed(struct tm *now)
{
now->tm_sec = BCD2BIN(cmos_read(0x0));
now->tm_min = BCD2BIN(cmos_read(0x2));
now->tm_hour = BCD2BIN(cmos_read(0x4));
now->tm_mday = BCD2BIN(cmos_read(0x7));
now->tm_mon = BCD2BIN(cmos_read(0x8));
now->tm_year = BCD2BIN(cmos_read(0x9));
now->tm_mon--;
}
static void main(unsigned long bist)
{
u8 boot_mode;
const char *default_filenames =
"normal/romstage\0fallback/romstage";
if (boot_cpu()) {
bootblock_mainboard_init();
#if CONFIG_USE_OPTION_TABLE
sanitize_cmos();
#endif
boot_mode = do_normal_boot();
} else {
/* Questionable single byte read from CMOS.
* Do not add any other CMOS access in the
* bootblock for AP CPUs.
*/
boot_mode = boot_use_normal(cmos_read(RTC_BOOT_BYTE));
}
char *normal_candidate = (char *)walkcbfs("coreboot-stages");
if (!normal_candidate)
normal_candidate = default_filenames;
unsigned long entry;
if (boot_mode) {
entry = findstage(normal_candidate);
if (entry)
call(entry, bist);
}
entry = findstage(get_fallback(normal_candidate));
if (entry)
call(entry, bist);
/* duh. we're stuck */
halt();
}
void read_vbnv_cmos(uint8_t *vbnv_copy)
{
int i;
for (i = 0; i < VBOOT_VBNV_BLOCK_SIZE; i++)
vbnv_copy[i] = cmos_read(CONFIG_VBOOT_VBNV_OFFSET + 14 + i);
if (IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS_BACKUP_TO_FLASH)) {
if (verify_vbnv(vbnv_copy))
return;
printk(BIOS_INFO, "VBNV: CMOS invalid, restoring from flash\n");
read_vbnv_flash(vbnv_copy);
if (verify_vbnv(vbnv_copy)) {
clear_vbnv_battery_cutoff_flag(vbnv_copy);
save_vbnv_cmos(vbnv_copy);
printk(BIOS_INFO, "VBNV: Flash backup restored\n");
} else {
printk(BIOS_INFO, "VBNV: Restore from flash failed\n");
}
}
}
static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save)
{
u16 pm1_sts;
volatile u8 cmos_status;
pm1_sts = reset_pm1_status();
dump_pm1_status(pm1_sts);
/* While OSPM is not active, poweroff immediately
* on a power button event.
*/
if (pm1_sts & PWRBTN_STS) {
// power button pressed
u32 reg32;
reg32 = (7 << 10) | (1 << 13);
outl(reg32, pmbase + PM1_CNT);
}
if (pm1_sts & RTC_STS) {
/* read RTC status register to disable the interrupt */
cmos_status = cmos_read(RTC_REG_C);
printk(BIOS_DEBUG, "RTC IRQ status: %02X\n", cmos_status);
}
}
int mainboard_should_reset_usb(int s3resume)
{
if (s3resume) {
/*
* For Stumpy the back USB ports are reset on resume
* so default to resetting the controller to make the
* kernel happy. There is a CMOS flag to disable the
* controller reset in case the kernel can tolerate
* the device power loss better in the future.
*/
u8 magic = cmos_read(CMOS_USB_RESET_DISABLE);
if (magic == USB_RESET_DISABLE_MAGIC) {
printk(BIOS_DEBUG, "USB Controller Reset Disabled\n");
return 0;
} else {
printk(BIOS_DEBUG, "USB Controller Reset Enabled\n");
return 1;
}
} else {
/* Ensure USB reset on resume is enabled at boot */
cmos_write(0, CMOS_USB_RESET_DISABLE);
return 1;
}
}
int cmos_day_of_month() {
return bcd2int(cmos_read(0x7));
}
int cmos_seconds() {
return bcd2int(cmos_read(0x0));
}
static int cmos_bcd ( void )
{
return cmos_read(CMOS_STATUSB) & 0x02 ;
}
int cmos_month() {
return bcd2int(cmos_read(0x8));
}
int cmos_minutes() {
return bcd2int(cmos_read(0x2));
}
int cmos_hours() {
return bcd2int(cmos_read(0x4));
}
int cmos_day_of_week() {
return bcd2int(cmos_read(0x6));
}
void main(unsigned long bist)
{
int boot_mode = 0;
int cbmem_was_initted;
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.smbusbar = SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBABASE,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
.thermalbase = 0xfed08000,
.system_type = 0, // 0 Mobile, 1 Desktop/Server
.tseg_size = CONFIG_SMM_TSEG_SIZE,
.spd_addresses = { 0xa0, 0x00,0xa4,0x00 },
.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
.ec_present = 0,
// 0 = leave channel enabled
// 1 = disable dimm 0 on channel
// 2 = disable dimm 1 on channel
// 3 = disable dimm 0+1 on channel
.dimm_channel0_disabled = 2,
.dimm_channel1_disabled = 2,
.max_ddr3_freq = 1333,
.usb_port_config = {
{ 1, 0, 0x0080 }, /* P0: Front port (OC0) */
{ 1, 1, 0x0040 }, /* P1: Back port (OC1) */
{ 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */
{ 1, 0, 0x0040 }, /* P3: MMC (no OC) */
{ 1, 2, 0x0080 }, /* P4: Front port (OC2) */
{ 0, 0, 0x0000 }, /* P5: Empty */
{ 0, 0, 0x0000 }, /* P6: Empty */
{ 0, 0, 0x0000 }, /* P7: Empty */
{ 1, 4, 0x0040 }, /* P8: Back port (OC4) */
{ 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */
{ 1, 4, 0x0040 }, /* P10: BLUETOOTH (no OC) */
{ 0, 4, 0x0000 }, /* P11: Empty */
{ 1, 6, 0x0040 }, /* P12: Back port (OC6) */
{ 1, 5, 0x0040 }, /* P13: Back port (OC5) */
},
};
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
if (bist == 0)
enable_lapic();
pch_enable_lpc();
/* Enable GPIOs */
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
setup_pch_gpios(&stumpy_gpio_map);
setup_sio_gpios();
/* Early SuperIO setup */
it8772f_ac_resume_southbridge(DUMMY_DEV);
ite_kill_watchdog(GPIO_DEV);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
init_bootmode_straps();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected\n");
boot_mode = 1;
/* System is not happy after keyboard reset... */
printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
outb(0x6, 0xcf9);
halt();
}
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
post_code(0x38);
/* Enable SPD ROMs and DDR-III DRAM */
enable_smbus();
/* Prepare USB controller early in S3 resume */
if (boot_mode == 2) {
/*
* For Stumpy the back USB ports are reset on resume
* so default to resetting the controller to make the
* kernel happy. There is a CMOS flag to disable the
* controller reset in case the kernel can tolerate
* the device power loss better in the future.
*/
u8 magic = cmos_read(CMOS_USB_RESET_DISABLE);
if (magic == USB_RESET_DISABLE_MAGIC) {
printk(BIOS_DEBUG, "USB Controller Reset Disabled\n");
enable_usb_bar();
} else {
printk(BIOS_DEBUG, "USB Controller Reset Enabled\n");
}
} else {
/* Ensure USB reset on resume is enabled at boot */
cmos_write(0, CMOS_USB_RESET_DISABLE);
}
post_code(0x39);
pei_data.boot_mode = boot_mode;
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(&pei_data);
timestamp_add_now(TS_AFTER_INITRAM);
post_code(0x3a);
/* Perform some initialization that must run before stage2 */
early_pch_init();
post_code(0x3b);
rcba_config();
post_code(0x3c);
quick_ram_check();
post_code(0x3e);
cbmem_was_initted = !cbmem_recovery(boot_mode==2);
if (boot_mode!=2)
save_mrc_data(&pei_data);
if (boot_mode==2 && !cbmem_was_initted) {
/* Failed S3 resume, reset to come up cleanly */
outb(0x6, 0xcf9);
halt();
}
northbridge_romstage_finalize(boot_mode==2);
post_code(0x3f);
if (CONFIG_LPC_TPM) {
init_tpm(boot_mode == 2);
}
}
