static void aza_init(struct device *dev)
{
u8 *base;
struct resource *res;
u32 codec_mask;
printk(BIOS_DEBUG, "AZALIA_INIT:---------->\n");
//-------------- enable AZA (SiS7502) -------------------------
{
u8 temp8;
int i=0;
while(SiS_SiS7502_init[i][0] != 0)
{
temp8 = pci_read_config8(dev, SiS_SiS7502_init[i][0]);
temp8 &= SiS_SiS7502_init[i][1];
temp8 |= SiS_SiS7502_init[i][2];
pci_write_config8(dev, SiS_SiS7502_init[i][0], temp8);
i++;
};
}
//-----------------------------------------------------------
// put audio to D0 state
pci_write_config8(dev, 0x54,0x00);
#if DEBUG_AZA
{
int i;
printk(BIOS_DEBUG, "****** Azalia PCI config ******");
printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
for(i=0;i<0xff;i+=4){
if((i%16)==0){
printk(BIOS_DEBUG, "\n%02x: ", i);
}
printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
}
printk(BIOS_DEBUG, "\n");
}
#endif
res = find_resource(dev, 0x10);
if(!res)
return;
base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "base = 0x%p\n", base);
codec_mask = codec_detect(base);
if(codec_mask) {
printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask);
codecs_init(base, codec_mask);
}
printk(BIOS_DEBUG, "AZALIA_INIT:<----------\n");
}
static void azalia_init(struct device *dev)
{
#if IS_ENABLED(CONFIG_MCP55_USE_AZA)
u8 *base;
u32 codec_mask, reg32;
struct resource *res;
u8 reg8;
/* Set bus master. */
reg32 = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
pci_write_config8(dev, 0x3c, 0x0a); // TODO: Unused?
reg8 = pci_read_config8(dev, 0x40);
reg8 |= (1 << 3); /* Clear Clock Detect bit. */
pci_write_config8(dev, 0x40, reg8);
reg8 &= ~(1 << 3); /* Keep CLKDETCLR from clearing the bit over and over. */
pci_write_config8(dev, 0x40, reg8);
reg8 |= (1 << 2); /* Enable clock detection. */
pci_write_config8(dev, 0x40, reg8);
mdelay(1);
reg8 = pci_read_config8(dev, 0x40);
printk(BIOS_DEBUG, "Azalia: codec type: %s\n",
(reg8 & (1 << 1)) ? "Azalia" : "AC97");
reg8 = pci_read_config8(dev, 0x40); /* Audio control */
reg8 |= 1; /* Select Azalia mode. TODO: Control via devicetree.cb. */
pci_write_config8(dev, 0x40, reg8);
reg8 = pci_read_config8(dev, 0x4d); /* Docking status. */
reg8 &= ~(1 << 7); /* Docking not supported. */
pci_write_config8(dev, 0x4d, reg8);
res = find_resource(dev, 0x10);
if (!res)
return;
/*
* NOTE: This will break as soon as the Azalia gets a BAR above
* 4G. Is there anything we can do about it?
*/
base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
codec_mask = codec_detect(base);
if (codec_mask) {
printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
codecs_init(dev, base, codec_mask);
}
#endif
}
static void hda_init(struct device *dev)
{
u8 byte;
u32 dword;
u32 base;
struct resource *res;
u32 codec_mask;
device_t sm_dev;
/* Enable azalia - PM_io 0x59[3], no ac97 in sb700. */
byte = pm_ioread(0x59);
byte |= 1 << 3;
pm_iowrite(0x59, byte);
/* Find the SMBus */
/* FIXME: Need to find out why the call below crashes. */
/*sm_dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_ATI_SB700_SM, 0);*/
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
/* Set routing pin - SMBus ExtFunc (0xf8/0xfc) */
pci_write_config32(sm_dev, 0xf8, 0x00);
pci_write_config8(sm_dev, 0xfc, 0xAA);
/* Set INTA - SMBus 0x63 [2..0] */
byte = pci_read_config8(sm_dev, 0x63);
byte &= ~0x7;
byte |= 0x0; /* INTA:0x0 - INTH:0x7 */
pci_write_config8(sm_dev, 0x63, byte);
/* Program the 2C to 0x437b1002 */
dword = 0x437b1002;
pci_write_config32(dev, 0x2c, dword);
/* Read in BAR */
/* Is this right? HDA allows for a 64-bit BAR
* but this is only setup for a 32-bit one
*/
res = find_resource(dev, 0x10);
if (!res)
return;
base = (u32)res->base;
printk(BIOS_DEBUG, "base = 0x%x\n", base);
codec_mask = codec_detect(base);
if (codec_mask) {
printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask);
codecs_init(base, codec_mask);
}
}
static void hda_init(struct device *dev)
{
u8 byte;
u32 dword;
void *base;
struct resource *res;
u32 codec_mask;
device_t sm_dev;
/* Enable azalia - PM_io 0x59[4], disable ac97 - PM_io 0x59[1..0] */
pm_iowrite(0x59, 0xB);
/* Find the SMBus */
sm_dev = dev_find_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_SM, 0);
/* Set routing pin - SMBus ExtFunc (0xf8/0xfc) */
pci_write_config32(sm_dev, 0xf8, 0x00);
pci_write_config8(sm_dev, 0xfc, 0xAA);
/* Set INTA - SMBus 0x63 [2..0] */
byte = pci_read_config8(sm_dev, 0x63);
byte &= ~0x7;
byte |= 0x0; /* INTA:0x0 - INTH:0x7 */
pci_write_config8(sm_dev, 0x63, byte);
/* Program the 2C to 0x437b1002 */
dword = 0x437b1002;
pci_write_config32(dev, 0x2c, dword);
/* Read in BAR */
/* Is this right? HDA allows for a 64-bit BAR
* but this is only setup for a 32-bit one
*/
res = find_resource(dev, 0x10);
if (!res)
return;
base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "base = 0x%p\n", base);
codec_mask = codec_detect(base);
if (codec_mask) {
printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask);
codecs_init(base, codec_mask);
}
}
void azalia_audio_init(struct device *dev)
{
u8 *base;
struct resource *res;
u32 codec_mask;
res = find_resource(dev, 0x10);
if (!res)
return;
// NOTE this will break as soon as the azalia_audio get's a bar above
// 4G. Is there anything we can do about it?
base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "azalia_audio: base = %p\n", base);
codec_mask = codec_detect(base);
if (codec_mask) {
printk(BIOS_DEBUG, "azalia_audio: codec_mask = %02x\n",
codec_mask);
codecs_init(dev, base, codec_mask);
}
}
static void azalia_init(struct device *dev)
{
u32 base;
struct resource *res;
u32 codec_mask;
u8 reg8;
u16 reg16;
u32 reg32;
/* Find base address */
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (!res)
return;
// NOTE this will break as soon as the Azalia get's a bar above
// 4G. Is there anything we can do about it?
base = (u32)res->base;
printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
if (RCBA32(0x2030) & (1 << 31)) {
reg32 = pci_read_config32(dev, 0x120);
reg32 &= 0xf8ffff01;
reg32 |= (1 << 24); // 2 << 24 for server
reg32 |= RCBA32(0x2030) & 0xfe;
pci_write_config32(dev, 0x120, reg32);
reg16 = pci_read_config16(dev, 0x78);
reg16 |= (1 << 11);
pci_write_config16(dev, 0x78, reg16);
} else
printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n");
reg32 = pci_read_config32(dev, 0x114);
reg32 &= ~0xfe;
pci_write_config32(dev, 0x114, reg32);
// Set VCi enable bit
reg32 = pci_read_config32(dev, 0x120);
reg32 |= (1 << 31);
pci_write_config32(dev, 0x120, reg32);
// Enable HDMI codec:
reg32 = pci_read_config32(dev, 0xc4);
reg32 |= (1 << 1);
pci_write_config32(dev, 0xc4, reg32);
reg8 = pci_read_config8(dev, 0x43);
reg8 |= (1 << 6);
pci_write_config8(dev, 0x43, reg8);
/* Additional programming steps */
reg32 = pci_read_config32(dev, 0xc4);
reg32 |= (1 << 13);
pci_write_config32(dev, 0xc4, reg32);
reg32 = pci_read_config32(dev, 0xc4);
reg32 |= (1 << 10);
pci_write_config32(dev, 0xc4, reg32);
reg32 = pci_read_config32(dev, 0xd0);
reg32 &= ~(1 << 31);
pci_write_config32(dev, 0xd0, reg32);
if (dev->device == 0x1e20) {
/* Additional step on Panther Point */
reg32 = pci_read_config32(dev, 0xc4);
reg32 |= (1 << 17);
pci_write_config32(dev, 0xc4, reg32);
}
/* Set Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
pci_write_config8(dev, 0x3c, 0x0a); // unused?
/* Codec Initialization Programming Sequence */
/* Take controller out of reset */
reg32 = read32(base + 0x08);
reg32 |= (1 << 0);
write32(base + 0x08, reg32);
/* Wait 1ms */
udelay(1000);
//
reg8 = pci_read_config8(dev, 0x40); // Audio Control
reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb
pci_write_config8(dev, 0x40, reg8);
reg8 = pci_read_config8(dev, 0x4d); // Docking Status
reg8 &= ~(1 << 7); // Docking not supported
pci_write_config8(dev, 0x4d, reg8);
codec_mask = codec_detect(base);
if (codec_mask) {
printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
codecs_init(dev, base, codec_mask);
}
/* Enable dynamic clock gating */
reg8 = pci_read_config8(dev, 0x43);
reg8 &= ~0x7;
reg8 |= (1 << 2) | (1 << 0);
pci_write_config8(dev, 0x43, reg8);
}
static void azalia_init(struct device *dev)
{
u32 base;
struct resource *res;
u32 codec_mask;
u8 reg8;
u32 reg32;
#if CONFIG_MMCONF_SUPPORT
// ESD
reg32 = pci_mmio_read_config32(dev, 0x134);
reg32 &= 0xff00ffff;
reg32 |= (2 << 16);
pci_mmio_write_config32(dev, 0x134, reg32);
// Link1 description
reg32 = pci_mmio_read_config32(dev, 0x140);
reg32 &= 0xff00ffff;
reg32 |= (2 << 16);
pci_mmio_write_config32(dev, 0x140, reg32);
// Port VC0 Resource Control Register
reg32 = pci_mmio_read_config32(dev, 0x114);
reg32 &= 0xffffff00;
reg32 |= 1;
pci_mmio_write_config32(dev, 0x114, reg32);
// VCi traffic class
reg8 = pci_mmio_read_config8(dev, 0x44);
reg8 |= (7 << 0); // TC7
pci_mmio_write_config8(dev, 0x44, reg8);
// VCi Resource Control
reg32 = pci_mmio_read_config32(dev, 0x120);
reg32 |= (1 << 31);
reg32 |= (1 << 24); // VCi ID
reg32 |= (0x80 << 0); // VCi map
pci_mmio_write_config32(dev, 0x120, reg32);
#else
#error ICH7 Azalia required CONFIG_MMCONF_SUPPORT
#endif
/* Set Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
pci_write_config8(dev, 0x3c, 0x0a); // unused?
// TODO Actually check if we're AC97 or HDA instead of hardcoding this
// here, in devicetree.cb and/or romstage.c.
reg8 = pci_read_config8(dev, 0x40);
reg8 |= (1 << 3); // Clear Clock Detect Bit
pci_write_config8(dev, 0x40, reg8);
reg8 &= ~(1 << 3); // Keep CLKDETCLR from clearing the bit over and over
pci_write_config8(dev, 0x40, reg8);
reg8 |= (1 << 2); // Enable clock detection
pci_write_config8(dev, 0x40, reg8);
mdelay(1);
reg8 = pci_read_config8(dev, 0x40);
printk(BIOS_DEBUG, "Azalia: codec type: %s\n", (reg8 & (1 << 1))?"Azalia":"AC97");
//
reg8 = pci_read_config8(dev, 0x40); // Audio Control
reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb
pci_write_config8(dev, 0x40, reg8);
reg8 = pci_read_config8(dev, 0x4d); // Docking Status
reg8 &= ~(1 << 7); // Docking not supported
pci_write_config8(dev, 0x4d, reg8);
#if 0
/* Set routing pin */
pci_write_config32(dev, 0xf8, 0x0);
pci_write_config8(dev, 0xfc, 0xAA);
/* Set INTA */
pci_write_config8(dev, 0x63, 0x0);
/* Enable azalia, disable ac97 */
// pm_iowrite(0x59, 0xB);
#endif
res = find_resource(dev, 0x10);
if (!res)
return;
// NOTE this will break as soon as the Azalia get's a bar above
// 4G. Is there anything we can do about it?
base = (u32)res->base;
printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
codec_mask = codec_detect(base);
if (codec_mask) {
printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
codecs_init(dev, base, codec_mask);
}
}
static void azalia_init(struct device *dev)
{
u32 base;
struct resource *res;
u32 codec_mask;
u8 reg8;
u32 reg32;
// ESD
reg32 = pci_read_config32(dev, 0x134);
reg32 &= 0xff00ffff;
reg32 |= (2 << 16);
pci_write_config32(dev, 0x134, reg32);
// Link1 description
reg32 = pci_read_config32(dev, 0x140);
reg32 &= 0xff00ffff;
reg32 |= (2 << 16);
pci_write_config32(dev, 0x140, reg32);
// Port VC0 Resource Control Register
reg32 = pci_read_config32(dev, 0x114);
reg32 &= 0xffffff00;
reg32 |= 1;
pci_write_config32(dev, 0x114, reg32);
// VCi traffic class
reg8 = pci_read_config8(dev, 0x44);
reg8 |= (7 << 0); // TC7
pci_write_config8(dev, 0x44, reg8);
// VCi Resource Control
reg32 = pci_read_config32(dev, 0x120);
reg32 |= (1 << 31);
reg32 |= (1 << 24); // VCi ID
reg32 |= (0x80 << 0); // VCi map
pci_write_config32(dev, 0x120, reg32);
/* Set Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
reg8 = pci_read_config8(dev, 0x4d); // Docking Status
reg8 &= ~(1 << 7); // Docking not supported
pci_write_config8(dev, 0x4d, reg8);
/* Lock some R/WO bits by writing their current value. */
reg32 = pci_read_config32(dev, 0x74);
pci_write_config32(dev, 0x74, reg32);
res = find_resource(dev, 0x10);
if (!res)
return;
// NOTE this will break as soon as the Azalia get's a bar above
// 4G. Is there anything we can do about it?
base = (u32)res->base;
printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
codec_mask = codec_detect(base);
if (codec_mask) {
printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
codecs_init(dev, base, codec_mask);
}
}
