inline T exchange(T value, MemoryOrder order = MEMORY_ORDER_SEQ_CST) volatile {
#if defined(__x86_64__) || defined(__i386__) // See below
    // The atomic exchange below only has MEMORY_ORDER_ACQUIRE semantics
    if ((order & MEMORY_ORDER_RELEASE) != 0) {
      __sync_synchronize();
    }
    // According to GCC this may only support storing the immediate value of 1 on some
    // platforms, but is an atomic exchange operation on Intel processors.
    return __sync_lock_test_and_set(&value_, value);
#else
    T before = load(MEMORY_ORDER_RELAXED);
    while (!compare_exchange_weak(before, before, order)) {}
    return before;
#endif
  }
	T exchange(T r, memory_order order=memory_order_seq_cst) volatile
	{
		T expected=(T)i;
		do { } while(!compare_exchange_weak(expected, r, order, memory_order_relaxed));
		return expected;
	}