void Nrf24l::powerUpRx(){
PTX = 0;
ceLow();
configRegister(CONFIG, mirf_CONFIG | ( (1<<PWR_UP) | (1<<PRIM_RX) ) );
ceHi();
configRegister(STATUS,(1 << TX_DS) | (1 << MAX_RT));
}
void Nrf24l::powerUpRx() {
PTX = 0;
ceLow();
configRegister(CONFIG, baseConfig | _BV(PWR_UP) | _BV(PRIM_RX));
configRegister(STATUS, _BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT));
ceHi();
}
// 上电
void Nrf24l::powerUpRx(){
PTX = 0;
ceLow();
// 使用 ‘0’-8 位CRC 校验模式，开启1:上电模式，开启接收模式
configRegister(CONFIG, mirf_CONFIG | ( (1<<PWR_UP) | (1<<PRIM_RX) ) );
ceHi();
// 清除之前的数据发送完成中断。不是关闭中断
// 当数据发送完成后产生中断。如果工作在自动应答模式下，
// 只有当接收到应答信号后此位置一。写‘1’清除中断。
// 清除之前的达到最多次重发中断。不是关闭中断
// 写‘1’清除中断。如果MAX_RT 中断产生则必须清除后系统才能进行通讯。
configRegister(STATUS,(1 << TX_DS) | (1 << MAX_RT));
}
extern void Nrf24l::getData(uint8_t * data)
// Reads payload bytes into data array
//读RX 有效数据：1-32 字节。读操作全部从字节0 开始。当读RX
//有效数据完成后，FIFO 寄存器中有效数据被清除。
//应用于接收模式下。
{
csnLow(); // Pull down chip select
spi->transfer( R_RX_PAYLOAD ); // Send cmd to read rx payload
transferSync(data,data,payload); // Read payload
csnHi(); // Pull up chip select
// NVI: per product spec, p 67, note c:
// "The RX_DR IRQ is asserted by a new packet arrival event. The procedure
// for handling this interrupt should be: 1) read payload through SPI,
// 2) clear RX_DR IRQ, 3) read FIFO_STATUS to check if there are more
// payloads available in RX FIFO, 4) if there are more data in RX FIFO,
// repeat from step 1)."
// So if we're going to clear RX_DR here, we need to check the RX FIFO
// in the dataReady() function
// NVI：每个产品的规格，第67页，注三：
//“的RX_DR IRQ是断言一个新的数据包到达事件的过程
//处理这个中断应该是：1）通过SPI读取有效负载，
//2）明确RX_DR IRQ，3）读FIFO_STATUS，以检查是否有更多的
//在RX FIFO中可用的有效载荷，4）如果在RX FIFO更多的数据，
//重复从步骤1开始）。“
//所以，如果我们要在这里清除RX_DR，我们需要检查RX FIFO
//在dataReady（）函数
configRegister(STATUS,(1<<RX_DR)); // Reset status register
}
void Nrf24l::config()
// Sets the important registers in the MiRF module and powers the module
// in receiving mode
// NB: channel and payload must be set now.
{
// Set RF channel
configRegister(RF_CH,channel);
// Set length of incoming payload
configRegister(RX_PW_P0, payload);
configRegister(RX_PW_P1, payload);
// Start receiver
powerUpRx();
flushRx();
}
void Nrf24l::powerDown(){
ceLow();
configRegister(CONFIG, baseConfig);
flushRx();
flushTx();
}
void Nrf24l::getData(uint8_t * data)
// Reads payload bytes into data array
{
nrfSpiWrite(R_RX_PAYLOAD, data, true, payload); // Read payload
// NVI: per product spec, p 67, note c:
// "The RX_DR IRQ is asserted by a new packet arrival event. The procedure
// for handling this interrupt should be: 1) read payload through SPI,
// 2) clear RX_DR IRQ, 3) read FIFO_STATUS to check if there are more
// payloads available in RX FIFO, 4) if there are more data in RX FIFO,
// repeat from step 1)."
// So if we're going to clear RX_DR here, we need to check the RX FIFO
// in the dataReady() function
configRegister(STATUS, _BV(RX_DR)); // Reset status register
}
extern void Nrf24l::getData(uint8_t * data)
// Reads payload bytes into data array
{
csnLow(); // Pull down chip select
spi->transfer( R_RX_PAYLOAD ); // Send cmd to read rx payload
transferSync(data,data,payload); // Read payload
csnHi(); // Pull up chip select
// NVI: per product spec, p 67, note c:
// "The RX_DR IRQ is asserted by a new packet arrival event. The procedure
// for handling this interrupt should be: 1) read payload through SPI,
// 2) clear RX_DR IRQ, 3) read FIFO_STATUS to check if there are more
// payloads available in RX FIFO, 4) if there are more data in RX FIFO,
// repeat from step 1)."
// So if we're going to clear RX_DR here, we need to check the RX FIFO
// in the dataReady() function
configRegister(STATUS,(1<<RX_DR)); // Reset status register
}
void Nrf24l::powerDown(){
// 掉电模式
ceLow();
configRegister(CONFIG, mirf_CONFIG );
}
void Nrf24l::powerUpTx(){
// 上电 发送模式 1 0 1 数据在TX FIFO 寄存器中
PTX = 1;
configRegister(CONFIG, mirf_CONFIG | ( (1<<PWR_UP) | (0<<PRIM_RX) ) );
}
void Nrf24l::powerUpTx() {
PTX = 1;
configRegister(CONFIG, baseConfig | _BV(PWR_UP) & ~_BV(PRIM_RX));
}
void Nrf24l::powerUpTx(){
PTX = 1;
configRegister(CONFIG, mirf_CONFIG | ( (1<<PWR_UP) | (0<<PRIM_RX) ) );
}
