/******************************************************************************* * Perform the very early platform specific architectural setup here. At the * moment this is only intializes the mmu in a quick and dirty way. ******************************************************************************/ void bl31_plat_arch_setup() { configure_mmu(&bl2_to_bl31_args->bl31_meminfo, BL31_RO_BASE, BL31_RO_LIMIT, BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT); }
/******************************************************************************* * Perform the very early platform specific architectural setup here. At the * moment this is only intializes the mmu in a quick and dirty way. ******************************************************************************/ void bl2_plat_arch_setup() { configure_mmu(&bl2_tzram_layout, BL2_RO_BASE, BL2_RO_LIMIT, BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT); }
/******************************************************************************* * Perform the very early platform specific architecture setup here. At the * moment this only does basic initialization. Later architectural setup * (bl1_arch_setup()) does not do anything platform specific. ******************************************************************************/ void bl1_plat_arch_setup(void) { unsigned long cci_setup; /* * Enable CCI-400 for this cluster. No need * for locks as no other cpu is active at the * moment */ cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI); if (cci_setup) { cci_enable_coherency(read_mpidr()); } configure_mmu(&bl1_tzram_layout, TZROM_BASE, TZROM_BASE + TZROM_SIZE, BL1_COHERENT_RAM_BASE, BL1_COHERENT_RAM_LIMIT); }