void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
{
struct platform_device *pdev;
struct atmel_uart_data *pdata;
switch (id) {
case 0: /* DBGU */
pdev = &at91rm9200_dbgu_device;
configure_dbgu_pins();
break;
case AT91RM9200_ID_US0:
pdev = &at91rm9200_uart0_device;
configure_usart0_pins(pins);
break;
case AT91RM9200_ID_US1:
pdev = &at91rm9200_uart1_device;
configure_usart1_pins(pins);
break;
case AT91RM9200_ID_US2:
pdev = &at91rm9200_uart2_device;
configure_usart2_pins(pins);
break;
case AT91RM9200_ID_US3:
pdev = &at91rm9200_uart3_device;
configure_usart3_pins(pins);
break;
default:
return;
}
pdata = pdev->dev.platform_data;
pdata->num = portnr; /* update to mapped ID */
if (portnr < ATMEL_MAX_UART)
at91_uarts[portnr] = pdev;
}
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
{
struct platform_device *pdev;
switch (id) {
case 0: /* DBGU */
pdev = &at91cap9_dbgu_device;
configure_dbgu_pins();
at91_clock_associate("mck", &pdev->dev, "usart");
break;
case AT91CAP9_ID_US0:
pdev = &at91cap9_uart0_device;
configure_usart0_pins(pins);
at91_clock_associate("usart0_clk", &pdev->dev, "usart");
break;
case AT91CAP9_ID_US1:
pdev = &at91cap9_uart1_device;
configure_usart1_pins(pins);
at91_clock_associate("usart1_clk", &pdev->dev, "usart");
break;
case AT91CAP9_ID_US2:
pdev = &at91cap9_uart2_device;
configure_usart2_pins(pins);
at91_clock_associate("usart2_clk", &pdev->dev, "usart");
break;
default:
return;
}
pdev->id = portnr; /* update to mapped ID */
if (portnr < ATMEL_MAX_UART)
at91_uarts[portnr] = pdev;
}
void __init at32_map_usart(unsigned int hw_id, unsigned int line)
{
struct platform_device *pdev;
switch (hw_id) {
case 0:
pdev = &atmel_usart0_device;
configure_usart0_pins();
break;
case 1:
pdev = &atmel_usart1_device;
configure_usart1_pins();
break;
case 2:
pdev = &atmel_usart2_device;
configure_usart2_pins();
break;
case 3:
pdev = &atmel_usart3_device;
configure_usart3_pins();
break;
default:
return;
}
if (PXSEG(pdev->resource[0].start) == P4SEG) {
/* Addresses in the P4 segment are permanently mapped 1:1 */
struct atmel_uart_data *data = pdev->dev.platform_data;
data->regs = (void __iomem *)pdev->resource[0].start;
}
pdev->id = line;
at32_usarts[line] = pdev;
}
void __init __deprecated at91_init_serial(struct at91_uart_config *config)
{
int i;
/* Fill in list of supported UARTs */
for (i = 0; i < config->nr_tty; i++) {
switch (config->tty_map[i]) {
case 0:
configure_usart0_pins(ATMEL_UART_CTS | ATMEL_UART_RTS | ATMEL_UART_DSR | ATMEL_UART_DTR | ATMEL_UART_DCD | ATMEL_UART_RI);
at91_uarts[i] = &at91sam9260_uart0_device;
at91_clock_associate("usart0_clk", &at91sam9260_uart0_device.dev, "usart");
break;
case 1:
configure_usart1_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
at91_uarts[i] = &at91sam9260_uart1_device;
at91_clock_associate("usart1_clk", &at91sam9260_uart1_device.dev, "usart");
break;
case 2:
configure_usart2_pins(0);
at91_uarts[i] = &at91sam9260_uart2_device;
at91_clock_associate("usart2_clk", &at91sam9260_uart2_device.dev, "usart");
break;
case 3:
configure_usart3_pins(0);
at91_uarts[i] = &at91sam9260_uart3_device;
at91_clock_associate("usart3_clk", &at91sam9260_uart3_device.dev, "usart");
break;
case 4:
configure_usart4_pins();
at91_uarts[i] = &at91sam9260_uart4_device;
at91_clock_associate("usart4_clk", &at91sam9260_uart4_device.dev, "usart");
break;
case 5:
configure_usart5_pins();
at91_uarts[i] = &at91sam9260_uart5_device;
at91_clock_associate("usart5_clk", &at91sam9260_uart5_device.dev, "usart");
break;
case 6:
configure_dbgu_pins();
at91_uarts[i] = &at91sam9260_dbgu_device;
at91_clock_associate("mck", &at91sam9260_dbgu_device.dev, "usart");
break;
default:
continue;
}
at91_uarts[i]->id = i; /* update ID number to mapped ID */
}
/* Set serial console device */
if (config->console_tty < ATMEL_MAX_UART)
atmel_default_console_device = at91_uarts[config->console_tty];
if (!atmel_default_console_device)
printk(KERN_INFO "AT91: No default serial console defined.\n");
}
struct device_d * __init at91_register_uart(unsigned id, unsigned pins)
{
resource_size_t start;
switch (id) {
case 0: /* DBGU */
configure_dbgu_pins();
start = AT91_BASE_SYS + AT91_DBGU;
id = 0;
break;
case AT91SAM9260_ID_US0:
configure_usart0_pins(pins);
start = AT91SAM9260_BASE_US0;
id = 1;
break;
case AT91SAM9260_ID_US1:
configure_usart1_pins(pins);
start = AT91SAM9260_BASE_US1;
id = 2;
break;
case AT91SAM9260_ID_US2:
configure_usart2_pins(pins);
start = AT91SAM9260_BASE_US2;
id = 3;
break;
case AT91SAM9260_ID_US3:
configure_usart3_pins(pins);
start = AT91SAM9260_BASE_US3;
id = 4;
break;
case AT91SAM9260_ID_US4:
configure_usart4_pins();
start = AT91SAM9260_BASE_US4;
id = 5;
break;
case AT91SAM9260_ID_US5:
configure_usart5_pins();
start = AT91SAM9260_BASE_US5;
id = 6;
break;
default:
return NULL;
}
return add_generic_device("atmel_usart", id, NULL, start, 4096,
IORESOURCE_MEM, NULL);
}
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
{
struct platform_device *pdev;
switch (id) {
case 0:
pdev = &at91sam9rl_dbgu_device;
configure_dbgu_pins();
at91_clock_associate("mck", &pdev->dev, "usart");
break;
case AT91SAM9RL_ID_US0:
pdev = &at91sam9rl_uart0_device;
configure_usart0_pins(pins);
at91_clock_associate("usart0_clk", &pdev->dev, "usart");
break;
case AT91SAM9RL_ID_US1:
pdev = &at91sam9rl_uart1_device;
configure_usart1_pins(pins);
at91_clock_associate("usart1_clk", &pdev->dev, "usart");
break;
case AT91SAM9RL_ID_US2:
pdev = &at91sam9rl_uart2_device;
configure_usart2_pins(pins);
at91_clock_associate("usart2_clk", &pdev->dev, "usart");
break;
case AT91SAM9RL_ID_US3:
pdev = &at91sam9rl_uart3_device;
configure_usart3_pins(pins);
at91_clock_associate("usart3_clk", &pdev->dev, "usart");
break;
default:
return;
}
pdev->id = portnr;
if (portnr < ATMEL_MAX_UART)
at91_uarts[portnr] = pdev;
}
