int up_addrenv_coherent(FAR const group_addrenv_t *addrenv)
{
DEBUGASSERT(addrenv);
/* Invalidate I-Cache */
cp15_invalidate_icache();
/* Clean D-Cache in each region.
* REVISIT: Cause crashes when trying to clean unmapped memory. In order
* for this to work, we need to know the exact size of each region (as we
* do now for the heap region).
*/
#warning REVISIT... causes crashes
#if 0
arch_clean_dcache(CONFIG_ARCH_TEXT_VBASE,
CONFIG_ARCH_TEXT_VBASE +
CONFIG_ARCH_TEXT_NPAGES * MM_PGSIZE - 1);
arch_clean_dcache(CONFIG_ARCH_DATA_VBASE,
CONFIG_ARCH_DATA_VBASE +
CONFIG_ARCH_DATA_NPAGES * MM_PGSIZE - 1);
#endif
#ifdef CONFIG_BUILD_KERNEL
arch_clean_dcache(CONFIG_ARCH_HEAP_VBASE,
CONFIG_ARCH_HEAP_VBASE + addrenv->heapsize);
#endif
return OK;
}
int dram_main(int argc, char *argv)
{
/* Here we have a in memory value we can change in the debugger
* to begin booting in NOR Flash
*/
static volatile uint32_t wait = DRAM_BOOT_MODE;
int ret;
/* Disable the PMC. This is necessary on the SAMA5D4-MB Rev C. board. On
* that board, the PMIC can lock up the I2C bus. The work around is
* awkward:
*
* 1. Open JP23 (disabling the WM8904 data line)
* 2. Execute DRAMBOOT. The WM8904 will be disabled while JP23 is open.
* 3. At the prompt to "Send the Intel HEX file now", close JP23,
* enabling the WM8904.
* 4. Send the NuttX file. When NuttX starts, the WM8904 is initialized,
* JP23 will be closed and the PMIC will be initialized.
*/
sam_pmic_initialize();
/* DRAM was already initialized at boot time, so we are ready to load the
* Intel HEX stream into DRAM.
*
* Hmm.. With no hardware handshake, there is a possibility of data loss
* to overrunning incoming data buffer. So far I have not seen this at
* 115200 8N1, but still it is a possibility.
*/
printf("Send Intel HEX file now\n");
fflush(stdout);
ret = hex2mem(0, /* Accept Intel HEX on stdin */
(uint32_t)SAM_DDRCS_VSECTION,
(uint32_t)(SAM_DDRCS_VSECTION + CONFIG_SAMA5_DDRCS_SIZE),
0);
if (ret < 0)
{
/* We failed the load */
printf("ERROR: Intel HEX file load failed: %d\n", ret);
fflush(stdout);
for(;;);
}
/* No success indication.. The following cache/MMU operations will clobber
* any I/O that we attempt (Hmm.. unless, perhaps, if we delayed. But who
* wants a delay?).
*/
/* Flush the entire data cache assure that everything is in memory before
* we disable caching.
*/
arch_clean_dcache((uintptr_t)SAM_DDRCS_VSECTION,
(uintptr_t)(SAM_DDRCS_VSECTION + CONFIG_SAMA5_DDRCS_SIZE));
/* Interrupts must be disabled through the following. In this configuration,
* there should only be timer interrupts. Your NuttX configuration must use
* CONFIG_SERIAL_LOWCONSOLE=y or printf() will hang when the interrupts
* are disabled!
*/
(void)irqsave();
/* Disable the caches and the MMU. Disabling the MMU should be safe here
* because there is a 1-to-1 identity mapping between the physical and
* virtual addressing.
*/
cp15_disable_mmu();
cp15_disable_caches();
/* Invalidate caches and TLBs */
cp15_invalidate_icache();
cp15_invalidate_dcache_all();
cp15_invalidate_tlbs();
/* Then jump into NOR flash */
while (wait)
{
}
DRAM_ENTRY();
return 0; /* We should not get here in either case */
}
int nor_main(int argc, char *argv)
{
uint32_t regval;
/* Here we have a in memory value we can change in the debugger
* to begin booting in NOR Flash
*/
static volatile uint32_t wait = NOR_BOOT_MODE;
printf("Configuring NOR FLASH on CS0 and %s\n", wait ? "waiting" : "booting");
/* Make sure that the SMC peripheral is enabled (But of course it is... we
* are executing from NOR FLASH now).
*/
sam_hsmc_enableclk();
/* The SAMA5D3x-EK has 118MB of 16-bit NOR FLASH at CS0. The NOR FLASH
* has already been configured by the first level ROM bootloader... we
* simply need to modify the timing here.
*/
regval = HSMC_SETUP_NWE_SETUP(1) | HSMC_SETUP_NCS_WRSETUP(0) |
HSMC_SETUP_NRD_SETUP(2) | HSMC_SETUP_NCS_RDSETUP(0);
putreg32(regval, SAM_HSMC_SETUP(HSMC_CS0));
regval = HSMC_PULSE_NWE_PULSE(10) | HSMC_PULSE_NCS_WRPULSE(10) |
HSMC_PULSE_NRD_PULSE(11) | HSMC_PULSE_NCS_RDPULSE(11);
putreg32(regval, SAM_HSMC_PULSE(HSMC_CS0));
regval = HSMC_CYCLE_NWE_CYCLE(11) | HSMC_CYCLE_NRD_CYCLE(14);
putreg32(regval, SAM_HSMC_CYCLE(HSMC_CS0));
regval = HSMC_TIMINGS_TCLR(0) | HSMC_TIMINGS_TADL(0) |
HSMC_TIMINGS_TAR(0) | HSMC_TIMINGS_TRR(0) |
HSMC_TIMINGS_TWB(0) | HSMC_TIMINGS_RBNSEL(0);
putreg32(regval, SAM_HSMC_TIMINGS(HSMC_CS0));
regval = HSMC_MODE_READMODE | HSMC_MODE_WRITEMODE |
HSMC_MODE_EXNWMODE_DISABLED | HSMC_MODE_BIT_16 |
HSMC_MODE_TDFCYCLES(1);
putreg32(regval, SAM_HSMC_MODE(HSMC_CS0));
/* Interrupts must be disabled through the following. In this configuration,
* there should only be timer interrupts. Your NuttX configuration must use
* CONFIG_SERIAL_LOWCONSOLE=y or printf() will hang when the interrupts
* are disabled!
*/
(void)irqsave();
/* Disable MATRIX write protection */
#if 0 /* Disabled on reset */
putreg32(MATRIX_WPMR_WPKEY, SAM_MATRIX_WPMR);
#endif
/* Set remap state 1.
*
* Boot state: ROM is seen at address 0x00000000
* Remap State 0: SRAM is seen at address 0x00000000 (through AHB slave
* interface) instead of ROM.
* Remap State 1: HEBI is seen at address 0x00000000 (through AHB slave
* interface) instead of ROM for external boot.
*
* REVISIT: This does not work. No matter what I do, the internal
* SRAM is always visible at address zero. I am missing something.
*/
putreg32(MATRIX_MRCR_RCB0, SAM_MATRIX_MRCR); /* Enable remap */
putreg32(AXIMX_REMAP_REMAP1, SAM_AXIMX_REMAP); /* Remap HEBI */
/* Restore MATRIX write protection */
#if 0 /* Disabled on reset */
putreg32(MATRIX_WPMR_WPKEY | MATRIX_WPMR_WPEN, SAM_MATRIX_WPMR);
#endif
/* Disable the caches and the MMU. Disabling the MMU should be safe here
* because there is a 1-to-1 identity mapping between the physical and
* virtual addressing.
*/
/* NOTE: This generates crashes and lots of error, but does leave the
* system in the proper state to run from NOR: very ugly but usable.
* Better than the alternative.
*/
cp15_disable_mmu();
cp15_disable_caches();
/* Invalidate caches and TLBs */
cp15_invalidate_icache();
cp15_invalidate_dcache_all();
cp15_invalidate_tlbs();
/* Then jump into NOR flash */
while (wait)
{
}
NOR_ENTRY();
return 0; /* We should not get here in either case */
}