/* Om DM365, Imager and TVP5146 I2C address collide. So we need to
* keep imager on reset when working with tvp5146 and vice-versa
* This function use GIO40 to act as reset to imager
*/
void image_sensor_hw_reset(int state)
{
u32 val1;
if (cpu_is_davinci_dm365()) {
val1 = cpld_read(DM365_CPLD_REGISTER3);
val1 |= DM365_IMAGER_RST_MASK;
cpld_write(val1, DM365_CPLD_REGISTER3);
/* CPLD to Route GPIO to Imager Reset line */
val1 = cpld_read(DM365_CPLD_REGISTER16);
val1 &= ~0x40404040;
cpld_write(val1, DM365_CPLD_REGISTER16);
val1 = cpld_read(DM365_CPLD_REGISTER18);
val1 |= 0x20202020;
cpld_write(val1, DM365_CPLD_REGISTER18);
val1 = cpld_read(DM365_CPLD_REGISTER18);
val1 &= ~0x01010101;
cpld_write(val1, DM365_CPLD_REGISTER18);
#ifndef CONFIG_MTD_CFI /* When NOR flash is use and at 16-bit access mode. GPIO 40 is used as address bus */
/* Pin mux to use GPIO40 */
davinci_cfg_reg(DM365_GPIO40, PINMUX_RESV);
/* Configure GPIO40 to be output and hight */
if (state)
gpio_direction_output(40, 1);
else
gpio_direction_output(40, 0);
#endif
}
}
int get_module(void)
{
int res,res2;
res=cpld_read(CPLD0);
while((res2=(cpld_read(CPLD0)&0xF))!=res) /* wait for the value to become stable */
res=res2;
return (res&0xff);
}
static
int cpld_accesible(void)
{
cpld_init();
cpld_write(AVR_ADDR, 0x02);
return cpld_read(AVR_ADDR) == 0x02;
}
static int renesas_ulcb_sysreset_probe(struct udevice *dev)
{
struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev);
if (gpio_request_by_name(dev, "gpio-miso", 0, &priv->miso,
GPIOD_IS_IN))
return -EINVAL;
if (gpio_request_by_name(dev, "gpio-sck", 0, &priv->sck,
GPIOD_IS_OUT))
return -EINVAL;
if (gpio_request_by_name(dev, "gpio-sstbz", 0, &priv->sstbz,
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE))
return -EINVAL;
if (gpio_request_by_name(dev, "gpio-mosi", 0, &priv->mosi,
GPIOD_IS_OUT))
return -EINVAL;
/* PULL-UP on MISO line */
setbits_le32(PFC_PUEN5, PUEN_SSI_SDATA4);
/* Dummy read */
cpld_read(dev, CPLD_ADDR_VERSION);
return 0;
}
static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u32 addr, val;
if (argc < 3)
return CMD_RET_USAGE;
addr = simple_strtoul(argv[2], NULL, 16);
if (!(addr == CPLD_ADDR_VERSION || addr == CPLD_ADDR_MODE ||
addr == CPLD_ADDR_MUX || addr == CPLD_ADDR_HDMI ||
addr == CPLD_ADDR_DIPSW || addr == CPLD_ADDR_RESET)) {
printf("cpld invalid addr\n");
return CMD_RET_USAGE;
}
if (argc == 3 && strcmp(argv[1], "read") == 0) {
printf("0x%x\n", cpld_read(addr));
} else if (argc == 4 && strcmp(argv[1], "write") == 0) {
val = simple_strtoul(argv[3], NULL, 16);
if (addr == CPLD_ADDR_MUX) {
/* never mask SCIFA0 console */
val &= ~MUX_MSK_SCIFA0_USB;
val |= MUX_VAL_SCIFA0_USB;
}
cpld_write(addr, val);
}
return 0;
}
int mt9xxx_set_input_mux(unsigned char channel)
{
int err = 0;
u8 val[2];
u32 val1;
val[0] = 8;
if (cpu_is_davinci_dm644x())
return err;
val[1] = 0x80;
if (cpu_is_davinci_dm355()) {
//Logi err = davinci_i2c_write(2, val, MSP430_I2C_ADDR);
if (err)
return err;
} else if (cpu_is_davinci_dm365()) {
/* Drive TVP5146 Reset to low */
tvp514x_hw_reset(0);
/* drive the sensor reset line high */
image_sensor_hw_reset(1);
/* Set Mux for image sensor */
val1 = cpld_read(DM365_CPLD_REGISTER3);
val1 &= ~DM365_VIDEO_MUX_MASK;
val1 |= DM365_SENSOR_SEL;
cpld_write(val1, DM365_CPLD_REGISTER3);
}
/* For image sensor we need to program I2C switch
* PCA9543A
*/
//Logi val[0] = 0x01;
//Logi davinci_i2c_write(1, val, PCA9543A_I2C_ADDR);
return 0;
}
/* type = 0 for TVP5146 and 1 for Image sensor */
int tvp514x_set_input_mux(unsigned char channel)
{
int err = 0;
u8 val[2];
u32 val1;
val[0] = 8;
val[1] = 0x0;
if (cpu_is_davinci_dm644x())
return err;
/* Logi if (cpu_is_davinci_dm355())
err = davinci_i2c_write(2, val, MSP430_I2C_ADDR);
else */if (cpu_is_davinci_dm365()) {
/* drive the sensor reset line low */
image_sensor_hw_reset(0);
/* set tvp5146 reset line high */
tvp514x_hw_reset(1);
/* Set Mux for TVP5146 */
val1 = cpld_read(DM365_CPLD_REGISTER3);
val1 &= ~DM365_VIDEO_MUX_MASK;
val1 |= DM365_TVP5146_SEL;
cpld_write(val1, DM365_CPLD_REGISTER3);
}
return err;
}
int tvp7002_set_input_mux(unsigned char channel)
{
u32 val;
val = cpld_read(DM365_CPLD_REGISTER3);
val &= ~DM365_VIDEO_MUX_MASK;
val |= DM365_TVP7002_SEL;
cpld_write(val, DM365_CPLD_REGISTER3);
return 0;
}
static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct udevice *dev;
u32 addr, val;
int ret;
ret = uclass_get_device_by_driver(UCLASS_SYSRESET,
DM_GET_DRIVER(sysreset_renesas_ulcb),
&dev);
if (ret)
return ret;
if (argc == 2 && strcmp(argv[1], "info") == 0) {
printf("CPLD version:\t\t\t0x%08x\n",
cpld_read(dev, CPLD_ADDR_VERSION));
printf("H3 Mode setting (MD0..28):\t0x%08x\n",
cpld_read(dev, CPLD_ADDR_MODE));
printf("Multiplexer settings:\t\t0x%08x\n",
cpld_read(dev, CPLD_ADDR_MUX));
printf("DIPSW (SW6):\t\t\t0x%08x\n",
cpld_read(dev, CPLD_ADDR_DIPSW6));
return 0;
}
if (argc < 3)
return CMD_RET_USAGE;
addr = simple_strtoul(argv[2], NULL, 16);
if (!(addr == CPLD_ADDR_VERSION || addr == CPLD_ADDR_MODE ||
addr == CPLD_ADDR_MUX || addr == CPLD_ADDR_DIPSW6 ||
addr == CPLD_ADDR_RESET)) {
printf("Invalid CPLD register address\n");
return CMD_RET_USAGE;
}
if (argc == 3 && strcmp(argv[1], "read") == 0) {
printf("0x%x\n", cpld_read(dev, addr));
} else if (argc == 4 && strcmp(argv[1], "write") == 0) {
val = simple_strtoul(argv[3], NULL, 16);
cpld_write(dev, addr, val);
}
return 0;
}
/* For DM365, we need set tvp5146 reset line low for
* working with sensor. This API is used for this
* purpose state is 0 for reset low and 1 for high
*/
void tvp514x_hw_reset(int state)
{
u32 val1;
if (cpu_is_davinci_dm365()) {
val1 = cpld_read(DM365_CPLD_REGISTER19);
if (state)
val1 &= ~DM365_TVP5146_RST_MASK;
else
val1 |= 0x01010101;
cpld_write(val1, DM365_CPLD_REGISTER19);
}
}
void cobalt_cpld_status(struct cobalt *cobalt)
{
u32 rev = cpld_read(cobalt, 0x30);
switch (rev) {
case 3:
case 4:
case 5:
cpld_info_ver3(cobalt);
break;
default:
cobalt_info("CPLD revision %u is not supported!\n", rev);
break;
}
}
void cpld_LOS_update(struct channel *sc)
{
u_int8_t los;
cpld_write(sc, SBE_2T3E3_CPLD_REG_PICSR,
SBE_2T3E3_CPLD_VAL_DMO_SIGNAL_DETECTED |
SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_LOCK_DETECTED |
SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_SIGNAL_DETECTED);
los = cpld_read(sc, SBE_2T3E3_CPLD_REG_PICSR) &
SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_SIGNAL_DETECTED;
if (los != sc->s.LOS)
dev_info(&sc->pdev->dev, "SBE 2T3E3: LOS status: %s\n",
los ? "Loss of signal" : "Signal OK");
sc->s.LOS = los;
}
void cpld_init(void)
{
u32 val;
/* PULL-UP on MISO line */
val = readl(PUPR3);
val |= PUPR3_SD3_DAT1;
writel(val, PUPR3);
gpio_request(SCLK, "SCLK");
gpio_request(SSTBZ, "SSTBZ");
gpio_request(MOSI, "MOSI");
gpio_request(MISO, "MISO");
gpio_direction_output(SCLK, 0);
gpio_direction_output(SSTBZ, 1);
gpio_direction_output(MOSI, 0);
gpio_direction_input(MISO);
/* dummy read */
cpld_read(CPLD_ADDR_VERSION);
printf("CPLD version: 0x%08x\n",
cpld_read(CPLD_ADDR_VERSION));
printf("H2 Mode setting (MD0..28): 0x%08x\n",
cpld_read(CPLD_ADDR_MODE));
printf("Multiplexer settings: 0x%08x\n",
cpld_read(CPLD_ADDR_MUX));
printf("HDMI setting: 0x%08x\n",
cpld_read(CPLD_ADDR_HDMI));
printf("DIPSW (SW3): 0x%08x\n",
cpld_read(CPLD_ADDR_DIPSW));
#ifdef CONFIG_SH_SDHI
/* switch MUX to SD0 */
val = cpld_read(CPLD_ADDR_MUX);
val &= ~MUX_MSK_SD0;
val |= MUX_VAL_SD0;
cpld_write(CPLD_ADDR_MUX, val);
#endif
}
void t3e3_reg_read(struct channel *sc, u32 *reg, u32 *val)
{
u32 i;
*val = 0;
switch (reg[0]) {
case SBE_2T3E3_CHIP_21143:
if (!(reg[1] & 7))
*val = dc_read(sc->addr, reg[1] / 8);
break;
case SBE_2T3E3_CHIP_CPLD:
for (i = 0; i < SBE_2T3E3_CPLD_REG_MAX; i++)
if (cpld_reg_map[i][sc->h.slot] == reg[1]) {
*val = cpld_read(sc, i);
break;
}
break;
case SBE_2T3E3_CHIP_FRAMER:
for (i = 0; i < SBE_2T3E3_FRAMER_REG_MAX; i++)
if (t3e3_framer_reg_map[i] == reg[1]) {
*val = exar7250_read(sc, i);
break;
}
break;
case SBE_2T3E3_CHIP_LIU:
for (i = 0; i < SBE_2T3E3_LIU_REG_MAX; i++)
if (t3e3_liu_reg_map[i] == reg[1]) {
*val = exar7300_read(sc, i);
break;
}
break;
default:
break;
}
}
int arch_cpld_getVersion(void){
return (cpld_read(CPLD0) & 0x000F);
}
static void cpld_info_ver3(struct cobalt *cobalt)
{
u32 rd;
u32 tmp;
cobalt_info("CPLD System control register (read/write)\n");
cobalt_info("\t\tSystem control: 0x%04x (0x0f00)\n",
cpld_read(cobalt, 0));
cobalt_info("CPLD Clock control register (read/write)\n");
cobalt_info("\t\tClock control: 0x%04x (0x0000)\n",
cpld_read(cobalt, 0x04));
cobalt_info("CPLD HSMA Clk Osc register (read/write) - Must set wr trigger to load default values\n");
cobalt_info("\t\tRegister #7:\t0x%04x (0x0022)\n",
cpld_read(cobalt, 0x08));
cobalt_info("\t\tRegister #8:\t0x%04x (0x0047)\n",
cpld_read(cobalt, 0x0c));
cobalt_info("\t\tRegister #9:\t0x%04x (0x00fa)\n",
cpld_read(cobalt, 0x10));
cobalt_info("\t\tRegister #10:\t0x%04x (0x0061)\n",
cpld_read(cobalt, 0x14));
cobalt_info("\t\tRegister #11:\t0x%04x (0x001e)\n",
cpld_read(cobalt, 0x18));
cobalt_info("\t\tRegister #12:\t0x%04x (0x0045)\n",
cpld_read(cobalt, 0x1c));
cobalt_info("\t\tRegister #135:\t0x%04x\n",
cpld_read(cobalt, 0x20));
cobalt_info("\t\tRegister #137:\t0x%04x\n",
cpld_read(cobalt, 0x24));
cobalt_info("CPLD System status register (read only)\n");
cobalt_info("\t\tSystem status: 0x%04x\n",
cpld_read(cobalt, 0x28));
cobalt_info("CPLD MAXII info register (read only)\n");
cobalt_info("\t\tBoard serial number: 0x%04x\n",
cpld_read(cobalt, 0x2c));
cobalt_info("\t\tMAXII program revision: 0x%04x\n",
cpld_read(cobalt, 0x30));
cobalt_info("CPLD temp and voltage ADT7411 registers (read only)\n");
cobalt_info("\t\tBoard temperature: %u Celsius\n",
cpld_read(cobalt, 0x34) / 4);
cobalt_info("\t\tFPGA temperature: %u Celsius\n",
cpld_read(cobalt, 0x38) / 4);
rd = cpld_read(cobalt, 0x3c);
tmp = (rd * 33 * 1000) / (483 * 10);
cobalt_info("\t\tVDD 3V3: %u,%03uV\n", tmp / 1000, tmp % 1000);
rd = cpld_read(cobalt, 0x40);
tmp = (rd * 74 * 2197) / (27 * 1000);
cobalt_info("\t\tADC ch3 5V: %u,%03uV\n", tmp / 1000, tmp % 1000);
rd = cpld_read(cobalt, 0x44);
tmp = (rd * 74 * 2197) / (47 * 1000);
cobalt_info("\t\tADC ch4 3V: %u,%03uV\n", tmp / 1000, tmp % 1000);
rd = cpld_read(cobalt, 0x48);
tmp = (rd * 57 * 2197) / (47 * 1000);
cobalt_info("\t\tADC ch5 2V5: %u,%03uV\n", tmp / 1000, tmp % 1000);
rd = cpld_read(cobalt, 0x4c);
tmp = (rd * 2197) / 1000;
cobalt_info("\t\tADC ch6 1V8: %u,%03uV\n", tmp / 1000, tmp % 1000);
rd = cpld_read(cobalt, 0x50);
tmp = (rd * 2197) / 1000;
cobalt_info("\t\tADC ch7 1V5: %u,%03uV\n", tmp / 1000, tmp % 1000);
rd = cpld_read(cobalt, 0x54);
tmp = (rd * 2197) / 1000;
cobalt_info("\t\tADC ch8 0V9: %u,%03uV\n", tmp / 1000, tmp % 1000);
}
