static void setvector_callback(int param) { static int irq1,irq2; switch(param) { case VECTOR_INIT: irq1 = irq2 = 0xff; break; case RST10_ASSERT: irq1 = 0xd7; break; case RST10_CLEAR: irq1 = 0xff; break; case RST18_ASSERT: irq2 = 0xdf; break; case RST18_CLEAR: irq2 = 0xff; break; } cpu_irq_line_vector_w(sound_cpu,0,irq1 & irq2); if ((irq1 & irq2) == 0xff) /* no IRQs pending */ cpu_set_irq_line(sound_cpu,0,CLEAR_LINE); else /* IRQ pending */ cpu_set_irq_line(sound_cpu,0,ASSERT_LINE); }
static void setvector_callback(int param) { static int irqvector; switch(param) { case VECTOR_INIT: irqvector = 0xff; break; case YM2151_ASSERT: irqvector &= 0xef; break; case YM2151_CLEAR: irqvector |= 0x10; break; case Z80_ASSERT: irqvector &= 0xdf; break; case Z80_CLEAR: irqvector |= 0x20; break; } cpu_irq_line_vector_w(1,0,irqvector); if (irqvector == 0xff) /* no IRQs pending */ cpu_set_irq_line(1,0,CLEAR_LINE); else /* IRQ pending */ cpu_set_irq_line(1,0,ASSERT_LINE); }
static void timer_callback(int param) { /* Only cause IRQ if the mask is set to allow it */ if (m68681_imr&8) { cpu_irq_line_vector_w(1, 6, vector_reg); cpu_set_irq_line(1, 6, ASSERT_LINE); imr_status|=0x8; } }
static void setvector_callback(int param) { static int irqvector; switch(param) { case VECTOR_INIT: irqvector = 0; break; case YM2151_ASSERT: irqvector |= 0x2; break; case YM2151_CLEAR: irqvector &= ~0x2; break; case V30_ASSERT: irqvector |= 0x1; break; case V30_CLEAR: irqvector &= ~0x1; break; } if (irqvector & 0x2) /* YM2151 has precedence */ cpu_irq_line_vector_w(1,0,0x18); else if (irqvector & 0x1) /* V30 */ cpu_irq_line_vector_w(1,0,0x19); if (irqvector == 0) /* no IRQs pending */ cpu_set_irq_line(1,0,CLEAR_LINE); else /* IRQ pending */ cpu_set_irq_line(1,0,ASSERT_LINE); }