static int
ixp425_attach(device_t dev)
{
struct ixp425_softc *sc;
device_printf(dev, "%b\n", ixp4xx_read_feature_bits(), EXP_FCTRL_BITS);
sc = device_get_softc(dev);
sc->sc_iot = &ixp425_bs_tag;
KASSERT(ixp425_softc == NULL, ("%s called twice?", __func__));
ixp425_softc = sc;
intr_enabled = 0;
ixp425_set_intrmask();
ixp425_set_intrsteer();
if (cpu_is_ixp43x()) {
intr_enabled2 = 0;
ixp435_set_intrmask();
ixp435_set_intrsteer();
}
if (bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
BUS_SPACE_MAXADDR, NULL, NULL, 0xffffffff, 0xff, 0xffffffff, 0,
NULL, NULL, &sc->sc_dmat))
panic("%s: failed to create dma tag", __func__);
sc->sc_irq_rman.rm_type = RMAN_ARRAY;
sc->sc_irq_rman.rm_descr = "IXP4XX IRQs";
if (rman_init(&sc->sc_irq_rman) != 0 ||
rman_manage_region(&sc->sc_irq_rman, 0, cpu_is_ixp43x() ? 63 : 31) != 0)
panic("%s: failed to set up IRQ rman", __func__);
sc->sc_mem_rman.rm_type = RMAN_ARRAY;
sc->sc_mem_rman.rm_descr = "IXP4XX Memory";
if (rman_init(&sc->sc_mem_rman) != 0 ||
rman_manage_region(&sc->sc_mem_rman, 0, ~0) != 0)
panic("%s: failed to set up memory rman", __func__);
BUS_ADD_CHILD(dev, 0, "pcib", 0);
BUS_ADD_CHILD(dev, 0, "ixpclk", 0);
BUS_ADD_CHILD(dev, 0, "ixpiic", 0);
/* XXX move to hints? */
BUS_ADD_CHILD(dev, 0, "ixpwdog", 0);
/* attach wired devices via hints */
bus_enumerate_hinted_children(dev);
if (bus_space_map(sc->sc_iot, IXP425_GPIO_HWBASE, IXP425_GPIO_SIZE,
0, &sc->sc_gpio_ioh))
panic("%s: unable to map GPIO registers", __func__);
if (bus_space_map(sc->sc_iot, IXP425_EXP_HWBASE, IXP425_EXP_SIZE,
0, &sc->sc_exp_ioh))
panic("%s: unable to map Expansion Bus registers", __func__);
bus_generic_probe(dev);
bus_generic_attach(dev);
return (0);
}
void __init ixp4xx_init_irq(void)
{
int i = 0;
/* Route all sources to IRQ instead of FIQ */
*IXP4XX_ICLR = 0x0;
/* Disable all interrupt */
*IXP4XX_ICMR = 0x0;
if (cpu_is_ixp46x() || cpu_is_ixp43x()) {
/* Route upper 32 sources to IRQ instead of FIQ */
*IXP4XX_ICLR2 = 0x00;
/* Disable upper 32 interrupts */
*IXP4XX_ICMR2 = 0x00;
}
/* Default to all level triggered */
for(i = 0; i < NR_IRQS; i++) {
set_irq_chip(i, &ixp4xx_irq_chip);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
}
static void ixp4xx_irq_mask(unsigned int irq)
{
if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32)
*IXP4XX_ICMR2 &= ~(1 << (irq - 32));
else
*IXP4XX_ICMR &= ~(1 << irq);
}
static void ixp4xx_irq_mask(struct irq_data *d)
{
if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
*IXP4XX_ICMR2 &= ~(1 << (d->irq - 32));
else
*IXP4XX_ICMR &= ~(1 << d->irq);
}
void __init ixp4xx_init_irq(void)
{
int i = 0;
/*
* ixp4xx does not implement the XScale PWRMODE register
* so it must not call cpu_do_idle().
*/
disable_hlt();
/* Route all sources to IRQ instead of FIQ */
*IXP4XX_ICLR = 0x0;
/* Disable all interrupt */
*IXP4XX_ICMR = 0x0;
if (cpu_is_ixp46x() || cpu_is_ixp43x()) {
/* Route upper 32 sources to IRQ instead of FIQ */
*IXP4XX_ICLR2 = 0x00;
/* Disable upper 32 interrupts */
*IXP4XX_ICMR2 = 0x00;
}
/* Default to all level triggered */
for(i = 0; i < NR_IRQS; i++) {
irq_set_chip_and_handler(i, &ixp4xx_irq_chip,
handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
}
static int ixp4xx_mdio_register(void)
{
int err;
if (!(mdio_bus = mdiobus_alloc()))
return -ENOMEM;
if (cpu_is_ixp43x()) {
/* IXP43x lacks NPE-B and uses NPE-C for MII PHY access */
if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEC_ETH))
return -ENOSYS;
mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
} else {
/* All MII PHY accesses use NPE-B Ethernet registers */
if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0))
return -ENOSYS;
mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
}
__raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
spin_lock_init(&mdio_lock);
mdio_bus->name = "IXP4xx MII Bus";
mdio_bus->read = &ixp4xx_mdio_read;
mdio_bus->write = &ixp4xx_mdio_write;
strcpy(mdio_bus->id, "0");
if ((err = mdiobus_register(mdio_bus)))
mdiobus_free(mdio_bus);
return err;
}
static void __init ixdp425_init(void)
{
ixp4xx_sys_init();
ixdp425_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
ixdp425_flash_resource.end =
IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
#if defined(CONFIG_MTD_NAND_PLATFORM) || \
defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
ixdp425_flash_nand_resource.start = IXP4XX_EXP_BUS_BASE(3),
ixdp425_flash_nand_resource.end = IXP4XX_EXP_BUS_BASE(3) + 0x10 - 1;
gpio_line_config(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_OUT);
/* Configure expansion bus for NAND Flash */
*IXP4XX_EXP_CS3 = IXP4XX_EXP_BUS_CS_EN |
IXP4XX_EXP_BUS_STROBE_T(1) | /* extend by 1 clock */
IXP4XX_EXP_BUS_CYCLES(0) | /* Intel cycles */
IXP4XX_EXP_BUS_SIZE(0) | /* 512bytes addr space*/
IXP4XX_EXP_BUS_WR_EN |
IXP4XX_EXP_BUS_BYTE_EN; /* 8 bit data bus */
#endif
if (cpu_is_ixp43x()) {
ixdp425_uart.num_resources = 1;
ixdp425_uart_data[1].flags = 0;
}
platform_add_devices(ixdp425_devices, ARRAY_SIZE(ixdp425_devices));
}
void __init ixp4xx_init_irq(void)
{
int i = 0;
*IXP4XX_ICLR = 0x0;
*IXP4XX_ICMR = 0x0;
if (cpu_is_ixp46x() || cpu_is_ixp43x()) {
*IXP4XX_ICLR2 = 0x00;
*IXP4XX_ICMR2 = 0x00;
}
for(i = 0; i < NR_IRQS; i++) {
set_irq_chip(i, &ixp4xx_irq_chip);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
}
void __init ixp4xx_init_irq(void)
{
int i = 0;
/*
*/
disable_hlt();
/* */
*IXP4XX_ICLR = 0x0;
/* */
*IXP4XX_ICMR = 0x0;
if (cpu_is_ixp46x() || cpu_is_ixp43x()) {
/* */
*IXP4XX_ICLR2 = 0x00;
/* */
*IXP4XX_ICMR2 = 0x00;
}
/* */
for(i = 0; i < NR_IRQS; i++) {
irq_set_chip_and_handler(i, &ixp4xx_irq_chip,
handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
}
/*
* Level triggered interrupts on GPIO lines can only be cleared when the
* interrupt condition disappears.
*/
static void ixp4xx_irq_unmask(unsigned int irq)
{
if (!(ixp4xx_irq_edge & (1 << irq)))
ixp4xx_irq_ack(irq);
if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32)
*IXP4XX_ICMR2 |= (1 << (irq - 32));
else
*IXP4XX_ICMR |= (1 << irq);
}
/*
* Level triggered interrupts on GPIO lines can only be cleared when the
* interrupt condition disappears.
*/
static void ixp4xx_irq_unmask(struct irq_data *d)
{
if (!(ixp4xx_irq_edge & (1 << d->irq)))
ixp4xx_irq_ack(d);
if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
*IXP4XX_ICMR2 |= (1 << (d->irq - 32));
else
*IXP4XX_ICMR |= (1 << d->irq);
}
static __inline void
update_masks(uint32_t mask, uint32_t mask2)
{
intr_enabled = mask;
ixp425_set_intrmask();
if (cpu_is_ixp43x()) {
intr_enabled2 = mask2;
ixp435_set_intrmask();
}
}
int
arm_get_next_irq(void)
{
uint32_t irq;
if ((irq = ixp425_irq_read()))
return (ffs(irq) - 1);
if (cpu_is_ixp43x() && (irq = ixp435_irq_read()))
return (32 + ffs(irq) - 1);
return (-1);
}
void
cambria_exp_bus_init(struct ixp425_softc *sc)
{
static struct expbus_softc c3; /* NB: no need to malloc */
uint32_t cs3;
KASSERT(cpu_is_ixp43x(), ("wrong cpu type"));
c3.sc = sc;
c3.csoff = EXP_TIMING_CS3_OFFSET;
EXP_LOCK_INIT(&c3);
cambria_exp_bs_tag.bs_cookie = &c3;
cs3 = EXP_BUS_READ_4(sc, EXP_TIMING_CS3_OFFSET);
/* XXX force slowest possible timings and byte mode */
EXP_BUS_WRITE_4(sc, EXP_TIMING_CS3_OFFSET,
cs3 | (EXP_T1|EXP_T2|EXP_T3|EXP_T4|EXP_T5) |
EXP_BYTE_EN | EXP_WR_EN | EXP_BYTE_RD16 | EXP_CS_EN);
/* XXX force GPIO 3+4 for GPS+RS485 uarts */
ixp425_set_gpio(sc, 3, GPIO_TYPE_EDG_RISING);
ixp425_set_gpio(sc, 4, GPIO_TYPE_EDG_RISING);
}
void *
initarm(void *arg, void *arg2)
{
#define next_chunk2(a,b) (((a) + (b)) &~ ((b)-1))
#define next_page(a) next_chunk2(a,PAGE_SIZE)
struct pv_addr kernel_l1pt;
struct pv_addr dpcpu;
int loop, i;
u_int l1pagetable;
vm_offset_t freemempos;
vm_offset_t freemem_pt;
vm_offset_t afterkern;
vm_offset_t freemem_after;
vm_offset_t lastaddr;
uint32_t memsize;
set_cpufuncs(); /* NB: sets cputype */
lastaddr = fake_preload_metadata();
pcpu_init(pcpup, 0, sizeof(struct pcpu));
PCPU_SET(curthread, &thread0);
/* Do basic tuning, hz etc */
init_param1();
/*
* We allocate memory downwards from where we were loaded
* by RedBoot; first the L1 page table, then NUM_KERNEL_PTS
* entries in the L2 page table. Past that we re-align the
* allocation boundary so later data structures (stacks, etc)
* can be mapped with different attributes (write-back vs
* write-through). Note this leaves a gap for expansion
* (or might be repurposed).
*/
freemempos = KERNPHYSADDR;
/* macros to simplify initial memory allocation */
#define alloc_pages(var, np) do { \
freemempos -= (np * PAGE_SIZE); \
(var) = freemempos; \
/* NB: this works because locore maps PA=VA */ \
memset((char *)(var), 0, ((np) * PAGE_SIZE)); \
} while (0)
#define valloc_pages(var, np) do { \
alloc_pages((var).pv_pa, (np)); \
(var).pv_va = (var).pv_pa + (KERNVIRTADDR - KERNPHYSADDR); \
} while (0)
/* force L1 page table alignment */
while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
freemempos -= PAGE_SIZE;
/* allocate contiguous L1 page table */
valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
/* now allocate L2 page tables; they are linked to L1 below */
for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
valloc_pages(kernel_pt_table[loop],
L2_TABLE_SIZE / PAGE_SIZE);
} else {
kernel_pt_table[loop].pv_pa = freemempos +
(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
L2_TABLE_SIZE_REAL;
kernel_pt_table[loop].pv_va =
kernel_pt_table[loop].pv_pa +
(KERNVIRTADDR - KERNPHYSADDR);
}
}
freemem_pt = freemempos; /* base of allocated pt's */
/*
* Re-align allocation boundary so we can map the area
* write-back instead of write-through for the stacks and
* related structures allocated below.
*/
freemempos = PHYSADDR + 0x100000;
/*
* Allocate a page for the system page mapped to V0x00000000
* This page will just contain the system vectors and can be
* shared by all processes.
*/
valloc_pages(systempage, 1);
/* Allocate dynamic per-cpu area. */
valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
dpcpu_init((void *)dpcpu.pv_va, 0);
/* Allocate stacks for all modes */
valloc_pages(irqstack, IRQ_STACK_SIZE);
valloc_pages(abtstack, ABT_STACK_SIZE);
valloc_pages(undstack, UND_STACK_SIZE);
valloc_pages(kernelstack, KSTACK_PAGES);
alloc_pages(minidataclean.pv_pa, 1);
valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
#ifdef ARM_USE_SMALL_ALLOC
freemempos -= PAGE_SIZE;
freemem_pt = trunc_page(freemem_pt);
freemem_after = freemempos - ((freemem_pt - (PHYSADDR + 0x100000)) /
PAGE_SIZE) * sizeof(struct arm_small_page);
arm_add_smallalloc_pages(
(void *)(freemem_after + (KERNVIRTADDR - KERNPHYSADDR)),
(void *)0xc0100000,
freemem_pt - (PHYSADDR + 0x100000), 1);
freemem_after -= ((freemem_after - (PHYSADDR + 0x1000)) / PAGE_SIZE) *
sizeof(struct arm_small_page);
arm_add_smallalloc_pages(
(void *)(freemem_after + (KERNVIRTADDR - KERNPHYSADDR)),
(void *)0xc0001000,
trunc_page(freemem_after) - (PHYSADDR + 0x1000), 0);
freemempos = trunc_page(freemem_after);
freemempos -= PAGE_SIZE;
#endif
/*
* Now construct the L1 page table. First map the L2
* page tables into the L1 so we can replace L1 mappings
* later on if necessary
*/
l1pagetable = kernel_l1pt.pv_va;
/* Map the L2 pages tables in the L1 page table */
pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00100000 - 1),
&kernel_pt_table[KERNEL_PT_SYS]);
pmap_link_l2pt(l1pagetable, IXP425_IO_VBASE,
&kernel_pt_table[KERNEL_PT_IO]);
pmap_link_l2pt(l1pagetable, IXP425_MCU_VBASE,
&kernel_pt_table[KERNEL_PT_IO + 1]);
pmap_link_l2pt(l1pagetable, IXP425_PCI_MEM_VBASE,
&kernel_pt_table[KERNEL_PT_IO + 2]);
pmap_link_l2pt(l1pagetable, KERNBASE,
&kernel_pt_table[KERNEL_PT_BEFOREKERN]);
pmap_map_chunk(l1pagetable, KERNBASE, PHYSADDR, 0x100000,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, PHYSADDR + 0x100000,
0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
pmap_map_chunk(l1pagetable, KERNEL_TEXT_BASE, KERNEL_TEXT_PHYS,
next_chunk2(((uint32_t)lastaddr) - KERNEL_TEXT_BASE, L1_S_SIZE),
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
freemem_after = next_page((int)lastaddr);
afterkern = round_page(next_chunk2((vm_offset_t)lastaddr, L1_S_SIZE));
for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000,
&kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
}
pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
#ifdef ARM_USE_SMALL_ALLOC
if ((freemem_after + 2 * PAGE_SIZE) <= afterkern) {
arm_add_smallalloc_pages((void *)(freemem_after),
(void*)(freemem_after + PAGE_SIZE),
afterkern - (freemem_after + PAGE_SIZE), 0);
}
#endif
/* Map the Mini-Data cache clean area. */
xscale_setup_minidata(l1pagetable, afterkern,
minidataclean.pv_pa);
/* Map the vector page. */
pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
if (cpu_is_ixp43x())
pmap_devmap_bootstrap(l1pagetable, ixp435_devmap);
else
pmap_devmap_bootstrap(l1pagetable, ixp425_devmap);
/*
* Give the XScale global cache clean code an appropriately
* sized chunk of unmapped VA space starting at 0xff000000
* (our device mappings end before this address).
*/
xscale_cache_clean_addr = 0xff000000U;
cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
setttb(kernel_l1pt.pv_pa);
cpu_tlb_flushID();
cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
/*
* Pages were allocated during the secondary bootstrap for the
* stacks for different CPU modes.
* We must now set the r13 registers in the different CPU modes to
* point to these stacks.
* Since the ARM stacks use STMFD etc. we must set r13 to the top end
* of the stack memory.
*/
set_stackptr(PSR_IRQ32_MODE, irqstack.pv_va + IRQ_STACK_SIZE*PAGE_SIZE);
set_stackptr(PSR_ABT32_MODE, abtstack.pv_va + ABT_STACK_SIZE*PAGE_SIZE);
set_stackptr(PSR_UND32_MODE, undstack.pv_va + UND_STACK_SIZE*PAGE_SIZE);
/*
* We must now clean the cache again....
* Cleaning may be done by reading new data to displace any
* dirty data in the cache. This will have happened in setttb()
* but since we are boot strapping the addresses used for the read
* may have just been remapped and thus the cache could be out
* of sync. A re-clean after the switch will cure this.
* After booting there are no gross relocations of the kernel thus
* this problem will not occur after initarm().
*/
cpu_idcache_wbinv_all();
/* ready to setup the console (XXX move earlier if possible) */
cninit();
/*
* Fetch the RAM size from the MCU registers. The
* expansion bus was mapped above so we can now read 'em.
*/
if (cpu_is_ixp43x())
memsize = ixp435_ddram_size();
else
memsize = ixp425_sdram_size();
physmem = memsize / PAGE_SIZE;
/* Set stack for exception handlers */
data_abort_handler_address = (u_int)data_abort_handler;
prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
undefined_handler_address = (u_int)undefinedinstruction_bounce;
undefined_init();
proc_linkup0(&proc0, &thread0);
thread0.td_kstack = kernelstack.pv_va;
thread0.td_pcb = (struct pcb *)
(thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1;
thread0.td_pcb->pcb_flags = 0;
thread0.td_frame = &proc0_tf;
pcpup->pc_curpcb = thread0.td_pcb;
arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
pmap_curmaxkvaddr = afterkern + PAGE_SIZE;
dump_avail[0] = PHYSADDR;
dump_avail[1] = PHYSADDR + memsize;
dump_avail[2] = 0;
dump_avail[3] = 0;
pmap_bootstrap(pmap_curmaxkvaddr, 0xd0000000, &kernel_l1pt);
msgbufp = (void*)msgbufpv.pv_va;
msgbufinit(msgbufp, msgbufsize);
mutex_init();
i = 0;
#ifdef ARM_USE_SMALL_ALLOC
phys_avail[i++] = PHYSADDR;
phys_avail[i++] = PHYSADDR + PAGE_SIZE; /*
*XXX: Gross hack to get our
* pages in the vm_page_array.
*/
#endif
phys_avail[i++] = round_page(virtual_avail - KERNBASE + PHYSADDR);
phys_avail[i++] = trunc_page(PHYSADDR + memsize - 1);
phys_avail[i++] = 0;
phys_avail[i] = 0;
init_param2(physmem);
kdb_init();
/* use static kernel environment if so configured */
if (envmode == 1)
kern_envp = static_env;
return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
sizeof(struct pcb)));
#undef next_page
#undef next_chunk2
}
void *
initarm(struct arm_boot_params *abp)
{
#define next_chunk2(a,b) (((a) + (b)) &~ ((b)-1))
#define next_page(a) next_chunk2(a,PAGE_SIZE)
struct pv_addr kernel_l1pt;
struct pv_addr dpcpu;
int loop, i;
u_int l1pagetable;
vm_offset_t freemempos;
vm_offset_t freemem_pt;
vm_offset_t afterkern;
vm_offset_t freemem_after;
vm_offset_t lastaddr;
uint32_t memsize;
/* kernel text starts where we were loaded at boot */
#define KERNEL_TEXT_OFF (abp->abp_physaddr - PHYSADDR)
#define KERNEL_TEXT_BASE (KERNBASE + KERNEL_TEXT_OFF)
#define KERNEL_TEXT_PHYS (PHYSADDR + KERNEL_TEXT_OFF)
lastaddr = parse_boot_param(abp);
arm_physmem_kernaddr = abp->abp_physaddr;
set_cpufuncs(); /* NB: sets cputype */
pcpu_init(pcpup, 0, sizeof(struct pcpu));
PCPU_SET(curthread, &thread0);
if (envmode == 1)
kern_envp = static_env;
/* Do basic tuning, hz etc */
init_param1();
/*
* We allocate memory downwards from where we were loaded
* by RedBoot; first the L1 page table, then NUM_KERNEL_PTS
* entries in the L2 page table. Past that we re-align the
* allocation boundary so later data structures (stacks, etc)
* can be mapped with different attributes (write-back vs
* write-through). Note this leaves a gap for expansion
* (or might be repurposed).
*/
freemempos = abp->abp_physaddr;
/* macros to simplify initial memory allocation */
#define alloc_pages(var, np) do { \
freemempos -= (np * PAGE_SIZE); \
(var) = freemempos; \
/* NB: this works because locore maps PA=VA */ \
memset((char *)(var), 0, ((np) * PAGE_SIZE)); \
} while (0)
#define valloc_pages(var, np) do { \
alloc_pages((var).pv_pa, (np)); \
(var).pv_va = (var).pv_pa + (KERNVIRTADDR - abp->abp_physaddr); \
} while (0)
/* force L1 page table alignment */
while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
freemempos -= PAGE_SIZE;
/* allocate contiguous L1 page table */
valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
/* now allocate L2 page tables; they are linked to L1 below */
for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
valloc_pages(kernel_pt_table[loop],
L2_TABLE_SIZE / PAGE_SIZE);
} else {
kernel_pt_table[loop].pv_pa = freemempos +
(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
L2_TABLE_SIZE_REAL;
kernel_pt_table[loop].pv_va =
kernel_pt_table[loop].pv_pa +
(KERNVIRTADDR - abp->abp_physaddr);
}
}
freemem_pt = freemempos; /* base of allocated pt's */
/*
* Re-align allocation boundary so we can map the area
* write-back instead of write-through for the stacks and
* related structures allocated below.
*/
freemempos = PHYSADDR + 0x100000;
/*
* Allocate a page for the system page mapped to V0x00000000
* This page will just contain the system vectors and can be
* shared by all processes.
*/
valloc_pages(systempage, 1);
/* Allocate dynamic per-cpu area. */
valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
dpcpu_init((void *)dpcpu.pv_va, 0);
/* Allocate stacks for all modes */
valloc_pages(irqstack, IRQ_STACK_SIZE);
valloc_pages(abtstack, ABT_STACK_SIZE);
valloc_pages(undstack, UND_STACK_SIZE);
valloc_pages(kernelstack, KSTACK_PAGES);
alloc_pages(minidataclean.pv_pa, 1);
valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
/*
* Now construct the L1 page table. First map the L2
* page tables into the L1 so we can replace L1 mappings
* later on if necessary
*/
l1pagetable = kernel_l1pt.pv_va;
/* Map the L2 pages tables in the L1 page table */
pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00100000 - 1),
&kernel_pt_table[KERNEL_PT_SYS]);
pmap_link_l2pt(l1pagetable, IXP425_IO_VBASE,
&kernel_pt_table[KERNEL_PT_IO]);
pmap_link_l2pt(l1pagetable, IXP425_MCU_VBASE,
&kernel_pt_table[KERNEL_PT_IO + 1]);
pmap_link_l2pt(l1pagetable, IXP425_PCI_MEM_VBASE,
&kernel_pt_table[KERNEL_PT_IO + 2]);
pmap_link_l2pt(l1pagetable, KERNBASE,
&kernel_pt_table[KERNEL_PT_BEFOREKERN]);
pmap_map_chunk(l1pagetable, KERNBASE, PHYSADDR, 0x100000,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, PHYSADDR + 0x100000,
0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
pmap_map_chunk(l1pagetable, KERNEL_TEXT_BASE, KERNEL_TEXT_PHYS,
next_chunk2(((uint32_t)lastaddr) - KERNEL_TEXT_BASE, L1_S_SIZE),
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
freemem_after = next_page((int)lastaddr);
afterkern = round_page(next_chunk2((vm_offset_t)lastaddr, L1_S_SIZE));
for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000,
&kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
}
pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
/* Map the Mini-Data cache clean area. */
xscale_setup_minidata(l1pagetable, afterkern,
minidataclean.pv_pa);
/* Map the vector page. */
pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
if (cpu_is_ixp43x())
arm_devmap_bootstrap(l1pagetable, ixp435_devmap);
else
arm_devmap_bootstrap(l1pagetable, ixp425_devmap);
/*
* Give the XScale global cache clean code an appropriately
* sized chunk of unmapped VA space starting at 0xff000000
* (our device mappings end before this address).
*/
xscale_cache_clean_addr = 0xff000000U;
cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
setttb(kernel_l1pt.pv_pa);
cpu_tlb_flushID();
cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
/*
* Pages were allocated during the secondary bootstrap for the
* stacks for different CPU modes.
* We must now set the r13 registers in the different CPU modes to
* point to these stacks.
* Since the ARM stacks use STMFD etc. we must set r13 to the top end
* of the stack memory.
*/
set_stackptrs(0);
/*
* We must now clean the cache again....
* Cleaning may be done by reading new data to displace any
* dirty data in the cache. This will have happened in setttb()
* but since we are boot strapping the addresses used for the read
* may have just been remapped and thus the cache could be out
* of sync. A re-clean after the switch will cure this.
* After booting there are no gross relocations of the kernel thus
* this problem will not occur after initarm().
*/
cpu_idcache_wbinv_all();
cpu_setup();
/* ready to setup the console (XXX move earlier if possible) */
cninit();
/*
* Fetch the RAM size from the MCU registers. The
* expansion bus was mapped above so we can now read 'em.
*/
if (cpu_is_ixp43x())
memsize = ixp435_ddram_size();
else
memsize = ixp425_sdram_size();
undefined_init();
init_proc0(kernelstack.pv_va);
arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
pmap_curmaxkvaddr = afterkern + PAGE_SIZE;
vm_max_kernel_address = 0xe0000000;
pmap_bootstrap(pmap_curmaxkvaddr, &kernel_l1pt);
msgbufp = (void*)msgbufpv.pv_va;
msgbufinit(msgbufp, msgbufsize);
mutex_init();
/*
* Add the physical ram we have available.
*
* Exclude the kernel, and all the things we allocated which immediately
* follow the kernel, from the VM allocation pool but not from crash
* dumps. virtual_avail is a global variable which tracks the kva we've
* "allocated" while setting up pmaps.
*
* Prepare the list of physical memory available to the vm subsystem.
*/
arm_physmem_hardware_region(PHYSADDR, memsize);
arm_physmem_exclude_region(freemem_pt, KERNPHYSADDR -
freemem_pt, EXFLAG_NOALLOC);
arm_physmem_exclude_region(freemempos, KERNPHYSADDR - 0x100000 -
freemempos, EXFLAG_NOALLOC);
arm_physmem_exclude_region(abp->abp_physaddr,
virtual_avail - KERNVIRTADDR, EXFLAG_NOALLOC);
arm_physmem_init_kernel_globals();
init_param2(physmem);
kdb_init();
/* use static kernel environment if so configured */
if (envmode == 1)
kern_envp = static_env;
return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
sizeof(struct pcb)));
#undef next_page
#undef next_chunk2
}
