bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97)
{
unsigned long gsr;
#ifdef CONFIG_PXA25x
if (cpu_is_pxa25x())
pxa_ac97_warm_pxa25x();
else
#endif
#ifdef CONFIG_PXA27x
if (cpu_is_pxa27x())
pxa_ac97_warm_pxa27x();
else
#endif
#ifdef CONFIG_PXA3xx
if (cpu_is_pxa3xx())
pxa_ac97_warm_pxa3xx();
else
#endif
BUG();
gsr = GSR | gsr_bits;
if (!(gsr & (GSR_PCR | GSR_SCR))) {
printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
__func__, gsr);
return false;
}
return true;
}
bool pxa2xx_ac97_try_cold_reset(struct snd_ac97 *ac97)
{
#ifdef CONFIG_PXA25x
if (cpu_is_pxa25x())
pxa_ac97_cold_pxa25x();
else
#endif
#ifdef CONFIG_PXA27x
if (cpu_is_pxa27x())
pxa_ac97_cold_pxa27x();
else
#endif
#ifdef CONFIG_PXA3xx
if (cpu_is_pxa3xx())
pxa_ac97_cold_pxa3xx();
else
#endif
BUG();
if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) {
printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
__func__, gsr_bits);
return false;
}
return true;
}
void __init pxa_init_irq(int irq_nr, set_wake_t fn)
{
int irq, i;
BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
pxa_internal_irq_nr = irq_nr;
for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq += 32) {
_ICMR(irq) = 0; /* disable all IRQs */
_ICLR(irq) = 0; /* all IRQs are IRQ, not FIQ */
}
/* initialize interrupt priority */
if (cpu_is_pxa27x() || cpu_is_pxa3xx()) {
for (i = 0; i < irq_nr; i++)
IPR(i) = i | (1 << 31);
}
/* only unmasked interrupts kick us out of idle */
ICCR = 1;
for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq++) {
set_irq_chip(irq, &pxa_internal_irq_chip);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
pxa_internal_irq_chip.set_wake = fn;
pxa_init_low_gpio_irq(fn);
}
static int __init mfp_init_devicefs(void)
{
if (cpu_is_pxa3xx())
return sysdev_class_register(&pxa3xx_mfp_sysclass);
return 0;
}
static void pxa2xx_ac97_warm_reset(struct snd_ac97 *ac97)
{
int timeout = 100;
gsr_bits = 0;
if (cpu_is_pxa27x()) {
/* warm reset broken on Bulverde, so manually keep
* AC97 reset high */
pxa_gpio_mode(113 | GPIO_OUT | GPIO_DFLT_HIGH);
udelay(10);
GCR |= GCR_WARM_RST;
pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
udelay(500);
} else if (cpu_is_pxa3xx()) {
/* Can't use interrupts */
GCR |= GCR_WARM_RST;
while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
mdelay(1);
} else {
GCR |= GCR_WARM_RST | GCR_PRIRDY_IEN | GCR_SECRDY_IEN;
wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
}
if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)))
printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
__FUNCTION__, gsr_bits);
GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
}
void clear_reset_status(unsigned int mask)
{
if (cpu_is_pxa2xx())
pxa2xx_clear_reset_status(mask);
if (cpu_is_pxa3xx())
pxa3xx_clear_reset_status(mask);
}
static void pxa2xx_ac97_cold_reset(struct snd_ac97 *ac97)
{
int timeout = 1000;
if (cpu_is_pxa3xx()) {
/* Hold CLKBPB for 100us */
GCR = 0;
GCR = GCR_CLKBPB;
udelay(100);
GCR = 0;
}
GCR &= GCR_COLD_RST; /* clear everything but nCRST */
GCR &= ~GCR_COLD_RST; /* then assert nCRST */
gsr_bits = 0;
if (cpu_is_pxa27x()) {
/* PXA27x Developers Manual section 13.5.2.2.1 */
clk_enable(ac97conf_clk);
udelay(5);
clk_disable(ac97conf_clk);
GCR = GCR_COLD_RST;
udelay(50);
} else if (cpu_is_pxa3xx()) {
/* Can't use interrupts on PXA3xx */
GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
GCR = GCR_WARM_RST | GCR_COLD_RST;
while (!(GSR & (GSR_PCR | GSR_SCR)) && timeout--)
mdelay(10);
} else {
GCR = GCR_COLD_RST;
GCR |= GCR_CDONE_IE|GCR_SDONE_IE;
wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
}
if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)))
printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
__FUNCTION__, gsr_bits);
GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
}
static int __init smemc_init(void)
{
if (cpu_is_pxa3xx())
__raw_writel(0x2, CSMSADRCFG);
register_syscore_ops(&smemc_syscore_ops);
return 0;
}
void __init pxa_map_io(void)
{
iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
get_clk_frequency_khz(1);
if (!cpu_is_pxa2xx() || !cpu_is_pxa3xx() || !cpu_is_pxa93x())
pxa_chip_id = __raw_readl(0xfb00ff80);
}
/*
* For non device-tree builds, keep legacy timer init
*/
void __init pxa_timer_init(void)
{
if (cpu_is_pxa25x())
pxa25x_clocks_init();
if (cpu_is_pxa27x())
pxa27x_clocks_init();
if (cpu_is_pxa3xx())
pxa3xx_clocks_init();
pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x40a00000));
}
void clear_reset_status(unsigned int mask)
{
if (cpu_is_pxa2xx())
pxa2xx_clear_reset_status(mask);
else if (cpu_is_pxa3xx())
pxa3xx_clear_reset_status(mask);
else if (cpu_is_pxa93x())
pxa93x_clear_reset_status(mask);
else
pxa95x_clear_reset_status(mask);
}
static int __init smemc_init(void)
{
int ret = 0;
if (cpu_is_pxa3xx()) {
smemc_mmio_base = ioremap(SMEMC_PHYS_BASE, SMEMC_PHYS_SIZE);
if (smemc_mmio_base == NULL)
return -ENODEV;
ret = sysdev_class_register(&smemc_sysclass);
if (ret)
return ret;
ret = sysdev_register(&smemc_sysdev);
}
return ret;
}
static void do_hw_reset(void)
{
if (cpu_is_pxa3xx()) {
if (cpu_is_pxa310()) {
/* Initialize the watchdog and let it fire */
OWER = OWER_WME;
OSSR = OSSR_M3;
OSMR3 = OSCR + 368640; /* ... in 100 ms */
} else {
/* GPIO reset */
PSPR = 0x5c014000;
PMCR = (PMCR & (PMCR_BIE | PMCR_TIE | PMCR_VIE))
| PMCR_SWGR;
}
} else {
/* Initialize the watchdog and let it fire */
OWER = OWER_WME;
OSSR = OSSR_M3;
OSMR3 = OSCR + 368640; /* ... in 100 ms */
}
}
static void pxa27x_stop_hc(struct pxa27x_ohci *ohci, struct device *dev)
{
struct pxaohci_platform_data *inf;
uint32_t uhccoms;
inf = dev->platform_data;
if (cpu_is_pxa3xx())
pxa3xx_u2d_stop_hc(&ohci_to_hcd(&ohci->ohci)->self);
if (inf->exit)
inf->exit(dev);
pxa27x_reset_hc(ohci);
/* Host Controller Reset */
uhccoms = __raw_readl(ohci->mmio_base + UHCCOMS) | 0x01;
__raw_writel(uhccoms, ohci->mmio_base + UHCCOMS);
udelay(10);
clk_disable(ohci->clk);
}
static int pxa27x_start_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev)
{
int retval = 0;
struct pxaohci_platform_data *inf;
uint32_t uhchr;
struct usb_hcd *hcd = dev_get_drvdata(dev);
inf = dev_get_platdata(dev);
clk_prepare_enable(pxa_ohci->clk);
pxa27x_reset_hc(pxa_ohci);
uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) | UHCHR_FSBIR;
__raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
while (__raw_readl(pxa_ohci->mmio_base + UHCHR) & UHCHR_FSBIR)
cpu_relax();
pxa27x_setup_hc(pxa_ohci, inf);
if (inf->init)
retval = inf->init(dev);
if (retval < 0)
return retval;
if (cpu_is_pxa3xx())
pxa3xx_u2d_start_hc(&hcd->self);
uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) & ~UHCHR_SSE;
__raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
__raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, pxa_ohci->mmio_base + UHCHIE);
/* Clear any OTG Pin Hold */
pxa27x_clear_otgph();
return 0;
}
static void pxa27x_stop_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev)
{
struct pxaohci_platform_data *inf;
struct usb_hcd *hcd = dev_get_drvdata(dev);
uint32_t uhccoms;
inf = dev_get_platdata(dev);
if (cpu_is_pxa3xx())
pxa3xx_u2d_stop_hc(&hcd->self);
if (inf->exit)
inf->exit(dev);
pxa27x_reset_hc(pxa_ohci);
/* Host Controller Reset */
uhccoms = __raw_readl(pxa_ohci->mmio_base + UHCCOMS) | 0x01;
__raw_writel(uhccoms, pxa_ohci->mmio_base + UHCCOMS);
udelay(10);
clk_disable_unprepare(pxa_ohci->clk);
}
