char *get_cpu_name() { unsigned int extension_id = get_extension_chip_id(); if (cpu_is_sama5d3()) switch (extension_id) { case ARCH_EXID_SAMA5D31: return "SAMA5D31"; case ARCH_EXID_SAMA5D33: return "SAMA5D33"; case ARCH_EXID_SAMA5D34: return "SAMA5D34"; case ARCH_EXID_SAMA5D35: return "SAMA5D35"; default: return "Unknown CPU type"; } else return "Unknown CPU type"; }
/* Actual code that puts the SoC in different idle states */ static int at91_enter_idle(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { if (cpu_is_at91rm9200()) at91rm9200_standby(); else if (cpu_is_at91sam9g45()) at91sam9g45_standby(); else if (cpu_is_at91sam9263()) at91sam9263_standby(); else if (cpu_is_at91sam9x5() || cpu_is_at91sam9n12() || cpu_is_sama5d3() || cpu_is_sama5d4()) at91sam_ddrc_standby(); else at91sam9_standby(); return index; }
char *get_cpu_name() { unsigned int extension_id = get_extension_chip_id(); if (cpu_is_sama5d3()) switch (extension_id) { case ARCH_EXID_SAMA5D31: return CONFIG_SYS_AT91_D31_CPU_NAME; case ARCH_EXID_SAMA5D33: return CONFIG_SYS_AT91_D33_CPU_NAME; case ARCH_EXID_SAMA5D34: return CONFIG_SYS_AT91_D34_CPU_NAME; case ARCH_EXID_SAMA5D35: return CONFIG_SYS_AT91_D35_CPU_NAME; case ARCH_EXID_SAMA5D36: return CONFIG_SYS_AT91_D36_CPU_NAME; default: return CONFIG_SYS_AT91_UNKNOWN_CPU; } else return CONFIG_SYS_AT91_UNKNOWN_CPU; }
static int at91_pm_enter(suspend_state_t state) { if (of_have_populated_dt()) at91_pinctrl_gpio_suspend(); else at91_gpio_suspend(); at91_irq_suspend(); pr_debug("AT91: PM - wake mask %08x, pm state %d\n", /* remember all the always-wake irqs */ (at91_pmc_read(AT91_PMC_PCSR) | (1 << AT91_ID_FIQ) | (1 << AT91_ID_SYS) | (at91_extern_irq)) & at91_aic_read(AT91_AIC_IMR), state); switch (state) { /* * Suspend-to-RAM is like STANDBY plus slow clock mode, so * drivers must suspend more deeply: only the master clock * controller may be using the main oscillator. */ case PM_SUSPEND_MEM: /* * Ensure that clocks are in a valid state. */ if (!at91_pm_verify_clocks()) goto error; /* * Enter slow clock mode by switching over to clk32k and * turning off the main oscillator; reverse on wakeup. */ if (slow_clock) { int memctrl = AT91_MEMCTRL_SDRAMC; if (cpu_is_at91rm9200()) memctrl = AT91_MEMCTRL_MC; else if (cpu_is_at91sam9g45() || cpu_is_at91sam9x5() || cpu_is_at91sam9n12() || cpu_is_sama5d3()) memctrl = AT91_MEMCTRL_DDRSDR; #ifdef CONFIG_AT91_SLOW_CLOCK /* copy slow_clock handler to SRAM, and call it */ memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz); #endif slow_clock(at91_pmc_base, at91_ramc_base[0], at91_ramc_base[1], memctrl); break; } else { pr_info("AT91: PM - no slow clock mode enabled ...\n"); /* FALLTHROUGH leaving master clock alone */ } /* * STANDBY mode has *all* drivers suspended; ignores irqs not * marked as 'wakeup' event sources; and reduces DRAM power. * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and * nothing fancy done with main or cpu clocks. */ case PM_SUSPEND_STANDBY: /* * NOTE: the Wait-for-Interrupt instruction needs to be * in icache so no SDRAM accesses are needed until the * wakeup IRQ occurs and self-refresh is terminated. * For ARM 926 based chips, this requirement is weaker * as at91sam9 can access a RAM in self-refresh mode. */ if (cpu_is_at91rm9200()) at91rm9200_standby(); else if (cpu_is_at91sam9g45()) at91sam_ddr_standby(2); else if (cpu_is_at91sam9x5() || cpu_is_at91sam9n12() || cpu_is_sama5d3()) at91sam_ddr_standby(1); else at91sam9_standby(); break; case PM_SUSPEND_ON: cpu_do_idle(); break; default: pr_debug("AT91: PM - bogus suspend state %d\n", state); goto error; } pr_debug("AT91: PM - wakeup %08x\n", at91_aic_read(AT91_AIC_IPR) & at91_aic_read(AT91_AIC_IMR)); error: target_state = PM_SUSPEND_ON; at91_irq_resume(); if (of_have_populated_dt()) at91_pinctrl_gpio_resume(); else at91_gpio_resume(); return 0; }