int validate_cpu(void)
{
u32 *err_flags;
int cpu_level, req_level;
const unsigned char *msg_strs;
check_cpu(&cpu_level, &req_level, &err_flags);
if (cpu_level < req_level) {
printf("This kernel requires an %s CPU, ",
cpu_name(req_level));
printf("but only detected an %s CPU.\n",
cpu_name(cpu_level));
return -1;
}
if (err_flags) {
int i, j;
puts("This kernel requires the following features "
"not present on the CPU:\n");
msg_strs = (const unsigned char *)x86_cap_strs;
for (i = 0; i < NCAPINTS; i++) {
u32 e = err_flags[i];
for (j = 0; j < 32; j++) {
if (msg_strs[0] < i ||
(msg_strs[0] == i && msg_strs[1] < j)) {
/* Skip to the next string */
msg_strs += 2;
while (*msg_strs++)
;
}
if (e & 1) {
if (msg_strs[0] == i &&
msg_strs[1] == j &&
msg_strs[2])
printf("%s ", msg_strs+2);
else
printf("%d:%d ", i, j);
}
e >>= 1;
}
}
putchar('\n');
return -1;
} else {
return 0;
int checkboard(void)
{
u8 sw;
char buf[15];
cpu_name(buf);
printf("Board: %s-RDB, ", buf);
sw = QIXIS_READ(arch);
printf("Board Arch: V%d, ", sw >> 4);
printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
sw = QIXIS_READ(brdcfg[0]);
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
if (sw < 0x8)
printf("vBank: %d\n", sw);
else if (sw == 0x9)
puts("NAND\n");
else
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
puts("SERDES1 Reference : ");
printf("Clock1 = 156.25MHz ");
printf("Clock2 = 156.25MHz");
puts("\nSERDES2 Reference : ");
printf("Clock1 = 100MHz ");
printf("Clock2 = 100MHz\n");
return 0;
}
/*
* Save l's FPU state, which may be on this processor or another processor.
* It may take some time, so we avoid disabling preemption where possible.
* Caller must know that the target LWP is stopped, otherwise this routine
* may race against it.
*/
void
fpusave_lwp(struct lwp *l, bool save)
{
struct cpu_info *oci;
struct pcb *pcb;
int s, spins, ticks;
spins = 0;
ticks = hardclock_ticks;
for (;;) {
s = splhigh();
pcb = lwp_getpcb(l);
oci = pcb->pcb_fpcpu;
if (oci == NULL) {
splx(s);
break;
}
if (oci == curcpu()) {
KASSERT(oci->ci_fpcurlwp == l);
fpusave_cpu(save);
splx(s);
break;
}
splx(s);
#ifdef XEN
if (xen_send_ipi(oci, XEN_IPI_SYNCH_FPU) != 0) {
panic("xen_send_ipi(%s, XEN_IPI_SYNCH_FPU) failed.",
cpu_name(oci));
}
#else /* XEN */
x86_send_ipi(oci, X86_IPI_SYNCH_FPU);
#endif
while (pcb->pcb_fpcpu == oci && ticks == hardclock_ticks) {
x86_pause();
spins++;
}
if (spins > 100000000) {
panic("fpusave_lwp: did not");
}
}
if (!save) {
/* Ensure we restart with a clean slate. */
l->l_md.md_flags &= ~MDL_USEDFPU;
}
}
/*
* Prints available information about the board
*/
void print_board_info(void)
{
u32 ahb_clk, cpu_clk, ddr_clk, spi_clk, ref_clk;
#if defined(CONFIG_PCI)
u32 did, vid;
#endif
u32 bank;
bd_t *bd = gd->bd;
char buffer[24];
/* Show warning if last reboot was caused by SOC watchdog */
if (last_reset_wdt())
printf_wrn("reset caused by watchdog!\n\n");
/* Board name */
printf("%" ALIGN_SIZE "s %s\n",
"BOARD:", MK_STR(CONFIG_BOARD_CUSTOM_STRING));
/* SOC name, version and revision */
qca_soc_name_rev(buffer);
printf("%" ALIGN_SIZE "s %s\n", "SOC:", buffer);
/* MIPS CPU type */
cpu_name(buffer);
printf("%" ALIGN_SIZE "s %s\n", "CPU:", buffer);
/* RAM size and type */
printf("%" ALIGN_SIZE "s ", "RAM:");
print_size(bd->bi_memsize, "");
switch (qca_dram_type()) {
case RAM_MEMORY_TYPE_SDR:
puts(" SDR ");
break;
case RAM_MEMORY_TYPE_DDR1:
puts(" DDR1 ");
break;
case RAM_MEMORY_TYPE_DDR2:
puts(" DDR2 ");
break;
default:
break;
}
/* DDR interface width */
printf("%d-bit ", qca_dram_ddr_width());
/* tCL-tRCD-tRP-tRAS latency */
printf("CL%d-%d-%d-%d\n", qca_dram_cas_lat(),
qca_dram_trcd_lat(),
qca_dram_trp_lat(),
qca_dram_tras_lat());
/* SPI NOR FLASH sizes and types */
printf("%" ALIGN_SIZE "s ", "FLASH:");
for (bank = 0; bank < CFG_MAX_FLASH_BANKS; bank++) {
if (flash_info[bank].size == 0)
continue;
if (bank > 0)
printf("%" ALIGN_SIZE "s ", " ");
print_size(flash_info[bank].size, "");
if (flash_info[bank].manuf_name != NULL)
printf(" %s", flash_info[bank].manuf_name);
if (flash_info[bank].model_name != NULL)
printf(" %s", flash_info[bank].model_name);
puts("\n");
}
/* PCIE device/s info */
#if defined(CONFIG_PCI)
printf("%" ALIGN_SIZE "s ", "PCIe:");
#if (SOC_TYPE & QCA_AR934X_SOC) |\
(SOC_TYPE & QCA_QCA955X_SOC)
if (!qca_pcie0_in_ep_mode()) {
if (qca_pcie_dev_info(0, &vid, &did))
printf("%04X:%04X", vid, did);
else
puts("no device");
} else {
puts("EP mode");
}
#elif (SOC_TYPE & QCA_QCA953X_SOC)
if (qca_pcie_dev_info(0, &vid, &did))
printf("%04X:%04X", vid, did);
else
puts("no device");
#endif
#if (SOC_TYPE & QCA_QCA956X_SOC)
if (qca_pcie_dev_info(1, &vid, &did))
printf("%04X:%04X", vid, did);
else
puts("no device");
#elif (SOC_TYPE & QCA_QCA955X_SOC)
if (qca_pcie_dev_info(1, &vid, &did))
printf(", %04X:%04X", vid, did);
else
puts(", no device");
#endif
puts("\n");
#endif
/* MAC address */
printf("%" ALIGN_SIZE "s %02X:%02X:%02X:%02X:%02X:%02X", "MAC:",
bd->bi_enetaddr[0],bd->bi_enetaddr[1], bd->bi_enetaddr[2],
bd->bi_enetaddr[3], bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
if (mac_is_not_valid)
puts(" (fixed)\n");
else
puts("\n");
/* System clocks */
printf("%" ALIGN_SIZE "s CPU/RAM/AHB/SPI/REF\n", "CLOCKS:");
qca_sys_clocks(&cpu_clk, &ddr_clk, &ahb_clk, &spi_clk, &ref_clk);
cpu_clk = cpu_clk / 1000000;
ddr_clk = ddr_clk / 1000000;
ahb_clk = ahb_clk / 1000000;
spi_clk = spi_clk / 1000000;
ref_clk = ref_clk / 1000000;
printf("%" ALIGN_SIZE "s %3d/%3d/%3d/%3d/%3d MHz\n",
" ", cpu_clk, ddr_clk, ahb_clk, spi_clk, ref_clk);
puts("\n");
}
