status_t block_device_init_driver (void)
{
int32_t i ;
char alpha_num[8], semaphore_name_buffer[64], * semaphore_prefix = "block_device_" ;
char isr_semaphore_name[64] ;
watch (status_t)
{
block_device_controls = kernel_malloc (sizeof (block_device_control_t) *
SOCLIB_BLOCK_DEVICES_NDEV, true) ;
ensure (block_device_controls != NULL, DNA_OUT_OF_MEM) ;
for (i = 0 ; i < SOCLIB_BLOCK_DEVICES_NDEV ; i++)
{
dna_itoa (i, alpha_num) ;
dna_strcpy (semaphore_name_buffer, semaphore_prefix) ;
dna_strcat (semaphore_name_buffer, alpha_num) ;
dna_strcat (semaphore_name_buffer, "_sem") ;
semaphore_create (semaphore_name_buffer, 1,
&block_device_controls[i] . semaphore_id) ;
block_device_controls[i] . should_enable_irq =
(bool) SOCLIB_BLOCK_DEVICES[i] . should_enable_irq ;
block_device_controls[i] . port =
(block_device_register_map_t) SOCLIB_BLOCK_DEVICES[i] . base_address ;
cpu_read (UINT32,
& (block_device_controls[i] . port -> BLOCK_DEVICE_SIZE),
block_device_controls[i] . block_count) ;
cpu_read (UINT32,
& (block_device_controls[i] . port -> BLOCK_DEVICE_BLOCK_SIZE),
block_device_controls[i] . block_size) ;
if (block_device_controls[i] . should_enable_irq) {
block_device_controls[i] . irq = SOCLIB_BLOCK_DEVICES[i] . irq ;
interrupt_attach (0, SOCLIB_BLOCK_DEVICES[i] . irq, 0x0,
block_device_isr, false) ;
dna_strcpy (isr_semaphore_name, semaphore_name_buffer) ;
dna_strcat (isr_semaphore_name, "_isr") ;
semaphore_create (isr_semaphore_name, 0,
&block_device_controls[i] . isr_semaphore_id) ;
}
}
return DNA_OK ;
}
}
static INLINE u8 memread(u32 addr)
{
static int n;
//handle dpcm cycle stealing
if(nes->cpu.pcmcycles) {
n = nes->cpu.pcmcycles - 1;
nes->cpu.pcmcycles = 0;
if(addr == 0x4016 || addr == 0x4017) {
if(n--)
memread(addr);
while(n--)
cpu_tick();
}
else {
while(n--)
memread(addr);
}
apu_dpcm_fetch();
}
//increment cycle counter, check irq lines
cpu_tick();
//read data from address
return(cpu_read(addr));
}
void cheat_create_cheat_map()
{
int i;
memset(cheat_map,0,sizeof(cheat_map));
for (i=0; i<nCheats; i++){
cheat_dat *tmp=&cheats[i];
if (!tmp->enable)
continue;
cheat_map[tmp->adr] = 1;
cheat_map_n[tmp->adr] = i;
switch(tmp->code){
case 0x00:
cpu_write_direct(tmp->adr, tmp->dat);
tmp->enable = false;
cheat_map[tmp->adr] = 0;
break;
case 0x01:
tmp->dat_old = cpu_read(tmp->adr);
cpu_write_direct(tmp->adr, tmp->dat);
break;
case 0x90:
case 0x91:
case 0x92:
case 0x93:
case 0x94:
case 0x95:
case 0x96:
case 0x97:
if ((tmp->adr>=0xD000)&&(tmp->adr<0xE000)){
int ram_adr = (tmp->code-0x90)*0x1000 + tmp->adr - 0xD000;
tmp->dat_old = ram[ram_adr];
ram[ram_adr] = tmp->dat;
}
else{
tmp->dat_old = cpu_read(tmp->adr);
cpu_write_direct(tmp->adr, tmp->dat);
}
break;
}
}
}
status_t d940_ethernet_control (void * handler, int32_t function,
void * arguments, int32_t * p_ret)
{
d940_eth_data_t * pdata = (d940_eth_data_t *) handler;
d940_eth_t d940_ethernet_device = pdata->dev;
switch (function)
{
case DNA_GET_ETH_LINK_STATUS:
d940_ethernet_phy_manage(pdata);
*(((uint32_t **)arguments)[0]) = pdata->phy_status & BMSR_LSTATUS;
break;
case DNA_GET_ETH_MAC:
{
interrupt_status_t it_status;
uint32_t tmp, tmp2;
it_status = cpu_trap_mask_and_backup();
lock_acquire(&pdata->lock);
/* Copy the MAC address */
cpu_read(UINT32, &(d940_ethernet_device->sa1.addr_l), tmp);
cpu_read(UINT32, &(d940_ethernet_device->sa1.addr_h), tmp2);
lock_release(&pdata->lock);
cpu_trap_restore(it_status);
dna_memcpy(((uint32_t **)arguments)[0], &tmp, 4);
dna_memcpy(((uint32_t **)arguments)[0] +1, &tmp2, 2);
break;
}
case DNA_GET_ETH_RX_STATS:
dna_memcpy(((uint32_t **)arguments)[0], &pdata->rx_count,
sizeof(int32_t));
break;
case DNA_GET_ETH_TX_STATS:
dna_memcpy(((uint32_t **)arguments)[0], &pdata->tx_count,
sizeof(int32_t));
break;
default:
return DNA_ERROR;
}
return DNA_OK;
}
status_t d940_mmc_read_low (void * buffer, int32_t word_count)
{
d940_mmc_status_t status;
for (int32_t i = 0; i < word_count; i += 1)
{
do
{
cpu_read (UINT32, & (PLATFORM_MCI_BASE -> SR), status . raw);
}
while (status . bits . receiver_ready == 0);
cpu_read (UINT32, & (PLATFORM_MCI_BASE -> RDR),
((uint32_t *)buffer)[i]);
}
return DNA_OK;
}
void dump_stack(cpu_t *cpu, uint8_t words)
{
uint32_t sp = cpu->sp;
puts("Stack Dump");
for(;sp != 0x00FFFFFC && sp - cpu->sp < 40; sp += 4)
{
printf("%08x = 0x%08x\n", sp+4, cpu_read(sp+4,cpu));
}
}
void platform_debug_puts (char * string)
{
uint32_t res = 0;
for (int32_t i = 0; string[i] != '\0'; i += 1)
{
do cpu_read (UINT32, & (PLATFORM_DBGU_BASE -> SR), res);
while ((res & 0x202) != 0x202);
cpu_write (UINT32, & (PLATFORM_DBGU_BASE -> THR), string[i]);
}
}
int Nsf_Impl::read_mem( addr_t addr )
{
int result = low_ram [addr & (low_ram_size-1)]; // also handles wrap-around
if ( addr & 0xE000 )
{
result = *cpu.get_code( addr );
if ( addr < sram_addr )
{
if ( addr == apu.status_addr )
result = apu.read_status( time() );
else
result = cpu_read( addr );
}
}
return LOG_MEM( addr, ">", result );
}
static inline cpu_syscall(Cpu *cpu, int *ret_val){
printf("syscall");
reg call_type = cpu->r[Tyr];
reg arg_1 = cpu->r[Glu];
reg arg_2 = cpu->r[Lys];
switch (call_type){
case sys_read:
cpu_read(cpu, arg_1, arg_2);
break;
case sys_write:
cpu_write(cpu, arg_1, arg_2);
break;
case sys_exit:
cpu_exit(cpu, ret_val);
break;
default:
p_errno = INV_SYSCALL;
break;
}
}
unsigned char SNES_SPC::ReadByte(unsigned int address)
{
return cpu_read(address);
}
status_t d940_ethernet_write (void * handler, void * source, int64_t offset,
int32_t * p_count) {
d940_eth_data_t * pdata = (d940_eth_data_t *) handler;
d940_eth_t d940_ethernet_device = pdata->dev;
d940_eth_ncr_t ncr;
d940_eth_tsr_t tsr;
int32_t buffer_index;
void * data = source;
int32_t buffer_size;
int32_t i;
int32_t frame_size = *p_count;
interrupt_status_t it_status;
if(frame_size < 0)
{
return DNA_BAD_ARGUMENT;
}
if(pdata->tx_write == 0)
{
pdata->tx_write = *((int32_t *) data);
return DNA_OK;
}
it_status = cpu_trap_mask_and_backup();
lock_acquire(&pdata->lock);
/* Check/Clear the status of the transmit */
cpu_read(UINT32, &(d940_ethernet_device->tsr.raw), tsr.raw);
cpu_write(UINT32, &(d940_ethernet_device->tsr.raw), tsr.raw);
lock_release(&pdata->lock);
cpu_trap_restore(it_status);
if(tsr.bits.und)
{
log(INFO_LEVEL, "Underrun: Clear the transmit buffer list");
it_status = cpu_trap_mask_and_backup();
lock_acquire(&pdata->lock);
/* Stop the transmit in case of underrun */
cpu_read(UINT32, &(d940_ethernet_device->ncr.raw), ncr.raw);
ncr.bits.te = 0;
cpu_write(UINT32, &(d940_ethernet_device->ncr.raw), ncr.raw);
ncr.bits.te = 1;
cpu_write(UINT32, &(d940_ethernet_device->ncr.raw), ncr.raw);
lock_release(&pdata->lock);
cpu_trap_restore(it_status);
/* ReInit the transmit */
pdata->tx_tail = 0;
/* ReInit the semaphore */
while(semaphore_acquire(pdata->tx_sem, 1, DNA_RELATIVE_TIMEOUT, 0)
== DNA_OK);
semaphore_release(pdata->tx_sem, TX_PACKET_LIMIT, 0);
/* Clear the buffers */
for(i = 0; i < D940_ETH_TX_BUFFER_COUNT; i++)
{
pdata->transmit_descs[i].used = 1;
}
}
buffer_index = pdata->tx_tail;
while(frame_size > 0)
{
cpu_cache_invalidate(CPU_CACHE_DATA, &pdata->transmit_descs[buffer_index],
sizeof(struct tbde));
buffer_size = D940_ETH_TX_BUFFER_SIZE;
if(buffer_size > frame_size)
{
buffer_size = frame_size;
}
/* Copy in the transmit buffer */
dna_memcpy(&pdata->transmit_buffers[buffer_index * D940_ETH_TX_BUFFER_SIZE],
data, buffer_size);
data += buffer_size;
frame_size -= buffer_size;
pdata->tx_write -= buffer_size;
/* Set the transmit buffer as ready to send */
pdata->transmit_descs[buffer_index].len = buffer_size;
pdata->transmit_descs[buffer_index].used = 0;
/* Last chunk ? */
if(pdata->tx_write != 0)
{
pdata->transmit_descs[buffer_index].last = 0;
}
else
{
pdata->transmit_descs[buffer_index].last = 1;
}
buffer_index = NEXT_TX_BUFFER(buffer_index);
}
/* Next Packet invalid */
pdata->transmit_descs[buffer_index].used = 1;
pdata->tx_tail = buffer_index;
if(pdata->tx_write == 0)
{
/* Force to flush the cache */
cpu_cache_sync();
it_status = cpu_trap_mask_and_backup();
lock_acquire(&pdata->lock);
/* Restart the transmission */
cpu_read(UINT32, &(d940_ethernet_device->ncr.raw), ncr.raw);
ncr.bits.tstart = 1;
cpu_write(UINT32, &(d940_ethernet_device->ncr.raw), ncr.raw);
lock_release(&pdata->lock);
cpu_trap_restore(it_status);
semaphore_acquire(pdata->tx_sem, 1, 0, 0);
}
return DNA_OK;
}
status_t d940_ethernet_open (char * name, int32_t mode, void ** data)
{
d940_eth_t d940_ethernet_device;
d940_eth_data_t * pdata;
d940_eth_int_t interrupt;
d940_eth_ncr_t ncr;
d940_eth_ncfgr_t ncfgr;
d940_eth_usrio_t usrio;
interrupt_status_t it_status;
uint32_t i;
if(data == NULL) return DNA_ERROR;
/* /!\ Only for one device /!\ */
if(dna_strcmp (name, d940_ethernet_devices[0]) != 0) return DNA_ERROR;
pdata = d940_ethernet_handlers[0];
/* Exclusive access */
it_status = cpu_trap_mask_and_backup();
lock_acquire(&pdata->lock);
if(pdata->ref != 0)
{
lock_release(&pdata->lock);
cpu_trap_restore(it_status);
return DNA_ERROR;
}
pdata->ref += 1;
lock_release(&pdata->lock);
cpu_trap_restore(it_status);
/* Set device access */
d940_ethernet_device = pdata->dev;
*data = pdata;
/* Init all the semaphore */
while(semaphore_acquire(pdata->mio_sem, 1, DNA_RELATIVE_TIMEOUT, 0)
== DNA_OK);
while(semaphore_acquire(pdata->mio_comp_sem, 1, DNA_RELATIVE_TIMEOUT, 0)
== DNA_OK);
while(semaphore_acquire(pdata->tx_sem, 1, DNA_RELATIVE_TIMEOUT, 0)
== DNA_OK);
while(semaphore_acquire(pdata->rx_sem, 1, DNA_RELATIVE_TIMEOUT, 0)
== DNA_OK);
/* Set the limit of packet in the transmit buffers */
semaphore_release(pdata->mio_sem, 1, 0);
semaphore_release(pdata->tx_sem, TX_PACKET_LIMIT, 0);
/* Initialisation of transmit buffer descriptor */
for(i = 0; i < D940_ETH_TX_BUFFER_COUNT; i++)
{
pdata->transmit_descs[i].addr =
((uint32_t)(& pdata->transmit_buffers[i * D940_ETH_TX_BUFFER_SIZE]));
pdata->transmit_descs[i].used = 1;
pdata->transmit_descs[i].wrap = 0;
pdata->transmit_descs[i].no_crc = 0;
}
pdata->transmit_descs[i-1].wrap = 1;
/* Initialisation of receive buffer descriptor */
for(i = 0; i < D940_ETH_RX_BUFFER_COUNT; i++)
{
pdata->receive_descs[i].addr =
((uint32_t)(& pdata->receive_buffers[i * D940_ETH_RX_BUFFER_SIZE])) >> 2;
pdata->receive_descs[i].owner = 0;
pdata->receive_descs[i].wrap = 0;
}
pdata->receive_descs[i-1].wrap = 1;
/* Initialisation of the tails */
pdata->tx_tail = 0;
pdata->rx_tail = 0;
pdata->rx_read = false;
pdata->tx_write = 0;
/* Initialisation of the stats */
pdata->tx_count = 0;
pdata->rx_count = 0;
/* Configure the PHY */
pdata->phy_status = 0;
d940_ethernet_phy_probe(pdata);
d940_ethernet_phy_manage(pdata);
it_status = cpu_trap_mask_and_backup();
lock_acquire(&pdata->lock);
/* Configure the device (depends of PHY) */
cpu_read(UINT32, &(d940_ethernet_device->ncfgr.raw), ncfgr.raw);
ncfgr.bits.rbof = 0;
ncfgr.bits.drfcs = 1;
ncfgr.bits.pae = 1;
cpu_write(UINT32, &(d940_ethernet_device->ncfgr.raw), ncfgr.raw);
/* Configure MII */
cpu_read(UINT32, &(d940_ethernet_device->usrio.raw), usrio.raw);
usrio.bits.clken = 0;
usrio.bits.rmii = 0;
cpu_write(UINT32, &(d940_ethernet_device->usrio.raw), usrio.raw);
/* Enable Interrupt (NO TXUBR & NO MFD) */
interrupt.raw = 0x00003cf6;
cpu_write(UINT32, &(d940_ethernet_device->ier.raw), interrupt.raw);
/* Start Receive/Transmit */
cpu_read(UINT32, &(d940_ethernet_device->ncr.raw), ncr.raw);
ncr.bits.re = 1;
ncr.bits.te = 1;
ncr.bits.clrstat = 1;
cpu_write(UINT32, &(d940_ethernet_device->ncr.raw), ncr.raw);
lock_release(&pdata->lock);
cpu_trap_restore(it_status);
return DNA_OK;
}