static int xilinx_uartlite_init(SysBusDevice *dev) { struct xlx_uartlite *s = FROM_SYSBUS(typeof (*s), dev); int uart_regs; sysbus_init_irq(dev, &s->irq); uart_update_status(s); uart_regs = cpu_register_io_memory(uart_read, uart_write, s, DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, R_MAX * 4, uart_regs); s->chr = qdev_init_chardev(&dev->qdev); if (s->chr) qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s); return 0; }
PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base, qemu_irq irq) { int iomemtype; PXA2xxKeyPadState *s; s = (PXA2xxKeyPadState *) qemu_mallocz(sizeof(PXA2xxKeyPadState)); s->irq = irq; iomemtype = cpu_register_io_memory(pxa2xx_keypad_readfn, pxa2xx_keypad_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x00100000, iomemtype); vmstate_register(NULL, 0, &vmstate_pxa2xx_keypad, s); return s; }
static int lm32_timer_init(SysBusDevice *dev) { LM32TimerState *s = FROM_SYSBUS(typeof(*s), dev); int timer_regs; sysbus_init_irq(dev, &s->irq); s->bh = qemu_bh_new(timer_hit, s); s->ptimer = ptimer_init(s->bh); ptimer_set_freq(s->ptimer, s->freq_hz); timer_regs = cpu_register_io_memory(timer_read_fn, timer_write_fn, s, DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, R_MAX * 4, timer_regs); return 0; }
static void etraxfs_ser_init(SysBusDevice *dev) { struct etrax_serial *s = FROM_SYSBUS(typeof (*s), dev); int ser_regs; /* transmitter begins ready and idle. */ s->regs[RS_STAT_DIN] |= (1 << STAT_TR_RDY); s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE); sysbus_init_irq(dev, &s->irq); ser_regs = cpu_register_io_memory(ser_read, ser_write, s); sysbus_init_mmio(dev, R_MAX * 4, ser_regs); s->chr = qdev_init_chardev(&dev->qdev); if (s->chr) qemu_chr_add_handlers(s->chr, serial_can_receive, serial_receive, serial_event, s); }
void icp_pit_init(uint32_t base, qemu_irq *pic, int irq) { int iomemtype; icp_pit_state *s; s = (icp_pit_state *)qemu_mallocz(sizeof(icp_pit_state)); /* Timer 0 runs at the system clock speed (40MHz). */ s->timer[0] = arm_timer_init(40000000, pic[irq]); /* The other two timers run at 1MHz. */ s->timer[1] = arm_timer_init(1000000, pic[irq + 1]); s->timer[2] = arm_timer_init(1000000, pic[irq + 2]); iomemtype = cpu_register_io_memory(0, icp_pit_readfn, icp_pit_writefn, s); cpu_register_physical_memory(base, 0x00001000, iomemtype); /* This device has no state to save/restore. The component timers will save themselves. */ }
void sp804_init(uint32_t base, qemu_irq irq) { int iomemtype; sp804_state *s; qemu_irq *qi; s = (sp804_state *)qemu_mallocz(sizeof(sp804_state)); qi = qemu_allocate_irqs(sp804_set_irq, s, 2); s->irq = irq; /* ??? The timers are actually configurable between 32kHz and 1MHz, but we don't implement that. */ s->timer[0] = arm_timer_init(1000000, qi[0]); s->timer[1] = arm_timer_init(1000000, qi[1]); iomemtype = cpu_register_io_memory(0, sp804_readfn, sp804_writefn, s); cpu_register_physical_memory(base, 0x00001000, iomemtype); register_savevm("sp804", -1, 1, sp804_save, sp804_load, s); }
static int lance_init(SysBusDevice *dev) { SysBusPCNetState *d = FROM_SYSBUS(SysBusPCNetState, dev); PCNetState *s = &d->state; s->mmio_index = cpu_register_io_memory(lance_mem_read, lance_mem_write, d); qdev_init_gpio_in(&dev->qdev, parent_lance_reset, 1); sysbus_init_mmio(dev, 4, s->mmio_index); sysbus_init_irq(dev, &s->irq); s->phys_mem_read = ledma_memory_read; s->phys_mem_write = ledma_memory_write; return pcnet_common_init(&dev->qdev, s, &net_lance_info); }
static int smc91c111_init1(SysBusDevice *dev) { smc91c111_state *s = FROM_SYSBUS(smc91c111_state, dev); s->mmio_index = cpu_register_io_memory(smc91c111_readfn, smc91c111_writefn, s); sysbus_init_mmio(dev, 16, s->mmio_index); sysbus_init_irq(dev, &s->irq); qemu_macaddr_default_if_unset(&s->conf.macaddr); smc91c111_reset(s); s->nic = qemu_new_nic(&net_smc91c111_info, &s->conf, dev->qdev.info->name, dev->qdev.id, s); qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); /* ??? Save/restore. */ return 0; }
static int stm32l_sys_init(uint32_t base, qemu_irq irq, stm32_board_info * board) { int iomemtype; ssys_state *s; s = (ssys_state *)g_malloc0(sizeof(ssys_state)); s->irq = irq; s->board = board; iomemtype = cpu_register_io_memory(ssys_readfn, ssys_writefn, s, DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(base, 0x00001000, iomemtype); ssys_reset(s); vmstate_register(NULL, -1, &vmstate_stm32_sys, s); return 0; }
PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base, qemu_irq irq) { int iomemtype; PXA2xxKeyPadState *s; s = (PXA2xxKeyPadState *) qemu_mallocz(sizeof(PXA2xxKeyPadState)); s->irq = irq; iomemtype = cpu_register_io_memory(pxa2xx_keypad_readfn, pxa2xx_keypad_writefn, s); cpu_register_physical_memory(base, 0x00100000, iomemtype); register_savevm("pxa2xx_keypad", 0, 0, pxa2xx_keypad_save, pxa2xx_keypad_load, s); return s; }
static int lm32_uart_init(SysBusDevice *dev) { LM32UartState *s = FROM_SYSBUS(typeof(*s), dev); int uart_regs; sysbus_init_irq(dev, &s->irq); uart_regs = cpu_register_io_memory(uart_read_fn, uart_write_fn, s, DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, R_MAX * 4, uart_regs); s->chr = qdev_init_chardev(&dev->qdev); if (s->chr) { qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s); } return 0; }
/* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is * modified, it should be retrieved with msix_bar_size. */ int msix_init(struct PCIDevice *dev, unsigned short nentries, unsigned bar_nr, unsigned bar_size) { int ret; /* Nothing to do if MSI is not supported by interrupt controller */ if (!msix_supported) return -ENOTSUP; if (nentries > MSIX_MAX_ENTRIES) return -EINVAL; dev->msix_entry_used = qemu_mallocz(MSIX_MAX_ENTRIES * sizeof *dev->msix_entry_used); dev->msix_table_page = qemu_mallocz(MSIX_PAGE_SIZE); msix_mask_all(dev, nentries); dev->msix_mmio_index = cpu_register_io_memory(msix_mmio_read, msix_mmio_write, dev, DEVICE_NATIVE_ENDIAN); if (dev->msix_mmio_index == -1) { ret = -EBUSY; goto err_index; } dev->msix_entries_nr = nentries; ret = msix_add_config(dev, nentries, bar_nr, bar_size); if (ret) goto err_config; dev->cap_present |= QEMU_PCI_CAP_MSIX; return 0; err_config: dev->msix_entries_nr = 0; cpu_unregister_io_memory(dev->msix_mmio_index); err_index: qemu_free(dev->msix_table_page); dev->msix_table_page = NULL; qemu_free(dev->msix_entry_used); dev->msix_entry_used = NULL; return ret; }
static void sp804_init(SysBusDevice *dev) { int iomemtype; sp804_state *s = FROM_SYSBUS(sp804_state, dev); qemu_irq *qi; qi = qemu_allocate_irqs(sp804_set_irq, s, 2); sysbus_init_irq(dev, &s->irq); /* ??? The timers are actually configurable between 32kHz and 1MHz, but we don't implement that. */ s->timer[0] = arm_timer_init(1000000); s->timer[1] = arm_timer_init(1000000); s->timer[0]->irq = qi[0]; s->timer[1]->irq = qi[1]; iomemtype = cpu_register_io_memory(0, sp804_readfn, sp804_writefn, s); sysbus_init_mmio(dev, 0x1000, iomemtype); register_savevm("sp804", -1, 1, sp804_save, sp804_load, s); }
static int at91_pio_init(SysBusDevice *dev) { PIOState *s = FROM_SYSBUS(typeof (*s), dev); int pio_regs; sysbus_init_irq(dev, &s->parent_irq); qdev_init_gpio_in(&dev->qdev, at91_pio_set_pin, PIO_PINS * 3); qdev_init_gpio_out(&dev->qdev, s->out, PIO_PINS * 3); pio_regs = cpu_register_io_memory(at91_pio_readfn, at91_pio_writefn, s, DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, PIO_SIZE, pio_regs); at91_pio_reset(s); qemu_register_reset(at91_pio_reset, s); //register_savevm(&dev->qdev, "at91_pio", -1, 1, at91_pio_save, at91_pio_load, s); vmstate_register(&dev->qdev, -1, &vmstate_at91sam9_pio, s); return 0; }
static int s5pc1xx_onedram_init1(SysBusDevice *dev, ModemPlatformData *mp) { S5pc1xxOneDRAMState *s = FROM_SYSBUS(S5pc1xxOneDRAMState, dev); int onedram_io; sysbus_init_irq(dev, &s->irq_onedram_int_ap); onedram_io = cpu_register_io_memory(onedram_mm_read, onedram_mm_write, s); sysbus_init_mmio(dev, ONEDRAM_REGISTER_SIZE, onedram_io); s->sem = 0; s->mbx_ab = 0; s->mbx_ba = 0; s->check_ab = 0; s->check_ba = 0; s->irq_onedram_int_ap_pending = 0; s->irq_onedram_int_cp_pending = 0; s->vmodem_connected = 0; s->vmodem_bootup = 0; s->fmt_info = (ModemInfo *)qemu_mallocz(sizeof(ModemInfo)); s->socket_buffer = (uint8_t *)qemu_mallocz(SOCKET_BUFFER_MAX_SIZE); s->socket_len = 0; s->onedram_state.waiting_authority = FALSE; s->onedram_state.non_cmd = INT_MASK_CMD_NONE; s->onedram_state.send_size = 0; s->onedram_state.waiting_sem_rep = 0; s->onedram_state.send_buf = NULL; s->onedram_state.interruptable = 1; s->onedram_state.writable = 1; onedram_register_modem(s, mp); onedram_tcp_init(s); s->bootup_timer = qemu_new_timer(vm_clock, onedram_bootup, s); s->sem_timer = qemu_new_timer(vm_clock, onedram_wait_semaphore, s); return 0; }
static int syborg_virtio_init(SyborgVirtIOProxy *proxy, VirtIODevice *vdev) { int iomemtype; proxy->vdev = vdev; /* Don't support multiple vectors */ proxy->vdev->nvectors = 0; sysbus_init_irq(&proxy->busdev, &proxy->irq); iomemtype = cpu_register_io_memory(syborg_virtio_readfn, syborg_virtio_writefn, proxy); sysbus_init_mmio(&proxy->busdev, 0x1000, iomemtype); proxy->id = ((uint32_t)0x1af4 << 16) | vdev->device_id; qemu_register_reset(virtio_reset, vdev); virtio_bind_device(vdev, &syborg_virtio_bindings, proxy); return 0; }
static void smc91c111_init1(SysBusDevice *dev) { smc91c111_state *s = FROM_SYSBUS(smc91c111_state, dev); s->mmio_index = cpu_register_io_memory(smc91c111_readfn, smc91c111_writefn, s); sysbus_init_mmio(dev, 16, s->mmio_index); sysbus_init_irq(dev, &s->irq); qdev_get_macaddr(&dev->qdev, s->macaddr); smc91c111_reset(s); s->vc = qdev_get_vlan_client(&dev->qdev, smc91c111_can_receive, smc91c111_receive, NULL, smc91c111_cleanup, s); qemu_format_nic_info_str(s->vc, s->macaddr); register_savevm( "smc91c111", 0, SMC91C111_SAVE_VERSION, smc91c111_save, smc91c111_load, s); }
void smc91c111_init(NICInfo *nd, uint32_t base, void *pic, int irq) { smc91c111_state *s; int iomemtype; s = (smc91c111_state *)qemu_mallocz(sizeof(smc91c111_state)); iomemtype = cpu_register_io_memory(0, smc91c111_readfn, smc91c111_writefn, s); cpu_register_physical_memory(base, 16, iomemtype); s->base = base; s->pic = pic; s->irq = irq; memcpy(s->macaddr, nd->macaddr, 6); smc91c111_reset(s); s->vc = qemu_new_vlan_client(nd->vlan, smc91c111_receive, smc91c111_can_receive, s); /* ??? Save/restore. */ }
static int grlib_apbuart_init(SysBusDevice *dev) { UART *uart = FROM_SYSBUS(typeof(*uart), dev); int uart_regs = 0; qemu_chr_add_handlers(uart->chr, &grlib_handlers, uart); sysbus_init_irq(dev, &uart->irq); uart_regs = cpu_register_io_memory(grlib_apbuart_read, grlib_apbuart_write, uart, DEVICE_NATIVE_ENDIAN); if (uart_regs < 0) { return -1; } sysbus_init_mmio(dev, UART_REG_SIZE, uart_regs); return 0; }
static int s5pc1xx_keyif_init(SysBusDevice *dev) { S5pc1xxKeyIFState *s = FROM_SYSBUS(S5pc1xxKeyIFState, dev); int iomemtype; sysbus_init_irq(dev, &s->irq_keypad); iomemtype = cpu_register_io_memory(s5pc1xx_keyif_mm_read, s5pc1xx_keyif_mm_write, s); sysbus_init_mmio(dev, S5PC1XX_KEYIF_REG_MEM_SIZE, iomemtype); s5pc1xx_gpio_register_io_memory(GPIO_IDX_KEYIF, 0, s5pc1xx_keyif_gpio_readfn, s5pc1xx_keyif_gpio_writefn, NULL, s); s5pc1xx_init_keymap(); qemu_add_kbd_event_handler(s5pc1xx_keypad_event, s); s5pc1xx_keyif_reset(s); return 0; }
static void icp_pit_init(SysBusDevice *dev) { int iomemtype; icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev); /* Timer 0 runs at the system clock speed (40MHz). */ s->timer[0] = arm_timer_init(40000000); /* The other two timers run at 1MHz. */ s->timer[1] = arm_timer_init(1000000); s->timer[2] = arm_timer_init(1000000); sysbus_init_irq(dev, &s->timer[0]->irq); sysbus_init_irq(dev, &s->timer[1]->irq); sysbus_init_irq(dev, &s->timer[2]->irq); iomemtype = cpu_register_io_memory(0, icp_pit_readfn, icp_pit_writefn, s); sysbus_init_mmio(dev, 0x1000, iomemtype); /* This device has no state to save/restore. The component timers will save themselves. */ }
void smc91c111_init(NICInfo *nd, uint32_t base, qemu_irq irq) { smc91c111_state *s; int iomemtype; qemu_check_nic_model(nd, "smc91c111"); s = (smc91c111_state *)qemu_mallocz(sizeof(smc91c111_state)); iomemtype = cpu_register_io_memory(0, smc91c111_readfn, smc91c111_writefn, s); cpu_register_physical_memory(base, 16, iomemtype); s->irq = irq; memcpy(s->macaddr, nd->macaddr, 6); smc91c111_reset(s); s->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name, smc91c111_receive, smc91c111_can_receive, s); qemu_format_nic_info_str(s->vc, s->macaddr); /* ??? Save/restore. */ }
void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq, qemu_irq ch0_irq, qemu_irq ch1_irq, qemu_irq ch2_irq0, qemu_irq ch2_irq1) { int iomemtype; tmu012_state *s; int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0; s = (tmu012_state *)qemu_mallocz(sizeof(tmu012_state)); s->feat = feat; s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq); s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq); if (feat & TMU012_FEAT_3CHAN) s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT, ch2_irq0); /* ch2_irq1 not supported */ iomemtype = cpu_register_io_memory(0, tmu012_readfn, tmu012_writefn, s); cpu_register_physical_memory(P4ADDR(base), 0x00001000, iomemtype); cpu_register_physical_memory(A7ADDR(base), 0x00001000, iomemtype); /* ??? Save/restore. */ }
static int pl031_init(SysBusDevice *dev) { int iomemtype; pl031_state *s = FROM_SYSBUS(pl031_state, dev); struct tm tm; iomemtype = cpu_register_io_memory(pl031_readfn, pl031_writefn, s); if (iomemtype == -1) { hw_error("pl031_init: Can't register I/O memory\n"); } sysbus_init_mmio(dev, 0x1000, iomemtype); sysbus_init_irq(dev, &s->irq); /* ??? We assume vm_clock is zero at this point. */ qemu_get_timedate(&tm, 0); s->tick_offset = mktimegm(&tm); s->timer = qemu_new_timer(vm_clock, pl031_interrupt, s); return 0; }
static int syborg_keyboard_init(SysBusDevice *dev) { SyborgKeyboardState *s = FROM_SYSBUS(SyborgKeyboardState, dev); int iomemtype; sysbus_init_irq(dev, &s->irq); iomemtype = cpu_register_io_memory(syborg_keyboard_readfn, syborg_keyboard_writefn, s, DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, iomemtype); if (s->fifo_size <= 0) { fprintf(stderr, "syborg_keyboard: fifo too small\n"); s->fifo_size = 16; } s->key_fifo = qemu_mallocz(s->fifo_size * sizeof(s->key_fifo[0])); qemu_add_kbd_event_handler(syborg_keyboard_event, s); vmstate_register(&dev->qdev, -1, &vmstate_syborg_keyboard, s); return 0; }
ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base) { ppc4xx_mmio_t *mmio; int mmio_memory; mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t)); if (mmio != NULL) { mmio->base = base; mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio); #if defined(DEBUG_MMIO) printf("%s: base " PADDRX " len %08x %d\n", __func__, base, TARGET_PAGE_SIZE, mmio_memory); #endif cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory); ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE, unassigned_mmio_read, unassigned_mmio_write, mmio); } return mmio; }
PCIBus *pci_prep_init(qemu_irq *pic) { PREPPCIState *s; PCIDevice *d; int PPC_io_memory; s = qemu_mallocz(sizeof(PREPPCIState)); s->bus = pci_register_bus(prep_set_irq, prep_map_irq, pic, 0, 4); register_ioport_write(0xcf8, 4, 4, pci_prep_addr_writel, s); register_ioport_read(0xcf8, 4, 4, pci_prep_addr_readl, s); register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s); register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s); register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s); register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s); register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s); register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s); PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read, PPC_PCIIO_write, s); cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory); /* PCI host bridge */ d = pci_register_device(s->bus, "PREP Host Bridge - Motorola Raven", sizeof(PCIDevice), 0, NULL, NULL); d->config[0x00] = 0x57; // vendor_id : Motorola d->config[0x01] = 0x10; d->config[0x02] = 0x01; // device_id : Raven d->config[0x03] = 0x48; d->config[0x08] = 0x00; // revision d->config[0x0A] = 0x00; // class_sub = pci host d->config[0x0B] = 0x06; // class_base = PCI_bridge d->config[0x0C] = 0x08; // cache_line_size d->config[0x0D] = 0x10; // latency_timer d->config[0x0E] = 0x00; // header_type d->config[0x34] = 0x00; // capabilities_pointer return s->bus; }
TUSBState *tusb6010_init(qemu_irq intr) { TUSBState *s = qemu_mallocz(sizeof(*s)); s->test_reset = TUSB_PROD_TEST_RESET_VAL; s->host_mode = 0; s->dev_config = 0; s->otg_status = 0; /* !TUSB_DEV_OTG_STAT_ID_STATUS means host mode */ s->power = 0; s->mask = 0xffffffff; s->intr = 0x00000000; s->otg_timer_val = 0; s->iomemtype[1] = cpu_register_io_memory(tusb_async_readfn, tusb_async_writefn, s); s->irq = intr; s->otg_timer = qemu_new_timer(vm_clock, tusb_otg_tick, s); s->pwr_timer = qemu_new_timer(vm_clock, tusb_power_tick, s); s->musb = musb_init(qemu_allocate_irqs(tusb_musb_core_intr, s, __musb_irq_max)); return s; }
void etraxfs_ser_init(CPUState *env, qemu_irq *irq, CharDriverState *chr, target_phys_addr_t base) { struct etrax_serial_t *s; int ser_regs; s = qemu_mallocz(sizeof *s); s->env = env; s->irq = irq; s->chr = chr; /* transmitter begins ready and idle. */ s->rs_stat_din |= (1 << STAT_TR_RDY); s->rs_stat_din |= (1 << STAT_TR_IDLE); qemu_chr_add_handlers(chr, serial_can_receive, serial_receive, serial_event, s); ser_regs = cpu_register_io_memory(0, ser_read, ser_write, s); cpu_register_physical_memory (base, 0x3c, ser_regs); }
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, target_phys_addr_t base, ram_addr_t size, target_phys_addr_t mask) { KBDState *s = &kbd_state; int s_io_memory; s->irq_kbd = kbd_irq; s->irq_mouse = mouse_irq; s->mask = mask; vmstate_register(NULL, 0, &vmstate_kbd, s); s_io_memory = cpu_register_io_memory(kbd_mm_read, kbd_mm_write, s); cpu_register_physical_memory(base, size, s_io_memory); s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s); s->mouse = ps2_mouse_init(kbd_update_aux_irq, s); #ifdef TARGET_I386 vmmouse_init(s->mouse); #endif qemu_register_reset(kbd_reset, s); }