/* ------------------------------------------------------------------------*//**
* @FUNCTION cm54xx_export
* @BRIEF export module register content to file, in XML format.
* @RETURNS 0 in case of success
* OMAPCONF_ERR_CPU
* OMAPCONF_ERR_ARG
* OMAPCONF_ERR_INTERNAL
* @param[in,out] fp: output file stream (opened for write operations)
* @param[in] id: CM module ID
* @DESCRIPTION export module register content to file, in XML format.
*//*------------------------------------------------------------------------ */
int cm54xx_export(FILE *fp, cm54xx_mod_id id)
{
reg **mod;
unsigned int i;
CHECK_CPU(54xx, OMAPCONF_ERR_CPU);
CHECK_NULL_ARG(fp, OMAPCONF_ERR_ARG);
CHECK_ARG_LESS_THAN(id, CM54XX_MODS_COUNT, OMAPCONF_ERR_ARG);
if ((cpu_revision_get() != REV_ES1_0) &&
(id == CM54XX_L4PER_CM_CORE)) {
fprintf(stderr, "omapconf: %s(): L4_PER does not exist!!!\n",
__func__);
return OMAPCONF_ERR_ARG;
}
dprintf("%s(): exporting CM %s (%u) module ...\n", __func__,
cm54xx_mod_name_get(id), id);
if (cpu_revision_get() == REV_ES1_0)
mod = cm54xxes1_mods[id];
else
mod = cm54xx_mods[id];
if (mod == NULL) {
fprintf(stderr, "omapconf: %s(): mod == NULL!!!\n", __func__);
return OMAPCONF_ERR_INTERNAL;
}
if ((id == CM54XX_INSTR_CM_CORE) &&
!cm54xx_is_profiling_running(CM54XX_INSTR_CM_CORE)) {
dprintf(
"%s(%s): CM module is not accessible, don't export registers\n",
__func__, cm54xx_mod_name_get(id));
return 0;
} else if ((id == CM54XX_INSTR_CM_CORE_AON) &&
!cm54xx_is_profiling_running(CM54XX_INSTR_CM_CORE_AON)) {
dprintf(
"%s(%s): CM module is not accessible, don't export registers\n",
__func__, cm54xx_mod_name_get(id));
return 0;
}
fprintf(fp, " <submodule id=\"%u\" name=\"%s\">\n",
id, cm54xx_mod_name_get(id));
for (i = 0; mod[i] != NULL; i++)
fprintf(fp,
" <register id=\"%u\" name=\"%s\" addr=\"0x%08X\" data=\"0x%08X\" />\n",
i, reg_name_get(mod[i]), reg_addr_get(mod[i]),
reg_read(mod[i]));
fprintf(fp, " </submodule>\n");
fflush(fp);
dprintf("%s(): CM %s (%u) module exported.\n", __func__,
cm54xx_mod_name_get(id), id);
return 0;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION emif54xx_export
* @BRIEF export module register content to file, in XML format.
* @RETURNS 0 in case of success
* OMAPCONF_ERR_CPU
* OMAPCONF_ERR_ARG
* OMAPCONF_ERR_REG_ACCESS
* OMAPCONF_ERR_INTERNAL
* @param[in,out] fp: output file stream (opened for write operations)
* @param[in] id: EMIF module ID
* @DESCRIPTION export module register content to file, in XML format.
*//*------------------------------------------------------------------------ */
int emif54xx_export(FILE *fp, emif54xx_mod_id id)
{
reg **mod;
unsigned int i, accessible;
CHECK_CPU(54xx, OMAPCONF_ERR_CPU);
CHECK_NULL_ARG(fp, OMAPCONF_ERR_ARG);
CHECK_ARG_LESS_THAN(id, EMIF54XX_MODS_COUNT, OMAPCONF_ERR_ARG);
switch (id) {
case EMIF54XX_EMIF1:
accessible = module_is_accessible(MOD_EMIF1);
break;
case EMIF54XX_EMIF2:
accessible = module_is_accessible(MOD_EMIF2);
break;
default: /* should not happen as already checked just before ... */
return OMAPCONF_ERR_INTERNAL;
}
if (!accessible) {
printf("%s export: module not running, skipping "
"registers export.\n", emif54xx_mod_name_get(id));
return 0;
}
if (cpu_revision_get() == REV_ES1_0)
mod = emif54xxes1_mods[id];
else
mod = emif54xx_mods[id];
fprintf(fp, " <submodule id=\"%u\" name=\"%s\">\n",
id, emif54xx_mod_name_get(id));
if (cpu_revision_get() == REV_ES1_0) {
for (i = 0; i < OMAP5430ES1_EMIF1_MOD_REGCOUNT; i++)
fprintf(fp, " <register id=\"%u\" name=\"%s\" "
"addr=\"0x%08X\" data=\"0x%08X\" />\n", i,
(mod[i])->name, (mod[i])->addr, reg_read(mod[i]));
} else {
for (i = 0; i < OMAP5430_EMIF1_MOD_REGCOUNT; i++)
fprintf(fp, " <register id=\"%u\" name=\"%s\" "
"addr=\"0x%08X\" data=\"0x%08X\" />\n", i,
(mod[i])->name, (mod[i])->addr, reg_read(mod[i]));
}
fprintf(fp, " </submodule>\n");
return 0;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION prm54xx_import
* @BRIEF import OMAP PRM registers from XML file
* @RETURNS 0 in case of success
* OMAPCONF_ERR_ARG
* OMAPCONF_ERR_UNEXPECTED
* @param[in,out] fp: XML import file descriptor
* @param[in] id: CM module ID
* @DESCRIPTION import OMAP PRM registers from XML file,
* generated with lib54xx_export().
*//*------------------------------------------------------------------------ */
int prm54xx_import(FILE *fp, prm54xx_mod_id id)
{
reg **mod;
char line[256], sline[256];
char *xml_entry;
int ret, i, n;
CHECK_NULL_ARG(fp, OMAPCONF_ERR_ARG);
CHECK_ARG_LESS_THAN(id, PRM54XX_MODS_COUNT, OMAPCONF_ERR_ARG);
if (cpu_revision_get() == REV_ES1_0)
mod = prm54xxes1_mods[id];
else
mod = prm54xx_mods[id];
rewind(fp);
/* Search for the PRM module tag */
sprintf(sline, "<submodule id=\"%u\" name=\"%s\">",
id, prm54xx_mod_name_get(id));
while (fgets(line, sizeof(line), fp) != NULL) {
if (strstr(line, sline) == NULL)
continue;
/* Import register content */
for (i = 0; mod[i] != NULL; i++) {
if (fgets(line, sizeof(line), fp) == NULL)
return OMAPCONF_ERR_UNEXPECTED;
line[strlen(line) - 1] = '\0'; /* remove ending '\n' */
xml_entry = strstr(line, "<"); /* remove spaces */
dprintf("%s(%u (%s)): xml_entry=%s\n", __func__, id,
prm54xx_mod_name_get(id), xml_entry);
/* Check register id is correct */
ret = sscanf(xml_entry, "<register id=\"%u\" %s",
&n, sline);
if (ret != 2) {
dprintf("%s(%u (%s)): could not get id\n",
__func__, id, prm54xx_mod_name_get(id));
return OMAPCONF_ERR_UNEXPECTED;
}
if (n != i) {
dprintf(
"%s(%u (%s)): register id does not match! (n=%u, i=%u)\n",
__func__, id,
prm54xx_mod_name_get(id), n, i);
return OMAPCONF_ERR_UNEXPECTED;
}
ret = reg_xml_import(mod[i], xml_entry);
if (ret != 0)
return ret;
}
dprintf("%s(%u (%s)): all registers imported.\n", __func__, id,
prm54xx_mod_name_get(id));
break;
}
return 0;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION powerdm_emu_disable
* @BRIEF Power OFF EMU domain and clocks.
* @DESCRIPTION Power OFF EMU domain and clocks.
*//*------------------------------------------------------------------------ */
void powerdm_emu_disable(void)
{
if (cpu_is_omap44xx()) {
mem_write(OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, 0);
} else if (cpu_is_omap54xx()) {
if (cpu_revision_get() == REV_ES1_0)
mem_write(OMAP5430ES1_CM_L3INSTR_L3_MAIN_3_CLKCTRL,
0x0);
else
mem_write(OMAP5430_CM_L3INSTR_L3_MAIN_3_CLKCTRL, 0x0);
} else {
fprintf(stderr,
"omapconf: %s(): warning: cpu not supported, skipping it.\n",
__func__);
}
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION prm54xx_is_profiling_running
* @BRIEF return 1 if profiling module (PMI) is running,
* 0 otherwise
* @RETURNS 1 if profiling module (PMI) is running,
* 0 otherwise
* @DESCRIPTION return 1 if profiling module (PMI) is running,
* 0 otherwise
*//*------------------------------------------------------------------------ */
unsigned int prm54xx_is_profiling_running(void)
{
reg *cm_clkctrl_reg;
unsigned int cm_clkctrl;
if (cpu_revision_get() == REV_ES1_0)
cm_clkctrl_reg = &omap5430es1_cm_prm_profiling_clkctrl;
else
cm_clkctrl_reg = &omap5430_cm_prm_profiling_clkctrl;
if (cm_clkctrl_reg == NULL) {
dprintf("%s(): cm_clkctrl_reg == NULL!!!\n", __func__);
return 0;
}
cm_clkctrl = reg_read(cm_clkctrl_reg);
return mod_is_accessible(cm_clkctrl);
}
void nosleep_32k_disable(void)
{
unsigned int reg;
unsigned int reg_clk;
if (cpu_is_omap54xx()) {
if (cpu_revision_get() == REV_ES1_0)
reg_clk = OMAP5430ES1_CM_WKUPAON_CLKSTCTRL;
else
reg_clk = OMAP5430_CM_WKUPAON_CLKSTCTRL;
} else if (cpu_is_omap44xx()) {
reg_clk = OMAP4430_CM_WKUP_CLKSTCTRL;
}
mem_read(reg_clk, ®);
reg = reg | nosleep_32k_reg;
mem_write(reg_clk, reg);
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION cm54xx_is_profiling_running
* @BRIEF return 1 if profiling module (CMI) is running,
* 0 otherwise
* @RETURNS 1 if profiling module (CMI) is running, 0 otherwise
* @param[in] id: instrumentation ID
* (CM54XX_INSTR_CM_CORE or CM54XX_INSTR_CM_CORE_AON)
* @DESCRIPTION return 1 if profiling module (CMI) is running,
* 0 otherwise
*//*------------------------------------------------------------------------ */
unsigned int cm54xx_is_profiling_running(cm54xx_mod_id id)
{
reg *cm_clkctrl_reg;
unsigned int cm_clkctrl;
if (cpu_revision_get() == REV_ES1_0) {
if (id == CM54XX_INSTR_CM_CORE_AON) {
cm_clkctrl_reg =
&omap5430es1_cm_cm_core_aon_profiling_clkctrl;
} else if (id == CM54XX_INSTR_CM_CORE) {
cm_clkctrl_reg =
&omap5430es1_cm_cm_core_profiling_clkctrl;
} else {
fprintf(stderr,
"%s(): called with incorrect ID (%s)!!!\n",
__func__, cm54xx_mod_name_get(id));
return 0;
}
} else {
if (id == CM54XX_INSTR_CM_CORE_AON) {
cm_clkctrl_reg =
&omap5430_cm_cm_core_aon_profiling_clkctrl;
} else if (id == CM54XX_INSTR_CM_CORE) {
cm_clkctrl_reg =
&omap5430_cm_cm_core_profiling_clkctrl;
} else {
fprintf(stderr,
"%s(): called with incorrect ID (%s)!!!\n",
__func__, cm54xx_mod_name_get(id));
return 0;
}
}
if (cm_clkctrl_reg == NULL) {
fprintf(stderr, "omapconf: %s(): cm_clkctrl_reg == NULL!!!\n",
__func__);
return 0;
}
cm_clkctrl = reg_read(cm_clkctrl_reg);
return mod_is_accessible(cm_clkctrl);
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION ctrlmod54xx_export
* @BRIEF export CONTROL MODULE registers content to file, in
* XML format.
* @RETURNS 0 in case of success
* OMAPCONF_ERR_CPU
* OMAPCONF_ERR_ARG
* OMAPCONF_ERR_REG_ACCESS
* @param[in,out] fp: output file stream (opened for write operations)
* @param[in] id: module ID
* @DESCRIPTION export CONTROL MODULE registers content to file, in
* XML format.
*//*------------------------------------------------------------------------ */
int ctrlmod54xx_export(FILE *fp, ctrlmod54xx_mod_id id)
{
reg **mod;
unsigned int i;
CHECK_NULL_ARG(fp, OMAPCONF_ERR_ARG);
CHECK_ARG_LESS_THAN(id, CTRLMOD54XX_MODS_COUNT, OMAPCONF_ERR_ARG);
if (cpu_revision_get() == REV_ES1_0)
mod = ctrlmod54xxes1_mods[id];
else
mod = ctrlmod54xx_mods[id];
fprintf(fp, " <submodule id=\"%u\" name=\"%s\">\n",
id, ctrlmod54xx_mod_name_get(id));
for (i = 0; mod[i] != NULL; i++)
fprintf(fp, " <register id=\"%u\" name=\"%s\" "
"addr=\"0x%08X\" data=\"0x%08X\" />\n", i,
(mod[i])->name, (mod[i])->addr, reg_read(mod[i]));
fprintf(fp, " </submodule>\n");
return 0;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION opp54xx_init
* @BRIEF initialize internal data
* @DESCRIPTION initialize internal data (architecture dependent)
*//*------------------------------------------------------------------------ */
void opp54xx_init(void)
{
opp_t opp;
/* ES1.0 */
static const opp_t mpu_opp_low_es1 = {OPP_LOW, 950000, 400000};
static const opp_t mpu_opp_nom_es1 = {OPP_NOM, 1040000, 800000};
static const opp_t mpu_opp_high_es1 = {OPP_HIGH, 1220000, 1100000};
static const opp_t mm_opp_low_es1 = {OPP_LOW, 950000, 177333};
static const opp_t mm_opp_nom_es1 = {OPP_NOM, 1040000, 354667};
static const opp_t mm_opp_high_es1 = {OPP_HIGH, 1220000, 532000};
static const opp_t core_opp_low_es1 = {OPP_LOW, 950000, 133000};
static const opp_t core_opp_nom_es1 = {OPP_NOM, 1040000, 2660000};
/* ES2.0 */
static const opp_t mpu_opp_low = {OPP_LOW, 880000, 500000};
static const opp_t mpu_opp_nom = {OPP_NOM, 1060000, 1000000};
static const opp_t mpu_opp_high = {OPP_HIGH, 1250000, 1500000};
static const opp_t mpu_opp_sb = {OPP_SB, 1290000, 1700000};
static const opp_t mm_opp_low = {OPP_LOW, 880000, 195000};
static const opp_t mm_opp_nom = {OPP_NOM, 1030000, 389000};
static const opp_t mm_opp_high = {OPP_HIGH, 1120000, 532000};
static const opp_t core_opp_low = {OPP_LOW, 880000, 133000};
static const opp_t core_opp_nom = {OPP_NOM, 1040000, 2660000};
#ifdef OPP54XX_DEBUG
int i, count;
voltdm54xx_id vdd;
#endif
if (!opp54xx_init_done) {
genlist_init(&vdd54xx_wkup_opp_list);
opp.name = OPP_NOM;
opp.voltage = 1.0;
opp.rate = clk54xx_sysclk_rate_get();
genlist_addtail(&vdd54xx_wkup_opp_list,
(void *) &opp, sizeof(opp_t));
genlist_init(&vdd54xx_mpu_opp_list);
if (cpu_revision_get() == REV_ES1_0) {
genlist_addtail(&vdd54xx_mpu_opp_list,
(void *) &mpu_opp_low_es1, sizeof(opp_t));
genlist_addtail(&vdd54xx_mpu_opp_list,
(void *) &mpu_opp_nom_es1, sizeof(opp_t));
genlist_addtail(&vdd54xx_mpu_opp_list,
(void *) &mpu_opp_high_es1, sizeof(opp_t));
genlist_init(&vdd54xx_mm_opp_list);
genlist_addtail(&vdd54xx_mm_opp_list,
(void *) &mm_opp_low_es1, sizeof(opp_t));
genlist_addtail(&vdd54xx_mm_opp_list,
(void *) &mm_opp_nom_es1, sizeof(opp_t));
genlist_addtail(&vdd54xx_mm_opp_list,
(void *) &mm_opp_high_es1, sizeof(opp_t));
genlist_init(&vdd54xx_core_opp_list);
genlist_addtail(&vdd54xx_core_opp_list,
(void *) &core_opp_low_es1, sizeof(opp_t));
genlist_addtail(&vdd54xx_core_opp_list,
(void *) &core_opp_nom_es1, sizeof(opp_t));
} else {
genlist_addtail(&vdd54xx_mpu_opp_list,
(void *) &mpu_opp_low, sizeof(opp_t));
genlist_addtail(&vdd54xx_mpu_opp_list,
(void *) &mpu_opp_nom, sizeof(opp_t));
genlist_addtail(&vdd54xx_mpu_opp_list,
(void *) &mpu_opp_high, sizeof(opp_t));
genlist_addtail(&vdd54xx_mpu_opp_list,
(void *) &mpu_opp_sb, sizeof(opp_t));
genlist_init(&vdd54xx_mm_opp_list);
genlist_addtail(&vdd54xx_mm_opp_list,
(void *) &mm_opp_low, sizeof(opp_t));
genlist_addtail(&vdd54xx_mm_opp_list,
(void *) &mm_opp_nom, sizeof(opp_t));
genlist_addtail(&vdd54xx_mm_opp_list,
(void *) &mm_opp_high, sizeof(opp_t));
genlist_init(&vdd54xx_core_opp_list);
genlist_addtail(&vdd54xx_core_opp_list,
(void *) &core_opp_low, sizeof(opp_t));
genlist_addtail(&vdd54xx_core_opp_list,
(void *) &core_opp_nom, sizeof(opp_t));
}
opp54xx_init_done = 1;
#ifdef OPP54XX_DEBUG
printf("%s(): init done.\n", __func__);
printf("OPP List:\n");
for (vdd = VDD54XX_WKUP; vdd <= VDD54XX_CORE; vdd++) {
count = genlist_getcount(
(genlist *) opp54xx_list_table_es1[vdd]);
printf(" %s (%d): ", voltdm54xx_name_get(vdd), count);
for (i = 0; i < count; i++) {
genlist_get(
(genlist *) opp54xx_list_table_es1[vdd],
i, (void *) &opp);
printf("%s (%.1lfMHz, %.3lfV)",
opp.name, khz2mhz(opp.rate),
uv2v(opp.voltage));
if (i != count - 1)
printf(", ");
}
printf(".\n");
}
#endif
}
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION prm54xx_dump
* @BRIEF dump selected registers and pretty-print it in
* selected output stream
* @RETURNS 0 in case of success
* OMAPCONF_ERR_CPU
* OMAPCONF_ERR_ARG
* @param[in,out] stream: output stream
* @param[in] id: PRM module ID - If id == PRM54XX_MODS_COUNT,
* dump all PRM registers.
* @DESCRIPTION dump selected registers and pretty-print it in
* selected output stream
*//*------------------------------------------------------------------------ */
int prm54xx_dump(FILE *stream, prm54xx_mod_id id)
{
unsigned int i = 0, mid;
unsigned int val = 0;
int err = 0;
reg **mod;
reg *r;
char s[TABLE_MAX_ELT_LEN];
char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN];
unsigned int row;
if (stream == NULL) {
fprintf(stderr, "%s(): stream == NULL!!!\n", __func__);
err = OMAPCONF_ERR_ARG;
goto prm54xx_dump_end;
}
if (id > PRM54XX_MODS_COUNT) {
fprintf(stderr, "%s(): id (%u) > PRM54XX_MODS_COUNT!!! (%u)\n",
__func__, id, PRM54XX_MODS_COUNT);
err = OMAPCONF_ERR_ARG;
goto prm54xx_dump_end;
}
autoadjust_table_init(table);
row = 0;
if (id != PRM54XX_MODS_COUNT)
snprintf(table[row][0], TABLE_MAX_ELT_LEN, "%s Reg. Name",
prm54xx_mod_name_get(id));
else
strncpy(table[row][0], "PRM Reg. Name", TABLE_MAX_ELT_LEN);
strncpy(table[row][1], "Reg. Address",
TABLE_MAX_ELT_LEN);
strncpy(table[row][2], "Reg. Value", TABLE_MAX_ELT_LEN);
row++;
for (mid = PRM54XX_DSS_PRM; mid < PRM54XX_MODS_COUNT; mid++) {
if ((id != PRM54XX_MODS_COUNT) && (mid != id))
continue;
else {
if (cpu_revision_get() == REV_ES1_0)
mod = prm54xxes1_mods[mid];
else
mod = prm54xx_mods[mid];
for (i = 0; mod[i] != NULL; i++) {
r = mod[i];
/* Read register */
val = reg_read(r);
/* Show register name, addr & content */
snprintf(s, TABLE_MAX_ELT_LEN, "%s", r->name);
autoadjust_table_strncpy(table, row, 0, s);
snprintf(s, TABLE_MAX_ELT_LEN, "0x%08X",
r->addr);
autoadjust_table_strncpy(table, row, 1, s);
snprintf(s, TABLE_MAX_ELT_LEN, "0x%08X", val);
autoadjust_table_strncpy(table, row++, 2, s);
}
}
}
autoadjust_table_print(table, row, 3);
prm54xx_dump_end:
return err;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION mpu44xx_config_show
* @BRIEF analyze MPU power configuration
* @RETURNS 0 in case of success
* OMAPCONF_ERR_CPU
* OMAPCONF_ERR_REG_ACCESS
* @param[in] stream: output file stream
* @DESCRIPTION analyze MPU power configuration
*//*------------------------------------------------------------------------ */
int mpu44xx_config_show(FILE *stream)
{
unsigned int pm_pda_cpu0_pwrstctrl;
unsigned int pm_pda_cpu0_pwrstst;
unsigned int rm_pda_cpu0_context;
unsigned int cm_pda_cpu0_clkctrl;
unsigned int cm_pda_cpu0_clkstctrl;
unsigned int pm_pda_cpu1_pwrstctrl;
unsigned int pm_pda_cpu1_pwrstst;
unsigned int rm_pda_cpu1_context;
unsigned int cm_pda_cpu1_clkctrl;
unsigned int cm_pda_cpu1_clkstctrl;
unsigned int scu_cpu_power_status;
char s0[32], s1[32];
unsigned int cm_clkmode_dpll_mpu;
unsigned int cm_idlest_dpll_mpu;
unsigned int cm_autoidle_dpll_mpu;
omap4_dpll_params dpll_mpu_params;
unsigned int pm_pwstctrl;
unsigned int pm_pwstst;
unsigned int cm_clkstctrl;
unsigned int rm_context;
unsigned int cm_clkctrl;
int ret;
CHECK_CPU(44xx, OMAPCONF_ERR_CPU);
if (!init_done)
mpu44xx_regtable_init();
if (mem_read(OMAP4430_PM_PDA_CPU0_PWRSTCTRL,
&pm_pda_cpu0_pwrstctrl) != 0)
return OMAPCONF_ERR_REG_ACCESS;
if (mem_read(OMAP4430_PM_PDA_CPU0_PWRSTST, &pm_pda_cpu0_pwrstst) != 0)
return OMAPCONF_ERR_REG_ACCESS;
if (mem_read(OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT,
&rm_pda_cpu0_context) != 0)
return OMAPCONF_ERR_REG_ACCESS;
if (mem_read(OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL,
&cm_pda_cpu0_clkctrl) != 0)
return OMAPCONF_ERR_REG_ACCESS;
if (mem_read(OMAP4430_CM_PDA_CPU0_CLKSTCTRL,
&cm_pda_cpu0_clkstctrl) != 0)
return OMAPCONF_ERR_REG_ACCESS;
if (mem_read(OMAP4430_PM_PDA_CPU1_PWRSTCTRL,
&pm_pda_cpu1_pwrstctrl) != 0)
return OMAPCONF_ERR_REG_ACCESS;
if (mem_read(OMAP4430_PM_PDA_CPU1_PWRSTST,
&pm_pda_cpu1_pwrstst) != 0)
return OMAPCONF_ERR_REG_ACCESS;
if (mem_read(OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT,
&rm_pda_cpu1_context) != 0)
return OMAPCONF_ERR_REG_ACCESS;
if (mem_read(OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL,
&cm_pda_cpu1_clkctrl) != 0)
return OMAPCONF_ERR_REG_ACCESS;
if (mem_read(OMAP4430_CM_PDA_CPU1_CLKSTCTRL,
&cm_pda_cpu1_clkstctrl) != 0)
return OMAPCONF_ERR_REG_ACCESS;
if (mem_read(OMAP4430_SCU_CPU_POWER_STATUS,
&scu_cpu_power_status) != 0)
return OMAPCONF_ERR_REG_ACCESS;
if (mem_read(OMAP4430_CM_CLKMODE_DPLL_MPU,
&cm_clkmode_dpll_mpu) != 0)
return OMAPCONF_ERR_REG_ACCESS;
if (mem_read(OMAP4430_CM_IDLEST_DPLL_MPU,
&cm_idlest_dpll_mpu) != 0)
return OMAPCONF_ERR_REG_ACCESS;
if (mem_read(OMAP4430_CM_AUTOIDLE_DPLL_MPU,
&cm_autoidle_dpll_mpu) != 0)
return OMAPCONF_ERR_REG_ACCESS;
ret = dpll44xx_dpll_params_get(DPLL44XX_MPU,
&dpll_mpu_params, 0);
if (ret < 0)
return ret;
/* MPU LPRM config */
fprintf(stream, "|----------------------------------------------------"
"----|\n");
fprintf(stream, "| %-30s | %-9s | %-9s |\n", "MPU LPRM Configuration",
"CPU0", "CPU1");
fprintf(stream, "|--------------------------------|-----------|-------"
"----|\n");
pwrdm_state2string(s0,
(pwrdm_state) extract_bitfield(pm_pda_cpu0_pwrstst, 0, 2));
pwrdm_state2string(s1,
(pwrdm_state) extract_bitfield(pm_pda_cpu1_pwrstst, 0, 2));
fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Current Power State",
s0, s1);
fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Current Logic State",
((extract_bit(pm_pda_cpu0_pwrstst, 2) == 1) ? "ON" : "OFF"),
((extract_bit(pm_pda_cpu1_pwrstst, 2) == 1) ? "ON" : "OFF"));
pwrdm_state2string(s0,
(pwrdm_state) extract_bitfield(pm_pda_cpu0_pwrstst, 4, 2));
pwrdm_state2string(s1,
(pwrdm_state) extract_bitfield(pm_pda_cpu1_pwrstst, 4, 2));
fprintf(stream, "| %-30s | %-9s | %-9s |\n",
"Current L1$ State", s0, s1);
pwrdm_state2string(s0,
(pwrdm_state)extract_bitfield(pm_pda_cpu0_pwrstctrl, 0, 2));
pwrdm_state2string(s1,
(pwrdm_state) extract_bitfield(pm_pda_cpu1_pwrstctrl, 0, 2));
fprintf(stream, "| %-30s | %-9s | %-9s |\n",
"Standby Status",
((extract_bit(cm_pda_cpu0_clkctrl, 0) == 1) ?
"STANDBY" : "RUNNING"),
((extract_bit(cm_pda_cpu1_clkctrl, 0) == 1) ?
"STANDBY" : "RUNNING"));
fprintf(stream, "| %-30s | %-9s | %-9s |\n", "", "", "");
fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Target Power State",
s0, s1);
fprintf(stream, "| %-30s | %-9s | %-9s |\n",
"Logic State When Domain is RET",
((extract_bit(pm_pda_cpu0_pwrstctrl, 2) == 1) ? "RET" : "OFF"),
((extract_bit(pm_pda_cpu1_pwrstctrl, 2) == 1) ? "RET" : "OFF"));
fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Clock Control",
clkdm_ctrl_mode_name_get((clkdm_ctrl_mode)
extract_bitfield(cm_pda_cpu0_clkstctrl, 0, 2)),
clkdm_ctrl_mode_name_get((clkdm_ctrl_mode)
extract_bitfield(cm_pda_cpu1_clkstctrl, 0, 2)));
fprintf(stream, "| %-30s | %-9s | %-9s |\n", "", "", "");
if ((cpu_is_omap4430() && (cpu_revision_get() != REV_ES1_0)) ||
cpu_is_omap4460() || cpu_is_omap4470()) {
pwrdm_state2string(s0, (pwrdm_state)
extract_bitfield(pm_pda_cpu0_pwrstst, 24, 2));
pwrdm_state2string(s1, (pwrdm_state)
extract_bitfield(pm_pda_cpu1_pwrstst, 24, 2));
fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Last Power State",
s0, s1);
}
fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Last L1$ Context",
((extract_bit(rm_pda_cpu0_context, 8) == 1) ?
"LOST" : "RETAINED"),
((extract_bit(rm_pda_cpu1_context, 8) == 1) ?
"LOST" : "RETAINED"));
fprintf(stream, "| %-30s | %-9s | %-9s |\n", "Last CPU Context",
((extract_bit(rm_pda_cpu0_context, 0) == 1) ?
"LOST" : "RETAINED"),
((extract_bit(rm_pda_cpu1_context, 0) == 1) ?
"LOST" : "RETAINED"));
fprintf(stream, "|----------------------------------------------------"
"----|\n");
fprintf(stream, "\n");
/* SCU Configuration */
fprintf(stream, "|----------------------------------------------------"
"----|\n");
fprintf(stream, "| %-30s | %-9s | %-9s |\n",
"SCU Configuration", "CPU0", "CPU1");
fprintf(stream, "|--------------------------------|-----------|-------"
"----|\n");
OMAPCONF_SCU_CPU_POWER_STATUS_2_STRING(s0,
extract_bitfield(scu_cpu_power_status, 0, 2));
OMAPCONF_SCU_CPU_POWER_STATUS_2_STRING(s1,
extract_bitfield(scu_cpu_power_status, 8, 2));
fprintf(stream, "| %-30s | %-9s | %-9s |\n", "CPU Power Status",
s0, s1);
fprintf(stream, "|---------------------------------------------------"
"-----|\n");
fprintf(stream, "\n");
/* MPU Power Domain Configuration */
if (mem_read(OMAP4430_PM_MPU_PWRSTCTRL, &pm_pwstctrl) != 0)
return OMAPCONF_ERR_REG_ACCESS;
if (mem_read(OMAP4430_PM_MPU_PWRSTST, &pm_pwstst) != 0)
return OMAPCONF_ERR_REG_ACCESS;
ret = pwrdm44xx_config_show(stream, "MPU",
OMAP4430_PM_MPU_PWRSTCTRL, pm_pwstctrl,
OMAP4430_PM_MPU_PWRSTST, pm_pwstst);
if (ret != 0)
return ret;
/* MPU Clock Domain Configuration */
if (mem_read(OMAP4430_CM_MPU_CLKSTCTRL, &cm_clkstctrl) != 0)
return OMAPCONF_ERR_REG_ACCESS;
ret = clkdm44xx_config_show(stream, "MPU",
OMAP4430_CM_MPU_CLKSTCTRL, cm_clkstctrl);
if (ret != 0)
return ret;
/* MPU Module Power Configuration */
if (mem_read(OMAP4430_CM_MPU_MPU_CLKCTRL, &cm_clkctrl) != 0)
return OMAPCONF_ERR_REG_ACCESS;
if (mem_read(OMAP4430_RM_MPU_MPU_CONTEXT, &rm_context) != 0)
return OMAPCONF_ERR_REG_ACCESS;
ret = mod44xx_config_show(stream, "MPU",
OMAP4430_CM_MPU_MPU_CLKCTRL, cm_clkctrl,
OMAP4430_RM_MPU_MPU_CONTEXT, rm_context);
if (ret != 0)
return ret;
/* MPU DPLL Configuration */
fprintf(stream, "|----------------------------------------------------"
"----|\n");
fprintf(stream, "| MPU DPLL Configuration "
" |\n");
fprintf(stream, "|--------------------------------|-------------------"
"----|\n");
fprintf(stream, "| %-30s | %-21s |\n", "Status",
dpll_status_name_get((dpll_status) dpll_mpu_params.status));
sprintf(s0, "%d", (unsigned int) dpll_mpu_params.M2_speed);
fprintf(stream, "| %-30s | %-21s |\n", "Clock Speed (MHz)", s0);
fprintf(stream, "| %-30s | %-21s |\n", "Mode",
dpll_mode_name_get((dpll_mode) dpll_mpu_params.mode));
fprintf(stream, "| %-30s | %-21s |\n", "Low-Power Mode",
(dpll_mpu_params.lpmode == 1) ? "Enabled" : "Disabled");
fprintf(stream, "| %-30s | %-21s |\n", "Autoidle Mode",
dpll_autoidle_mode_name_get((dpll_autoidle_mode)
dpll_mpu_params.autoidle_mode));
fprintf(stream, "| %-30s | %-21s |\n", "M2 Output Autogating",
(dpll_mpu_params.M2_autogating == 1) ? "Enabled" : "Disabled");
fprintf(stream, "|----------------------------------------------------"
"----|\n");
fprintf(stream, "\nNB: type \"omapconf dplls cfg\" "
"for detailed DPLL configuration.\n\n");
return 0;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION mpu44xx_regtable_init
* @BRIEF initialize reg_table fields (not possible statically)
* @RETURNS 0 in case of success
* OMAPCONF_ERR_CPU
* @DESCRIPTION initialize reg_table fields (not possible statically)
*//*------------------------------------------------------------------------ */
int mpu44xx_regtable_init(void)
{
int i = 0;
CHECK_CPU(44xx, OMAPCONF_ERR_CPU);
/* Init PRCM MPU registers table */
strcpy(prcm_mpu_reg_table[i].name, "PM_PDA_CPU0_PWRSTCTRL");
prcm_mpu_reg_table[i++].addr = OMAP4430_PM_PDA_CPU0_PWRSTCTRL;
strcpy(prcm_mpu_reg_table[i].name, "PM_PDA_CPU0_PWRSTST");
prcm_mpu_reg_table[i++].addr = OMAP4430_PM_PDA_CPU0_PWRSTST;
strcpy(prcm_mpu_reg_table[i].name, "RM_PDA_CPU0_CONTEXT");
prcm_mpu_reg_table[i++].addr = OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT;
strcpy(prcm_mpu_reg_table[i].name, "RM_PDA_CPU0_RSTCTRL");
prcm_mpu_reg_table[i++].addr = OMAP4430_RM_PDA_CPU0_CPU0_RSTCTRL;
strcpy(prcm_mpu_reg_table[i].name, "CM_PDA_CPU0_CLKCTRL");
prcm_mpu_reg_table[i++].addr = OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL;
strcpy(prcm_mpu_reg_table[i].name, "CM_PDA_CPU0_CLKSTCTRL");
prcm_mpu_reg_table[i++].addr = OMAP4430_CM_PDA_CPU0_CLKSTCTRL;
strcpy(prcm_mpu_reg_table[i].name, "PM_PDA_CPU1_PWRSTCTRL");
prcm_mpu_reg_table[i++].addr = OMAP4430_PM_PDA_CPU1_PWRSTCTRL;
strcpy(prcm_mpu_reg_table[i].name, "PM_PDA_CPU1_PWRSTST");
prcm_mpu_reg_table[i++].addr = OMAP4430_PM_PDA_CPU1_PWRSTST;
strcpy(prcm_mpu_reg_table[i].name, "RM_PDA_CPU1_CONTEXT");
prcm_mpu_reg_table[i++].addr = OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT;
strcpy(prcm_mpu_reg_table[i].name, "RM_PDA_CPU1_RSTCTRL");
prcm_mpu_reg_table[i++].addr = OMAP4430_RM_PDA_CPU1_CPU1_RSTCTRL;
strcpy(prcm_mpu_reg_table[i].name, "CM_PDA_CPU1_CLKCTRL");
prcm_mpu_reg_table[i++].addr = OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL;
strcpy(prcm_mpu_reg_table[i].name, "CM_PDA_CPU1_CLKSTCTRL");
prcm_mpu_reg_table[i++].addr = OMAP4430_CM_PDA_CPU1_CLKSTCTRL;
strcpy(prcm_mpu_reg_table[i].name, "PM_MPU_PWRSTCTRL");
prcm_mpu_reg_table[i++].addr = OMAP4430_PM_MPU_PWRSTCTRL;
strcpy(prcm_mpu_reg_table[i].name, "PM_MPU_PWRSTST");
prcm_mpu_reg_table[i++].addr = OMAP4430_PM_MPU_PWRSTST;
strcpy(prcm_mpu_reg_table[i].name, "RM_MPU_MPU_CONTEXT");
prcm_mpu_reg_table[i++].addr = OMAP4430_RM_MPU_MPU_CONTEXT;
strcpy(prcm_mpu_reg_table[i].name, "CM_MPU_CLKSTCTRL");
prcm_mpu_reg_table[i++].addr = OMAP4430_CM_MPU_CLKSTCTRL;
strcpy(prcm_mpu_reg_table[i].name, "CM_MPU_MPU_CLKCTRL");
prcm_mpu_reg_table[i++].addr = OMAP4430_CM_MPU_MPU_CLKCTRL;
strcpy(prcm_mpu_reg_table[i].name, "CM_MPU_STATICDEP");
prcm_mpu_reg_table[i++].addr = OMAP4430_CM_MPU_STATICDEP;
strcpy(prcm_mpu_reg_table[i].name, "CM_MPU_DYNAMICDEP");
prcm_mpu_reg_table[i++].addr = OMAP4430_CM_MPU_DYNAMICDEP;
strcpy(prcm_mpu_reg_table[i].name, "SCU_CPU_POWER_STATUS");
prcm_mpu_reg_table[i++].addr = OMAP4430_SCU_CPU_POWER_STATUS;
strcpy(prcm_mpu_reg_table[i].name, "CM_CLKMODE_DPLL_MPU");
prcm_mpu_reg_table[i++].addr = OMAP4430_CM_CLKMODE_DPLL_MPU;
strcpy(prcm_mpu_reg_table[i].name, "CM_IDLEST_DPLL_MPU");
prcm_mpu_reg_table[i++].addr = OMAP4430_CM_IDLEST_DPLL_MPU;
strcpy(prcm_mpu_reg_table[i].name, "CM_AUTOIDLE_DPLL_MPU");
prcm_mpu_reg_table[i++].addr = OMAP4430_CM_AUTOIDLE_DPLL_MPU;
strcpy(prcm_mpu_reg_table[i].name, "PRM_IRQSTATUS_MPU_A9");
prcm_mpu_reg_table[i++].addr = OMAP4430_PRM_IRQSTATUS_MPU;
strcpy(prcm_mpu_reg_table[i].name, "PRM_IRQSTATUS_MPU_A9_2");
prcm_mpu_reg_table[i++].addr = OMAP4430_PRM_IRQSTATUS_MPU_2;
strcpy(prcm_mpu_reg_table[i].name, "PRM_IRQENABLE_MPU_A9");
prcm_mpu_reg_table[i++].addr = OMAP4430_PRM_IRQENABLE_MPU;
strcpy(prcm_mpu_reg_table[i].name, "PRM_IRQENABLE_MPU_A9_2");
prcm_mpu_reg_table[i++].addr = OMAP4430_PRM_IRQENABLE_MPU_2;
strcpy(prcm_mpu_reg_table[i].name, "END");
prcm_mpu_reg_table[i].addr = 0;
/* ES2.0 updates */
if ((cpu_is_omap4430() && (cpu_revision_get() != REV_ES1_0))
|| cpu_is_omap4460() || cpu_is_omap4470()) {
strcpy(omap44xx_prm_irq_names[22], "VC_CORE_VPACK");
strcpy(omap44xx_prm_irq_names[7], "RESERVED");
strcpy(omap44xx_prm_irq_names[5], "RESERVED");
}
init_done = 1;
return 0;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION lib54xx_export
* @BRIEF export OMAP registers in XML format into file
* @RETURNS 0 in case of success
* OMAPCONF_ERR_ARG otherwise
* @param[in] file: export file name (default if == NULL)
* @DESCRIPTION export OMAP registers in XML format into file. If no
* file name provided, generate one using current date.
*//*------------------------------------------------------------------------ */
int lib54xx_export(char *file)
{
FILE *fp = NULL;
char default_file[64];
char export_date[32];
char version[RELEASE_VERSION_MAX_LENGTH];
char type[RELEASE_TYPE_MAX_LENGTH];
char date[RELEASE_DATE_MAX_LENGTH];
char kversion[KERNEL_VERSION_MAX_LENGTH];
char kauthor[KERNEL_AUTHOR_MAX_LENGTH];
char ktoolchain[KERNEL_TOOLCHAIN_MAX_LENGTH];
char ktype[KERNEL_TYPE_MAX_LENGTH];
char kdate[KERNEL_DATE_MAX_LENGTH];
char dev_name[CPU_NAME_MAX_LENGTH];
char dev_rev[CPU_REVISION_MAX_NAME_LENGTH];
char dev_type[CPU_DEVICE_TYPE_MAX_NAME_LENGTH];
char dev_si_type[CPU_SI_TYPE_MAX_NAME_LENGTH];
unsigned int dev_max_speed;
unsigned int i;
time_t t;
struct tm *tmp;
CHECK_CPU(54xx, OMAPCONF_ERR_CPU);
/* Get date */
t = time(NULL);
tmp = localtime(&t);
/* Open export file */
if (file == NULL) {
/* No file name given, generate default one */
strcpy(default_file,
"omapconf_export_Mon_Jan_01_00_00_00_CET_1970.xml");
if (tmp != NULL)
strftime(default_file, 64,
"omapconf_export_%a_%b_%d_%H_%M_%S_%Z_%Y.xml",
tmp);
fp = fopen(default_file, "w");
} else {
fp = fopen(file, "w");
}
if (fp == NULL) {
printf("Oups... could not create %s!!!\n\n", file);
return 0;
}
/* XML header */
fprintf(fp, "<?xml version=\"1.0\"?>\n\n");
strcpy(export_date, "Mon Jan 01 00:00:00 CET 1970");
if (tmp != NULL)
strftime(export_date, sizeof(export_date),
"%a %b %d %H:%M:%S %Z %Y", tmp);
fprintf(fp,
"<omapconf_export export_date=\"%s\" omapconf_version=\"%u.%u\" omapconf_builddate=\"%s\">\n",
export_date, OMAPCONF_REV_MAJOR, OMAPCONF_REV_MINOR, builddate);
release_details_get(version, type, date);
if (os_is_android())
fprintf(fp,
" <buildinfo os=\"android\" version=\"%s\" type=\"%s\" date=\"%s\">\n",
version, type, date);
else
fprintf(fp, " <buildinfo os=\"linux\" version=\"%s\">\n",
version);
kernel_details_get(kversion, kauthor, ktoolchain, ktype, kdate);
fprintf(fp,
" <kernel version=\"%s\" author=\"%s\" toolchain=\"%s\" type=\"%s\" date=\"%s\">\n",
kversion, kauthor, ktoolchain, ktype, kdate);
cpu_gets(dev_name);
cpu_revision_gets(dev_rev);
cpu_device_type_gets(dev_type);
cpu_silicon_type_gets(dev_si_type);
dev_max_speed = cpu_silicon_max_speed_get();
fprintf(fp,
" <device name=\"%s\" revision=\"%s\" type=\"%s\" silicon_type=\"%s\" max_speed_mhz=\"%u\">\n",
dev_name, dev_rev, dev_type, dev_si_type, dev_max_speed);
/* Export PRM registers */
fprintf(fp, " <module name=\"PRM\">\n");
for (i = 0; i < PRM54XX_MODS_COUNT; i++) {
if ((cpu_revision_get() != REV_ES1_0) &&
(i == PRM54XX_L4PER_PRM))
/* L4_PER does not exist on ES2.x */
continue;
prm54xx_export(fp, (prm54xx_mod_id) i);
}
fprintf(fp, " </module>\n");
/* Export CM registers */
fprintf(fp, " <module name=\"CM\">\n");
for (i = 0; i < CM54XX_MODS_COUNT; i++) {
if ((cpu_revision_get() != REV_ES1_0) &&
(i == CM54XX_L4PER_CM_CORE))
/* Does not exist on ES2.x */
continue;
cm54xx_export(fp, (cm54xx_mod_id) i);
}
fprintf(fp, " </module>\n");
/* Export Smart-Reflex registers */
fprintf(fp, " <module name=\"SR\">\n");
sr54xx_export(fp, SR54XX_SMARTREFLEX_MPU);
sr54xx_export(fp, SR54XX_SMARTREFLEX_MM);
sr54xx_export(fp, SR54XX_SMARTREFLEX_CORE);
fprintf(fp, " </module>\n");
/* Export CONTROL MODULE registers */
fprintf(fp, " <module name=\"CONTROL MODULE\">\n");
ctrlmod54xx_export(fp, CTRLMOD54XX_CTRL_MODULE_CORE);
ctrlmod54xx_export(fp, CTRLMOD54XX_CTRL_MODULE_CORE_PAD);
ctrlmod54xx_export(fp, CTRLMOD54XX_CTRL_MODULE_WKUP);
ctrlmod54xx_export(fp, CTRLMOD54XX_CTRL_MODULE_WKUP_PAD);
fprintf(fp, " </module>\n");
/* Export EMIF registers */
fprintf(fp, " <module name=\"EMIF\">\n");
emif54xx_export(fp, EMIF54XX_EMIF1);
emif54xx_export(fp, EMIF54XX_EMIF2);
fprintf(fp, " </module>\n");
fprintf(fp, " </device>\n");
fprintf(fp, " </kernel>\n");
fprintf(fp, " </build>\n");
fprintf(fp, "</omapconf_export>");
/* Close file */
if (fp != NULL)
fclose(fp);
if (file == NULL)
printf("Registers successfully exported in \"%s\" file.\n\n",
default_file);
else
printf("Registers successfully exported in \"%s\" file.\n\n",
file);
return 0;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION pwrdm44xx_config_show
* @BRIEF analyze power domain configuration
* @RETURNS 0 in case of error
* @param[in,out] stream: output file
* @param[in,out] name: domain name
* @param[in] pm_pwstctrl_addr: PM_xyz_PWSTCTRL register address
* @param[in] pm_pwstctrl: PM_xyz_PWSTCTRL register content
* @param[in] pm_pwstst_addr: PM_xyz_PWSTST register address
* @param[in] pm_pwstst: PM_xyz_PWSTST register content
* @DESCRIPTION analyze power domain configuration
*//*------------------------------------------------------------------------ */
int pwrdm44xx_config_show(FILE *stream, const char name[11],
unsigned int pm_pwstctrl_addr, unsigned int pm_pwstctrl,
unsigned int pm_pwstst_addr, unsigned int pm_pwstst)
{
char curr[32], tgt[32], last[32];
dprintf("%s(): name=%s\n", __func__, name);
dprintf("%s(): pm_pwstctrl addr=0x%08X\n", __func__, pm_pwstctrl_addr);
dprintf("%s(): pm_pwstctrl=0x%08X\n", __func__, pm_pwstctrl);
dprintf("%s(): pm_pwstst addr=0x%08X\n", __func__, pm_pwstst_addr);
dprintf("%s(): pm_pwstst=0x%08X\n", __func__, pm_pwstst);
dprintf("\n");
fprintf(stream, "|---------------------------------------------------"
"-----------|\n");
fprintf(stream, "| %-10s Power Domain Configuration "
" |\n", name);
fprintf(stream, "|---------------------------------------------------"
"-----------|\n");
fprintf(stream, "| %-30s | %-7s | %-7s | %-7s |\n", "Power State",
"Current", "Target", "Last");
fprintf(stream, "|--------------------------------|---------|--------"
"-|---------|\n");
pwrdm_state2string(curr,
(pwrdm_state) extract_bitfield(pm_pwstst, 0, 2));
pwrdm_state2string(tgt,
(pwrdm_state) extract_bitfield(pm_pwstctrl, 0, 2));
if ((cpu_is_omap4430() && (cpu_revision_get() != REV_ES1_0)) ||
cpu_is_omap4460() || cpu_is_omap4470()) {
switch (pm_pwstst_addr) {
case OMAP4430_PM_MPU_PWRSTST:
case OMAP4430_PM_DSP_PWRSTST:
case OMAP4430_PM_ABE_PWRSTST:
case OMAP4430_PM_CORE_PWRSTST:
case OMAP4430_PM_IVAHD_PWRSTST:
case OMAP4430_PM_L3INIT_PWRSTST:
case OMAP4430_PM_L4PER_PWRSTST:
pwrdm_state2string(last, (pwrdm_state)
extract_bitfield(pm_pwstst, 24, 2));
break;
case OMAP4430_PM_CAM_PWRSTST:
case OMAP4430_PM_DSS_PWRSTST:
case OMAP4430_PM_GFX_PWRSTST:
case OMAP4430_PM_EMU_PWRSTST:
if (!cpu_is_omap4430())
pwrdm_state2string(last, (pwrdm_state)
extract_bitfield(pm_pwstst, 24, 2));
else
strcpy(last, "");
break;
default:
strcpy(last, "");
}
} else {
strcpy(last, "");
}
fprintf(stream, "| %-30s | %-7s | %-7s | %-7s |\n",
"Domain", curr, tgt, last);
if ((pm_pwstctrl_addr == OMAP4430_PM_CAM_PWRSTCTRL) ||
(pm_pwstctrl_addr == OMAP4430_PM_EMU_PWRSTCTRL) ||
(pm_pwstctrl_addr == OMAP4430_PM_GFX_PWRSTCTRL)) {
fprintf(stream, "| %-30s | %-7s | %-7s | |\n", "Logic",
((extract_bit(pm_pwstst, 2) == 1) ? "ON" : "OFF"),
"");
} else {
fprintf(stream, "| %-30s | %-7s | %-7s | |\n", "Logic",
((extract_bit(pm_pwstst, 2) == 1) ? "ON" : "OFF"),
((extract_bit(pm_pwstctrl, 2) == 1) ? "RET" : "OFF"));
}
fprintf(stream, "| %-30s | %-7s | %-7s | |\n",
"Memory", "", "");
switch (pm_pwstctrl_addr) {
case OMAP4430_PM_CORE_PWRSTCTRL:
pwrdm_state2string(curr, (pwrdm_state)
extract_bitfield(pm_pwstst, 12, 2));
pwrdm_state2string(tgt, (pwrdm_state)
extract_bit(pm_pwstctrl, 12));
fprintf(stream, "| %-30s | %-7s | %-7s | |\n",
" OCP_WP Bank & DMM Bank2", curr, tgt);
break;
default:
break;
}
switch (pm_pwstctrl_addr) {
case OMAP4430_PM_IVAHD_PWRSTCTRL:
pwrdm_state2string(curr, (pwrdm_state)
extract_bitfield(pm_pwstst, 10, 2));
pwrdm_state2string(tgt, (pwrdm_state)
extract_bit(pm_pwstctrl, 11));
fprintf(stream, "| %-30s | %-7s | %-7s | |\n",
" TCM2", curr, tgt);
break;
case OMAP4430_PM_CORE_PWRSTCTRL:
pwrdm_state2string(curr, (pwrdm_state)
extract_bitfield(pm_pwstst, 10, 2));
pwrdm_state2string(tgt, (pwrdm_state)
extract_bit(pm_pwstctrl, 11));
fprintf(stream, "| %-30s | %-7s | %-7s | |\n",
" MPU_M3 Unicache", curr, tgt);
default:
break;
}
switch (pm_pwstctrl_addr) {
case OMAP4430_PM_MPU_PWRSTCTRL:
pwrdm_state2string(curr, (pwrdm_state)
extract_bitfield(pm_pwstst, 8, 2));
pwrdm_state2string(tgt, (pwrdm_state)
extract_bit(pm_pwstctrl, 10));
fprintf(stream, "| %-30s | %-7s | %-7s | |\n",
" RAM", curr, tgt);
break;
case OMAP4430_PM_DSP_PWRSTCTRL:
pwrdm_state2string(curr, (pwrdm_state)
extract_bitfield(pm_pwstst, 8, 2));
pwrdm_state2string(tgt, (pwrdm_state)
extract_bit(pm_pwstctrl, 10));
fprintf(stream, "| %-30s | %-7s | %-7s | |\n",
" EDMA", curr, tgt);
break;
case OMAP4430_PM_DSS_PWRSTCTRL:
case OMAP4430_PM_CAM_PWRSTCTRL:
case OMAP4430_PM_GFX_PWRSTCTRL:
pwrdm_state2string(curr, (pwrdm_state)
extract_bitfield(pm_pwstst, 4, 2));
pwrdm_state2string(tgt, (pwrdm_state)
extract_bit(pm_pwstctrl, 8));
fprintf(stream, "| %-30s | %-7s | %-7s | |\n",
" MEM", curr, tgt);
break;
case OMAP4430_PM_IVAHD_PWRSTCTRL:
pwrdm_state2string(curr, (pwrdm_state)
extract_bitfield(pm_pwstst, 8, 2));
pwrdm_state2string(tgt, (pwrdm_state)
extract_bit(pm_pwstctrl, 10));
fprintf(stream, "| %-30s | %-7s | %-7s | |\n",
" TCM1", curr, tgt);
case OMAP4430_PM_CORE_PWRSTCTRL:
pwrdm_state2string(curr, (pwrdm_state)
extract_bitfield(pm_pwstst, 8, 2));
pwrdm_state2string(tgt, (pwrdm_state)
extract_bit(pm_pwstctrl, 10));
fprintf(stream, "| %-30s | %-7s | %-7s | |\n",
" MPU_M3 L2 RAM", curr, tgt);
default:
break;
}
switch (pm_pwstctrl_addr) {
case OMAP4430_PM_ABE_PWRSTCTRL:
pwrdm_state2string(curr, (pwrdm_state)
extract_bitfield(pm_pwstst, 8, 2));
pwrdm_state2string(tgt, (pwrdm_state)
extract_bit(pm_pwstctrl, 10));
fprintf(stream, "| %-30s | %-7s | %-7s | |\n",
" PERIPHMEM", curr, tgt);
pwrdm_state2string(curr, (pwrdm_state)
extract_bitfield(pm_pwstst, 4, 2));
pwrdm_state2string(tgt, (pwrdm_state)
extract_bit(pm_pwstctrl, 8));
fprintf(stream, "| %-30s | %-7s | %-7s | |\n",
" AESSMEM", curr, tgt);
break;
case OMAP4430_PM_MPU_PWRSTCTRL:
pwrdm_state2string(curr, (pwrdm_state)
extract_bitfield(pm_pwstst, 6, 2));
pwrdm_state2string(tgt, (pwrdm_state)
extract_bit(pm_pwstctrl, 9));
fprintf(stream, "| %-30s | %-7s | %-7s | |\n",
" L2$", curr, tgt);
if (cpu_is_omap4430())
pwrdm_state2string(curr,
extract_bitfield(pm_pwstst, 4, 2));
else
strcpy(curr, ""); /* not available on OMAP44[60-70] */
pwrdm_state2string(tgt,
extract_bit(pm_pwstctrl, 8));
fprintf(stream, "| %-30s | %-7s | %-7s | |\n",
" L1$", curr, tgt);
break;
case OMAP4430_PM_DSP_PWRSTCTRL:
pwrdm_state2string(curr, (pwrdm_state)
extract_bitfield(pm_pwstst, 6, 2));
pwrdm_state2string(tgt, (pwrdm_state)
extract_bit(pm_pwstctrl, 9));
fprintf(stream, "| %-30s | %-7s | %-7s | |\n",
" L2$", curr, tgt);
pwrdm_state2string(curr,
extract_bitfield(pm_pwstst, 4, 2));
pwrdm_state2string(tgt,
extract_bit(pm_pwstctrl, 8));
fprintf(stream, "| %-30s | %-7s | %-7s | |\n",
" L1$", curr, tgt);
break;
case OMAP4430_PM_IVAHD_PWRSTCTRL:
pwrdm_state2string(curr, (pwrdm_state)
extract_bitfield(pm_pwstst, 6, 2));
pwrdm_state2string(tgt, (pwrdm_state)
extract_bit(pm_pwstctrl, 9));
fprintf(stream, "| %-30s | %-7s | %-7s | |\n",
" SL2", curr, tgt);
pwrdm_state2string(curr, (pwrdm_state)
extract_bitfield(pm_pwstst, 4, 2));
pwrdm_state2string(tgt, (pwrdm_state)
extract_bit(pm_pwstctrl, 8));
fprintf(stream, "| %-30s | %-7s | %-7s | |\n",
" HWA", curr, tgt);
break;
case OMAP4430_PM_L4PER_PWRSTCTRL:
pwrdm_state2string(curr, (pwrdm_state)
extract_bitfield(pm_pwstst, 6, 2));
pwrdm_state2string(tgt, (pwrdm_state)
extract_bit(pm_pwstctrl, 9));
fprintf(stream, "| %-30s | %-7s | %-7s | |\n",
" NONRETAINED", curr, tgt);
pwrdm_state2string(curr, (pwrdm_state)
extract_bitfield(pm_pwstst, 4, 2));
pwrdm_state2string(tgt, (pwrdm_state)
extract_bit(pm_pwstctrl, 8));
fprintf(stream, "| %-30s | %-7s | %-7s | |\n",
" RETAINED", curr, tgt);
break;
case OMAP4430_PM_CORE_PWRSTCTRL:
pwrdm_state2string(curr, (pwrdm_state)
extract_bitfield(pm_pwstst, 6, 2));
pwrdm_state2string(tgt, (pwrdm_state)
extract_bit(pm_pwstctrl, 9));
fprintf(stream, "| %-30s | %-7s | %-7s | |\n",
" OCM RAM", curr, tgt);
pwrdm_state2string(curr, (pwrdm_state)
extract_bitfield(pm_pwstst, 4, 2));
pwrdm_state2string(tgt, (pwrdm_state)
extract_bit(pm_pwstctrl, 8));
fprintf(stream, "| %-30s | %-7s | %-7s | |\n",
" DMA/ICR Bank & DMM Bank1", curr, tgt);
break;
case OMAP4430_PM_L3INIT_PWRSTCTRL:
pwrdm_state2string(curr, (pwrdm_state)
extract_bitfield(pm_pwstst, 4, 2));
pwrdm_state2string(tgt, (pwrdm_state)
extract_bit(pm_pwstctrl, 8));
fprintf(stream, "| %-30s | %-7s | %-7s | |\n",
" L3INIT Bank1", curr, tgt);
break;
case OMAP4430_PM_EMU_PWRSTCTRL:
pwrdm_state2string(curr, (pwrdm_state)
extract_bitfield(pm_pwstst, 4, 2));
pwrdm_state2string(tgt, (pwrdm_state)
extract_bitfield(pm_pwstctrl, 16, 2));
fprintf(stream, "| %-30s | %-7s | %-7s | |\n",
" EMU Bank", curr, tgt);
break;
default:
break;
}
fprintf(stream, "|---------------------------------------------------"
"-----------|\n");
fprintf(stream, "| %-30s | %-27s |\n", "Ongoing Power Transition?",
((extract_bit(pm_pwstst, 20) == 1) ? "YES" : "NO"));
fprintf(stream, "|---------------------------------------------------"
"-----------|\n");
fprintf(stream, "\n");
return 0;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION cpu_detect
* @BRIEF Detect cpu and set internal global variables accordingly
* @RETURNS 0 on success
* OMAPCONF_ERR_UNEXPECTED
* OMAPCONF_ERR_CPU if cpu not recognized
* OMAPCONF_ERR_REG_ACCESS
* @param[in] none
* @DESCRIPTION Detect cpu and set internal global variables accordingly
*//*------------------------------------------------------------------------ */
int cpu_detect(void)
{
unsigned int status;
unsigned int efuse;
unsigned int prod_id_1;
int ret;
unsigned char status_bit_start;
#ifdef CPUID_DEBUG
char s[CPU_FULL_NAME_MAX_LENGTH];
char rev_s[CPU_REVISION_MAX_NAME_LENGTH];
char dev_type_s[CPU_DEVICE_TYPE_MAX_NAME_LENGTH];
#endif
/* Init variables */
cpu_init();
/* Retrieve OMAP chip & ES */
/* Determine if device is of the AM or OMAP family */
if (cpu_is_omap())
ret = identify_omap();
else
ret = identify_sitara();
if (ret)
return ret;
dprintf("%s(): Chip is %s ES%s\n", __func__,
cpu_gets(s), cpu_revision_gets(rev_s));
/* Retrieve device type */
if (cpu_is_omap44xx()) {
ret = mem_read(OMAP44XX_STATUS, &status);
status_bit_start = 8;
} else if (cpu_is_omap54xx() || cpu_is_dra7xx()) {
ret = mem_read(OMAP54XX_STATUS, &status);
status_bit_start = 6;
} else if (cpu_is_am335x() || cpu_is_am437x()) {
ret = mem_read(AM335X_STATUS, &status);
status_bit_start = 8;
} else {
ret = -1;
}
if (ret)
return OMAPCONF_ERR_REG_ACCESS;
dprintf("%s(): OMAP44XX_STATUS = 0x%08X\n", __func__, status);
switch (extract_bitfield(status, status_bit_start, 2)) {
case 3:
cpu_device_type_set(DEV_GP);
break;
case 2:
cpu_device_type_set(DEV_HS);
break;
case 1:
cpu_device_type_set(DEV_EMU);
break;
default:
cpu_device_type_set(DEV_TEST);
}
dprintf("%s(): Device Type is %s\n", __func__,
cpu_device_type_gets(dev_type_s));
/* Retrieve silicon performance type from EFuse */
if (cpu_is_omap44xx()) {
if (mem_read(CONTROL_STD_FUSE_PROD_ID_1, &prod_id_1) != 0) {
fprintf(stderr,
"omapconf (%s()): could not read CONTROL_STD_FUSE_PROD_ID_1 register!\n",
__func__);
return OMAPCONF_ERR_REG_ACCESS;
}
dprintf("%s(): CONTROL_STD_FUSE_PROD_ID_1 = 0x%08X\n",
__func__, prod_id_1);
si_type = (silicon_type) extract_bitfield(prod_id_1, 16, 2);
} else if (cpu_is_omap54xx()) {
if (cpu_revision_get() == REV_ES1_0) {
if (cpu_silicon_max_speed_get() != 1200)
cpu_silicon_type_set(STANDARD_PERF_SI);
else
cpu_silicon_type_set(SPEEDBIN_SI);
} else {
if (cpu_silicon_max_speed_get() != 1700)
cpu_silicon_type_set(STANDARD_PERF_SI);
else
cpu_silicon_type_set(SPEEDBIN_SI);
}
} else if (cpu_is_dra7xx()) {
/* TBD: implement true detection when ID data is available */
cpu_silicon_type_set(STANDARD_PERF_SI);
} else if (cpu_is_am335x()){
if (mem_read(EFUSE_SMA_REG, &efuse) != 0) {
fprintf(stderr,
"omapconf: (%s()): could not read EFUSE_SMA register!\n",
__func__);
return OMAPCONF_ERR_REG_ACCESS;
}
switch (extract_bitfield(efuse, 16, 2)) {
case 0:
/*
* Silicon revision 1.0 does not support EFUSE SMA REG
* (returns all 0's if read)
* Setting as unknown until there is an alternate method
*/
cpu_package_type_set(PACKAGE_TYPE_MAX);
break;
case 1:
cpu_package_type_set(ZCZ);
break;
case 2:
cpu_package_type_set(ZCE);
break;
default:
fprintf(stderr,
"omapconf: (%s()): could not identify package type!\n",
__func__);
return OMAPCONF_ERR_UNEXPECTED;
}
}
dprintf("%s(): Silicon performance type is %s (%uMHz)\n",
__func__, cpu_silicon_type_gets(s),
cpu_silicon_max_speed_get());
/* Set CPU full name */
cpu_full_name_set();
dprintf("%s(): CPU full name is %s\n", __func__, cpu_full_name);
return 0;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION emif54xx_dump
* @BRIEF dump selected registers
* @RETURNS 0 in case of success
* OMAPCONF_ERR_CPU
* OMAPCONF_ERR_ARG
* @param[in,out] stream: output stream
* @param[in] id: EMIF module ID
* If id == EMIF54XX_MODS_COUNT, dump all EMIF registers.
* @DESCRIPTION dump selected registers and pretty-print it in selected
* output stream
*//*------------------------------------------------------------------------ */
int emif54xx_dump(FILE *stream, emif54xx_mod_id id)
{
unsigned int i = 0, mid, accessible;
unsigned int val = 0;
int err = 0;
reg **mod;
reg *r;
char s[TABLE_MAX_ELT_LEN];
char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN];
unsigned int row;
CHECK_CPU(54xx, OMAPCONF_ERR_CPU);
CHECK_NULL_ARG(stream, OMAPCONF_ERR_ARG);
if (id > EMIF54XX_MODS_COUNT) {
fprintf(stderr, "%s(): id (%u) > EMIF54XX_MODS_COUNT!!! (%u)\n",
__func__, id, EMIF54XX_MODS_COUNT);
err = OMAPCONF_ERR_ARG;
goto emif54xx_dump_end;
}
autoadjust_table_init(table);
row = 0;
if (id != EMIF54XX_MODS_COUNT)
snprintf(table[row][0], TABLE_MAX_ELT_LEN, "%s Reg. Name",
emif54xx_mod_name_get(id));
else
strncpy(table[row][0], "EMIF Reg. Name", TABLE_MAX_ELT_LEN);
strncpy(table[row][1], "Reg. Address",
TABLE_MAX_ELT_LEN);
strncpy(table[row][2], "Reg. Value", TABLE_MAX_ELT_LEN);
row++;
for (mid = 0; mid < EMIF54XX_MODS_COUNT; mid++) {
if ((id != EMIF54XX_MODS_COUNT) && (mid != id))
continue;
else {
switch (mid) {
case EMIF54XX_EMIF1:
accessible = module_is_accessible(MOD_EMIF1);
break;
case EMIF54XX_EMIF2:
accessible = module_is_accessible(MOD_EMIF2);
break;
default:
accessible = 0;
}
if (!accessible) {
printf("%s module is not running, registers not"
" accessible.\n",
emif54xx_mod_name_get(mid));
return 0;
}
if (cpu_revision_get() == REV_ES1_0)
mod = emif54xxes1_mods[mid];
else
mod = emif54xx_mods[mid];
for (i = 0; mod[i] != NULL; i++) {
r = mod[i];
/* Read register */
dprintf("%s(): read %s 0x%08X\n", __func__,
r->name, r->addr);
val = reg_read(r);
dprintf("%s(): OK\n", __func__);
/* Show register name, addr & content */
snprintf(s, TABLE_MAX_ELT_LEN, "%s", r->name);
autoadjust_table_strncpy(table, row, 0, s);
snprintf(s, TABLE_MAX_ELT_LEN, "0x%08X",
r->addr);
autoadjust_table_strncpy(table, row, 1, s);
snprintf(s, TABLE_MAX_ELT_LEN, "0x%08X", val);
autoadjust_table_strncpy(table, row++, 2, s);
}
}
}
autoadjust_table_print(table, row, 3);
emif54xx_dump_end:
return err;
}
/**
* Function: dpll44xx_init_regtable
* Role: initialize .addr field of reg_table (not possible statically)
* Parameters:
* none
* Return:
* 0
* OMAPCONF_ERR_CPU
*/
int dpll44xx_init_regtable(void)
{
unsigned int i = 0;
CHECK_CPU(44xx, OMAPCONF_ERR_CPU);
if (dpll44xx_prcm_reg_table_init_done == 1)
return 0;
/* Init DPLLs registers table */
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKMODE_DPLL_CORE;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKMODE_DPLL_CORE");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_IDLEST_DPLL_CORE;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_IDLEST_DPLL_CORE");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_AUTOIDLE_DPLL_CORE;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_AUTOIDLE_DPLL_CORE");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKSEL_DPLL_CORE;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKSEL_DPLL_CORE");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M2_DPLL_CORE;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M2_DPLL_CORE");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M3_DPLL_CORE;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M3_DPLL_CORE");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M4_DPLL_CORE;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M4_DPLL_CORE");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M5_DPLL_CORE;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M5_DPLL_CORE");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M6_DPLL_CORE;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M6_DPLL_CORE");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M7_DPLL_CORE;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M7_DPLL_CORE");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_DELTAMSTEP_DPLL_CORE");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_MODFREQDIV_DPLL_CORE");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_EMU_OVERRIDE_DPLL_CORE");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKMODE_DPLL_PER;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKMODE_DPLL_PER");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_IDLEST_DPLL_PER;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_IDLEST_DPLL_PER");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_AUTOIDLE_DPLL_PER;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_AUTOIDLE_DPLL_PER");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKSEL_DPLL_PER;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKSEL_DPLL_PER");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M2_DPLL_PER;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M2_DPLL_PER");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M3_DPLL_PER;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M3_DPLL_PER");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M4_DPLL_PER;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M4_DPLL_PER");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M5_DPLL_PER;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M5_DPLL_PER");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M6_DPLL_PER;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M6_DPLL_PER");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M7_DPLL_PER;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M7_DPLL_PER");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_DELTAMSTEP_DPLL_PER");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_MODFREQDIV_DPLL_PER");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_EMU_OVERRIDE_DPLL_PER;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_EMU_OVERRIDE_DPLL_PER");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKMODE_DPLL_MPU;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKMODE_DPLL_MPU");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_IDLEST_DPLL_MPU;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_IDLEST_DPLL_MPU");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_AUTOIDLE_DPLL_MPU;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_AUTOIDLE_DPLL_MPU");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKSEL_DPLL_MPU;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKSEL_DPLL_MPU");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M2_DPLL_MPU;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M2_DPLL_MPU");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_DELTAMSTEP_DPLL_MPU");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_MODFREQDIV_DPLL_MPU");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_BYPCLK_DPLL_MPU;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_BYPCLK_DPLL_MPU");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKMODE_DPLL_IVA;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKMODE_DPLL_IVA");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_IDLEST_DPLL_IVA;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_IDLEST_DPLL_IVA");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_AUTOIDLE_DPLL_IVA;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_AUTOIDLE_DPLL_IVA");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKSEL_DPLL_IVA;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKSEL_DPLL_IVA");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M4_DPLL_IVA;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M4_DPLL_IVA");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M5_DPLL_IVA;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M5_DPLL_IVA");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_DELTAMSTEP_DPLL_IVA");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_MODFREQDIV_DPLL_IVA");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_BYPCLK_DPLL_IVA;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_BYPCLK_DPLL_IVA");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKMODE_DPLL_ABE;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKMODE_DPLL_ABE");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_IDLEST_DPLL_ABE;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_IDLEST_DPLL_ABE");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_AUTOIDLE_DPLL_ABE;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_AUTOIDLE_DPLL_ABE");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKSEL_DPLL_ABE;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKSEL_DPLL_ABE");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M2_DPLL_ABE;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M2_DPLL_ABE");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M3_DPLL_ABE;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M3_DPLL_ABE");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_DELTAMSTEP_DPLL_ABE");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_MODFREQDIV_DPLL_ABE");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKMODE_DPLL_USB;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKMODE_DPLL_USB");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_IDLEST_DPLL_USB;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_IDLEST_DPLL_USB");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_AUTOIDLE_DPLL_USB;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_AUTOIDLE_DPLL_USB");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_CLKSEL_DPLL_USB;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_CLKSEL_DPLL_USB");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_DIV_M2_DPLL_USB;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_DIV_M2_DPLL_USB");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_DELTAMSTEP_DPLL_USB");
dpll44xx_prcm_reg_table[i].addr = OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB;
strcpy(dpll44xx_prcm_reg_table[i++].name, "CM_SSC_MODFREQDIV_DPLL_USB");
if (cpu_is_omap4430() && (cpu_revision_get() == REV_ES1_0)) {
dpll44xx_prcm_reg_table[i].addr =
OMAP4430_CM_CLKMODE_DPLL_UNIPRO;
strcpy(dpll44xx_prcm_reg_table[i++].name,
"CM_CLKMODE_DPLL_UNIPRO");
dpll44xx_prcm_reg_table[i].addr =
OMAP4430_CM_IDLEST_DPLL_UNIPRO;
strcpy(dpll44xx_prcm_reg_table[i++].name,
"CM_IDLEST_DPLL_UNIPRO");
dpll44xx_prcm_reg_table[i].addr =
OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO;
strcpy(dpll44xx_prcm_reg_table[i++].name,
"CM_AUTOIDLE_DPLL_UNIPRO");
dpll44xx_prcm_reg_table[i].addr =
OMAP4430_CM_CLKSEL_DPLL_UNIPRO;
strcpy(dpll44xx_prcm_reg_table[i++].name,
"CM_CLKSEL_DPLL_UNIPRO");
dpll44xx_prcm_reg_table[i].addr =
OMAP4430_CM_DIV_M2_DPLL_UNIPRO;
strcpy(dpll44xx_prcm_reg_table[i++].name,
"CM_DIV_M2_DPLL_UNIPRO");
dpll44xx_prcm_reg_table[i].addr =
OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO;
strcpy(dpll44xx_prcm_reg_table[i++].name,
"CM_SSC_DELTAMSTEP_DPLL_UNIPRO");
dpll44xx_prcm_reg_table[i].addr =
OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO;
strcpy(dpll44xx_prcm_reg_table[i++].name,
"CM_SSC_MODFREQDIV_DPLL_UNIPRO");
dpll44xx_prcm_reg_table[i].addr =
OMAP4430_CM_CLKMODE_DPLL_DDRPHY;
strcpy(dpll44xx_prcm_reg_table[i++].name,
"CM_CLKMODE_DPLL_DDRPHY");
dpll44xx_prcm_reg_table[i].addr =
OMAP4430_CM_IDLEST_DPLL_DDRPHY;
strcpy(dpll44xx_prcm_reg_table[i++].name,
"CM_IDLEST_DPLL_DDRPHY");
dpll44xx_prcm_reg_table[i].addr =
OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY;
strcpy(dpll44xx_prcm_reg_table[i++].name,
"CM_AUTOIDLE_DPLL_DDRPHY");
dpll44xx_prcm_reg_table[i].addr =
OMAP4430_CM_CLKSEL_DPLL_DDRPHY;
strcpy(dpll44xx_prcm_reg_table[i++].name,
"CM_CLKSEL_DPLL_DDRPHY");
dpll44xx_prcm_reg_table[i].addr =
OMAP4430_CM_DIV_M2_DPLL_DDRPHY;
strcpy(dpll44xx_prcm_reg_table[i++].name,
"CM_DIV_M2_DPLL_DDRPHY");
dpll44xx_prcm_reg_table[i].addr =
OMAP4430_CM_DIV_M4_DPLL_DDRPHY;
strcpy(dpll44xx_prcm_reg_table[i++].name,
"CM_DIV_M4_DPLL_DDRPHY");
dpll44xx_prcm_reg_table[i].addr =
OMAP4430_CM_DIV_M5_DPLL_DDRPHY;
strcpy(dpll44xx_prcm_reg_table[i++].name,
"CM_DIV_M5_DPLL_DDRPHY");
dpll44xx_prcm_reg_table[i].addr =
OMAP4430_CM_DIV_M6_DPLL_DDRPHY;
strcpy(dpll44xx_prcm_reg_table[i++].name,
"CM_DIV_M6_DPLL_DDRPHY");
dpll44xx_prcm_reg_table[i].addr =
OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY;
strcpy(dpll44xx_prcm_reg_table[i++].name,
"CM_SSC_DELTAMSTEP_DPLL_DDRPHY");
dpll44xx_prcm_reg_table[i].addr =
OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY;
strcpy(dpll44xx_prcm_reg_table[i++].name,
"CM_SSC_MODFREQDIV_DPLL_DDRPHY");
}
dpll44xx_prcm_reg_table[i].addr = 0;
strcpy(dpll44xx_prcm_reg_table[i].name, "END");
dpll44xx_prcm_reg_table_init_done = 1;
return 0;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION ctrlmod54xx_io_audit
* @BRIEF OMAP5 PADCONF/IO audit.
* @RETURNS 0 in case of success
* OMAPCONF_ERR_ARG
* OMAPCONF_ERR_CPU
* @param[in,out] stream: output file - NULL: no output (silent)
* @param[in,out] err_nbr: pointer to return audit error number
* @param[in,out] wng_nbr: pointer to return audit warning number
* @DESCRIPTION OMAP5 PADCONF/IO audit.
*//*------------------------------------------------------------------------ */
int ctrlmod54xx_io_audit(FILE *stream, unsigned int *err_nbr,
unsigned int *wng_nbr)
{
const char pass[5] = "pass";
const char fail[5] = "FAIL";
const char ignore[5] = "ign.";
const char warning[5] = "warn";
char *status;
char table[TABLE_MAX_ROW][TABLE_MAX_COL][TABLE_MAX_ELT_LEN];
unsigned int row, i, j, curr, expected, max;
ctrlmod54xx_golden_item *golden_values;
reg **ctrlmod_regs;
CHECK_CPU(54xx, OMAPCONF_ERR_CPU);
CHECK_NULL_ARG(err_nbr, OMAPCONF_ERR_ARG);
CHECK_NULL_ARG(wng_nbr, OMAPCONF_ERR_ARG);
*err_nbr = 0;
*wng_nbr = 0;
if (cpu_revision_get() != REV_ES1_0) {
fprintf(stream,
"No golden settings available for OMAP5430 ES2.x, sorry...\n\n");
status = (char *) warning;
(*wng_nbr)++;
return OMAPCONF_ERR_CPU;
}
for (j = 0; j < 4; j++) {
autoadjust_table_init(table);
row = 0;
switch (j) {
case 0:
snprintf(table[row][0], TABLE_MAX_ELT_LEN,
"CONTROL MODULE CORE registers AUDIT");
if (cpu_revision_get() == REV_ES1_0) {
golden_values = (ctrlmod54xx_golden_item *)
ctrlmod_core54xxes1_golden_values;
ctrlmod_regs = omap5430es1_ctrl_module_core_mod;
max = OMAP5430ES1_CTRL_MODULE_CORE_MOD_REGCOUNT;
} else { /* FIXME WHEN ES2.0 targets available */
golden_values = (ctrlmod54xx_golden_item *)
ctrlmod_core54xxes1_golden_values;
ctrlmod_regs = omap5430_ctrl_module_core_mod;
max = OMAP5430_CTRL_MODULE_CORE_MOD_REGCOUNT;
}
break;
case 1:
snprintf(table[row][0], TABLE_MAX_ELT_LEN,
"CONTROL MODULE CORE PADCONF Registers AUDIT");
if (cpu_revision_get() == REV_ES1_0) {
golden_values = (ctrlmod54xx_golden_item *)
ctrlmod_core_pad54xxes1_golden_values;
ctrlmod_regs =
omap5430es1_ctrl_module_core_pad_mod;
max = OMAP5430_CTRL_MODULE_CORE_PAD_MOD_REGCOUNT;
} else {
golden_values = (ctrlmod54xx_golden_item *)
ctrlmod_core_pad54xxes1_golden_values;
ctrlmod_regs =
omap5430_ctrl_module_core_pad_mod;
max = OMAP5430_CTRL_MODULE_CORE_PAD_MOD_REGCOUNT;
}
break;
case 2:
snprintf(table[row][0], TABLE_MAX_ELT_LEN,
"CONTROL MODULE WKUP Registers AUDIT");
if (cpu_revision_get() == REV_ES1_0) {
golden_values = (ctrlmod54xx_golden_item *)
ctrlmod_wkup54xxes1_golden_values;
ctrlmod_regs = omap5430es1_ctrl_module_wkup_mod;
max = OMAP5430ES1_CTRL_MODULE_WKUP_MOD_REGCOUNT;
} else { /* FIXME WHEN ES2.0 targets available */
golden_values = (ctrlmod54xx_golden_item *)
ctrlmod_wkup54xxes1_golden_values;
ctrlmod_regs = omap5430_ctrl_module_wkup_mod;
max = OMAP5430ES1_CTRL_MODULE_WKUP_MOD_REGCOUNT;
}
break;
case 3:
snprintf(table[row][0], TABLE_MAX_ELT_LEN,
"CONTROL MODULE WKUP PADCONF Registers AUDIT");
if (cpu_revision_get() == REV_ES1_0) {
golden_values = (ctrlmod54xx_golden_item *)
ctrlmod_wkup_pad54xxes1_golden_values;
ctrlmod_regs = omap5430_ctrl_module_wkup_pad_mod;
max = OMAP5430_CTRL_MODULE_WKUP_PAD_MOD_REGCOUNT;
} else { /* FIXME WHEN ES2.0 targets available */
golden_values = (ctrlmod54xx_golden_item *)
ctrlmod_wkup_pad54xxes1_golden_values;
ctrlmod_regs = omap5430_ctrl_module_wkup_pad_mod;
max = OMAP5430_CTRL_MODULE_WKUP_PAD_MOD_REGCOUNT;
}
break;
}
snprintf(table[row][1], TABLE_MAX_ELT_LEN, "Current");
snprintf(table[row][2], TABLE_MAX_ELT_LEN, "Expected");
snprintf(table[row++][3], TABLE_MAX_ELT_LEN, "STATUS");
for (i = 0; i < max; i++) {
/* Read register */
curr = reg_read(ctrlmod_regs[i]);
/* Store name & register read content in table */
snprintf(table[row][0], TABLE_MAX_ELT_LEN, "%s",
(ctrlmod_regs[i])->name);
snprintf(table[row][1], TABLE_MAX_ELT_LEN, "0x%08X",
curr);
/* Compare to golden value */
switch (golden_values[i].valid) {
case DATA_INVALID:
case DATA_TBD:
status = (char *) warning;
(*wng_nbr)++;
snprintf(table[row][2], TABLE_MAX_ELT_LEN,
" TBD");
break;
case DATA_VALID:
expected = golden_values[i].golden_value;
snprintf(table[row][2], TABLE_MAX_ELT_LEN,
"0x%08X", expected);
if (curr != expected) {
status = (char *) fail;
(*err_nbr)++;
} else {
status = (char *) pass;
}
break;
case DATA_IGNORE:
status = (char *) ignore;
break;
default:
fprintf(stderr,
"%s(): something's wrong here?! (j=%u, "
"i=%u, golden_values[i].valid=%u)\n",
__func__, j, i, golden_values[i].valid);
}
/* Store status in table */
snprintf(table[row++][3], TABLE_MAX_ELT_LEN, "%s",
status);
}
if (stream != NULL) {
autoadjust_table_fprint(stream, table, row, 4);
fprintf(stream, " ### WARNING: PRELIMINARY ###\n");
fprintf(stream, " ### GOLDEN VALUES STILL TO BE "
"VERIFIED/COMPLETED!!! ###\n\n");
}
}
/* Print audit results summary */
if (stream != NULL) {
if (*err_nbr == 0)
fprintf(stream, "\nSUCCESS! Clock Speed audit "
"completed with 0 error (%d warning(s))\n\n",
*wng_nbr);
else
fprintf(stream, "\nFAILED! Clock Speed audit "
"completed with %d error and %d warning.\n\n",
*err_nbr, *wng_nbr);
}
return 0;
}
