void IRQ_manager::bsp_init()
{
const auto WORDS_PER_BMP = IRQ_LINES / 32;
auto* bmp = new MemBitmap::word[WORDS_PER_BMP * 3]();
irq_subs.set_location(bmp + 0 * WORDS_PER_BMP, WORDS_PER_BMP);
irq_pend.set_location(bmp + 1 * WORDS_PER_BMP, WORDS_PER_BMP);
irq_todo.set_location(bmp + 2 * WORDS_PER_BMP, WORDS_PER_BMP);
//Create an idt entry for the 'lidt' instruction
idt_loc idt_reg;
idt_reg.limit = INTR_LINES * sizeof(IDTDescr) - 1;
idt_reg.base = (uint32_t)idt;
INFO("INTR", "Creating interrupt handlers");
for (size_t i = 0; i < 32; i++) {
create_gate(&idt[i],exception_handler,default_sel,default_attr);
}
// Set all interrupt-gates >= 32 to unused do-nothing handler
for (size_t i = 32; i < INTR_LINES; i++) {
create_gate(&idt[i],unused_interrupt_handler,default_sel,default_attr);
}
// spurious interrupts (should not happen)
// currently set to be the last interrupt vector
create_gate(&idt[INTR_LINES-1], spurious_intr, default_sel, default_attr);
INFO2("+ Default interrupt gates set for irq >= 32");
// Load IDT
asm volatile ("lidt %0": :"m"(idt_reg) );
}
bool netlist::create_gates(const evl_components &comps,
const evl_wires_table &wires_table)
{
for (evl_components::const_iterator ci = comps.begin(); ci !=comps.end(); ++ci)
{
evl_component c = (*ci);
create_gate(c, wires_table); // gate semantic vilation only output an error, does not stop the program
}
return true;
}
void IRQ_manager::set_handler(uint8_t vec, intr_func func) {
create_gate(&idt[vec], func, default_sel, default_attr);
}
