* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE. */
#include <stdint.h>
#include <pru_cfg.h>
volatile register uint32_t __R30;
volatile register uint32_t __R31;
/* Mapping Constant table register to variable */
volatile pruCfg CT_CFG __attribute__((cregister("CFG", near), peripheral));
void main(){
volatile uint32_t gpio;
/* Clear SYSCFG[STANDBY_INIT] to enable OCP master port */
CT_CFG.SYSCFG_bit.STANDBY_INIT = 0;
/* Toggle GPO pins TODO: Figure out which to use */
gpio = 0x000F;
/* TODO: Create stop condition, else it will toggle indefinitely */
while(1){
__R30 ^= gpio;
__delay_cycles(100000000);
* POSSIBILITY OF SUCH DAMAGE. */
/* This program waits for sysevent 16 from ARM. It sends and interrupt to ARM
using sysevent 32 which is generated by writing to its own R31 register.
Sysevent 16 is then cleared by this code. The ARM remoteproc driver is
responsible for clearing sysevent 32 */
#include <stdint.h>
#include <pru_cfg.h>
#include <pru_intc.h>
#include "resource_table_1.h"
volatile register uint32_t __R30;
volatile register uint32_t __R31;
/* Mapping Constant table register to variable */
volatile pruCfg CT_CFG __attribute__((cregister("PRU_CFG", near), peripheral));
volatile far pruIntc CT_INTC __attribute__((cregister("PRU_INTC", far), peripheral));
volatile far uint32_t CT_DRAM __attribute__((cregister("PRU_DMEM_0_1", near), peripheral));
/* Defines */
#define PRU1
#define HOST1_MASK (0x80000000)
#define PRU0_PRU1_EVT (16)
#define TOGGLE_BLUE (__R30 ^= (1 << 7))
void main(){
/* Configure GPI and GPO as Mode 0 (Direct Connect) */
CT_CFG.GPCFG0 = 0x0000;
uint32_t *dram = (uint32_t *) &CT_DRAM;
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdint.h>
#include <pru_cfg.h>
#include <pru_ctrl.h>
#include "resource_table_empty.h"
/* Mapping Constant Table (CT) registers to variables */
volatile far uint8_t CT_MCSPI0 __attribute__((cregister("MCSPI0", near), peripheral));
#ifndef PRU_SRAM
#define PRU_SRAM __far __attribute__((cregister("PRU_SHAREDMEM", near)))
#endif
/* NOTE: Allocating shared_freq_x to PRU Shared Memory means that other PRU cores on
* the same subsystem must take care not to allocate data to that memory.
* Users also cannot rely on where in shared memory these variables are placed
* so accessing them from another PRU core or from the ARM is an undefined behavior.
*/
PRU_SRAM volatile uint32_t shared_freq_1;
PRU_SRAM volatile uint32_t shared_freq_2;
PRU_SRAM volatile uint32_t shared_freq_3;
/* PRCM Registers */
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE. */
#include <stdint.h>
#include <pru_cfg.h>
#include <pru_ctrl.h>
#include <pru_intc.h>
#include "resource_table_empty.h"
volatile register uint32_t __R30;
volatile register uint32_t __R31;
/* Mapping Constant table register to variable */
volatile far pruIntc CT_INTC __attribute__((cregister("PRU_INTC", far), peripheral));
volatile pruCfg CT_CFG __attribute__((cregister("PRU_CFG", near), peripheral));
volatile far uint32_t CT_L3 __attribute__((cregister("L3OCMC", near), peripheral));
volatile far uint32_t CT_DDR __attribute__((cregister("DDR", near), peripheral));
/* PRU-to-ARM interrupt */
#define PRU0_ARM_INTERRUPT (19+16)
#define HOST_NUM 2
#define CHAN_NUM 2
void main(){
uint32_t *pDdr = (uint32_t *) &CT_DDR;
uint32_t score;
/* Clear SYSCFG[STANDBY_INIT] to enable OCP master port */
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE. */
#include <stdint.h>
#include <pru_cfg.h>
#include <pru_intc.h>
#include <pru_ctrl.h>
#include <pru_ecap.h>
#include "PRU_1wire.h"
#include <string.h>
volatile register uint32_t __R30;
volatile register uint32_t __R31;
/* Mapping Constant table register to variable */
volatile far pruIntc CT_INTC __attribute__((cregister("PRU_INTC", far), peripheral));
volatile pruCfg CT_CFG __attribute__((cregister("PRU_CFG", near), peripheral));
volatile pruEcap CT_ECAP __attribute__((cregister("PRU_ECAP", near), peripheral));
/******************************************************************************
** INTERNAL FUNCTION DEFINITIONS
******************************************************************************/
void intc_config(void);
void pwm_config(unsigned int time_interval);
/* PRU peripheral system event */
#define PRU_IEP_EVT 7
#define PRU_ECAP_EVT 15
/* PRU-to-PRU system event */
#define PRU_SLAVE_MASTER_EVT 20
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdint.h>
#include <pru_cfg.h>
#include <pru_intc.h>
#include <pru_ctrl.h>
#include "resource_table_empty.h"
volatile register uint32_t __R30;
volatile register uint32_t __R31;
/* Mapping Constant table register to variable */
volatile far uint32_t CT_DDR __attribute__((cregister("DDR", near), peripheral));
/* PRU-to-ARM interrupt */
#define PRU0_ARM_INTERRUPT (19+16)
#define HOST_NUM 2
#define CHAN_NUM 2
void main(void)
{
uint32_t *pDdr = (uint32_t *) &CT_DDR;
/* Clear SYSCFG[STANDBY_INIT] to enable OCP master port */
CT_CFG.SYSCFG_bit.STANDBY_INIT = 0;
// Globally enable host interrupts
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE. */
#include <stdint.h>
#include <pru_uart.h>
#include "resource_table_empty.h"
/* Define UART register "overlay" */
volatile far pruUart CT_UART __attribute__((cregister("PRU_UART", near), peripheral));
/* The FIFO size on the PRU UART is 16 bytes; however, we are (arbitrarily)
* only going to send 8 at a time */
#define FIFO_SIZE 16
#define MAX_CHARS 8
/* This hostBuffer structure is temporary but stores a data buffer */
struct {
uint8_t msg; // Not used today
uint8_t data[FIFO_SIZE];
} hostBuffer;
/* Making this buffer global will force the received data into memory */
uint8_t buffer[MAX_CHARS];
* POSSIBILITY OF SUCH DAMAGE. */
#include <stdint.h>
#include <pru_cfg.h>
#include <pru_intc.h>
#include <pru_ctrl.h>
#include <pru_iep.h>
#include "PRU_1wire.h"
#include <string.h>
volatile register uint32_t __R30;
volatile register uint32_t __R31;
/* Mapping Constant table register to variable */
volatile far pruIntc CT_INTC __attribute__((cregister("PRU_INTC", far), peripheral));
volatile pruCfg CT_CFG __attribute__((cregister("PRU_CFG", near), peripheral));
volatile far pruIep CT_IEP __attribute__((cregister("PRU_IEP", far), peripheral));
volatile far char CT_DMEM[64] __attribute__((cregister("PRU_DMEM_0_1", far), peripheral));
/******************************************************************************
** INTERNAL FUNCTION DEFINITIONS
******************************************************************************/
void write_cmd(unsigned int cmd);
void write_0(void);
void write_1(void);
unsigned int read();
unsigned int init();
void reset(void);
void timer(unsigned int cmp);
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE. */
#include <stdint.h>
#include <pru_cfg.h>
/*TODO: Include intc.h */
// PRU Core 1
#define PRU1
volatile register uint32_t __R30;
volatile register uint32_t __R31;
/* Mapping Constant table register to variable */
volatile pruCfg CT_CFG __attribute__((cregister("C4_CFG", near), peripheral));
volatile far pruIntc CT_INTC __attribute__((cregister("C0_INTC", far), peripheral));
/* Defines */
#define PRU0
/* PRU0-to-PRU1 interrupt */
#define PRU0_PRU1_EVT (16)
#define PRU0_PRU1_TRIGGER (__R31 = (PRU0_PRU1_EVT - 16) | (1 << 5))
/* SW1 offset */
/*TODO: Define GPI offset for SW1 */
/* INTC configuration
* We are going to map User event 16 to Host 1
* PRU1 will then wait for r31 bit 31 (designates Host 1) to go high
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE. */
#include <stdint.h>
#include <pru_cfg.h>
#include <pru_ctrl.h>
/* Mapping Constant table registers to variables */
volatile far pruCfg CT_CFG __attribute__((cregister("CFG", near), peripheral));
volatile far uint32_t CT_DDR __attribute__((cregister("DDR", near), peripheral));
/* This is a char so that I can force access to R31.b0 for the host interrupt */
volatile register uint8_t __R31;
/* Definition of control register structures. */
#pragma DATA_SECTION(PRU0_CTRL, ".PRU0_CTRL");
volatile far pruCtrl PRU0_CTRL;
/* PRU-to-ARM interrupt */
#define PRU_ARM_INTERRUPT (19+16)
int main(){
uint32_t *ddrPtr = (uint32_t *)&CT_DDR;
uint32_t result;
