static int __init init(void) { int ret; if (!crypt_s390_func_available(KIMD_SHA_512)) return -EOPNOTSUPP; if ((ret = crypto_register_shash(&sha512_alg)) < 0) goto out; if ((ret = crypto_register_shash(&sha384_alg)) < 0) crypto_unregister_shash(&sha512_alg); out: return ret; }
static int __init sha256_s390_init(void) { int ret; if (!crypt_s390_func_available(KIMD_SHA_256, CRYPT_S390_MSA)) return -EOPNOTSUPP; ret = crypto_register_shash(&sha256_alg); if (ret < 0) goto out; ret = crypto_register_shash(&sha224_alg); if (ret < 0) crypto_unregister_shash(&sha256_alg); out: return ret; }
static int __init crct10dif_intel_mod_init(void) { if (!x86_match_cpu(crct10dif_cpu_id)) return -ENODEV; return crypto_register_shash(&alg); }
static int __init sha256_generic_mod_init(void) { int ret = 0; ret = crypto_register_shash(&sha224); if (ret < 0) return ret; ret = crypto_register_shash(&sha256); if (ret < 0) crypto_unregister_shash(&sha224); return ret; }
static int __init crct10dif_mod_init(void) { int ret; ret = crypto_register_shash(&alg); return ret; }
static int __init crc32c_intel_mod_init(void) { if (cpu_has_xmm4_2) return crypto_register_shash(&alg); else return -ENODEV; }
int __init p8_init(void) { int ret = 0; struct crypto_alg **alg_it; for (alg_it = algs; *alg_it; alg_it++) { ret = crypto_register_alg(*alg_it); printk(KERN_INFO "crypto_register_alg '%s' = %d\n", (*alg_it)->cra_name, ret); if (ret) { for (alg_it--; alg_it >= algs; alg_it--) crypto_unregister_alg(*alg_it); break; } } if (ret) return ret; ret = crypto_register_shash(&p8_ghash_alg); if (ret) { for (alg_it = algs; *alg_it; alg_it++) crypto_unregister_alg(*alg_it); } return ret; }
static int sha256_s390_init(void) { if (!crypt_s390_func_available(KIMD_SHA_256)) return -EOPNOTSUPP; return crypto_register_shash(&alg); }
static int __init sha1_neon_mod_init(void) { if (!cpu_has_neon()) return -ENODEV; return crypto_register_shash(&alg); }
static int __init crypto_null_mod_init(void) { int ret = 0; ret = crypto_register_alg(&cipher_null); if (ret < 0) goto out; ret = crypto_register_alg(&skcipher_null); if (ret < 0) goto out_unregister_cipher; ret = crypto_register_shash(&digest_null); if (ret < 0) goto out_unregister_skcipher; ret = crypto_register_alg(&compress_null); if (ret < 0) goto out_unregister_digest; out: return ret; out_unregister_digest: crypto_unregister_shash(&digest_null); out_unregister_skcipher: crypto_unregister_alg(&skcipher_null); out_unregister_cipher: crypto_unregister_alg(&cipher_null); goto out; }
int cfs_crypto_crc32_register(void) { #ifdef HAVE_STRUCT_SHASH_ALG return crypto_register_shash(&alg); #else return crypto_register_alg(&alg); #endif }
int cfs_crypto_crc32c_pclmul_register(void) { if (!boot_cpu_has(X86_FEATURE_XMM4_2)) { CDEBUG(D_INFO, "CRC32 instruction is not detected.\n"); return -ENODEV; } return crypto_register_shash(&alg); }
static int __init crc32_pclmul_mod_init(void) { if (!x86_match_cpu(crc32pclmul_cpu_id)) { pr_info("PCLMULQDQ-NI instructions are not detected.\n"); return -ENODEV; } return crypto_register_shash(&alg); }
static int __init skein_generic_init(void) { if (crypto_register_shash(&alg256)) goto out; if (crypto_register_shash(&alg512)) goto unreg256; if (crypto_register_shash(&alg1024)) goto unreg512; return 0; unreg512: crypto_unregister_shash(&alg512); unreg256: crypto_unregister_shash(&alg256); out: return -1; }
static int __init crc32_mod_init(void) { int err; err = crypto_register_shash(&crc32_alg); if (err) return err; err = crypto_register_shash(&crc32c_alg); if (err) { crypto_unregister_shash(&crc32_alg); return err; } return 0; }
static int __init crc32c_intel_mod_init(void) { if (!x86_match_cpu(crc32c_cpu_id)) return -ENODEV; #ifdef CONFIG_X86_64 if (boot_cpu_has(X86_FEATURE_PCLMULQDQ)) { alg.update = crc32c_pcl_intel_update; alg.finup = crc32c_pcl_intel_finup; alg.digest = crc32c_pcl_intel_digest; } #endif return crypto_register_shash(&alg); }
static int __init openssl_module_init(void) { int rc; if ((rc = crypto_register_shash(&shaalg))) return rc; if ((rc = crypto_register_alg(&alg))) return rc; if (0) test2(); printk(KERN_INFO "OpenSSL loaded\n"); return 0; }
/*! \fn int __init ifxdeu_init_md5 (void) * \ingroup IFX_MD5_FUNCTIONS * \brief initialize md5 driver */ int __init ifxdeu_init_md5 (void) { int ret = -ENOSYS; if ((ret = crypto_register_shash(&ifxdeu_md5_alg))) goto md5_err; CRTCL_SECT_INIT; printk (KERN_NOTICE "IFX DEU MD5 initialized%s.\n", disable_deudma ? "" : " (DMA)"); return ret; md5_err: printk(KERN_ERR "IFX DEU MD5 initialization failed!\n"); return ret; }
static int __init crypto_null_mod_init(void) { int ret = 0; ret = crypto_register_algs(null_algs, ARRAY_SIZE(null_algs)); if (ret < 0) goto out; ret = crypto_register_shash(&digest_null); if (ret < 0) goto out_unregister_algs; return 0; out_unregister_algs: crypto_unregister_algs(null_algs, ARRAY_SIZE(null_algs)); out: return ret; }
static int __init ghash_pclmulqdqni_mod_init(void) { int err; if (!x86_match_cpu(pcmul_cpu_id)) return -ENODEV; err = crypto_register_shash(&ghash_alg); if (err) goto err_out; err = crypto_register_ahash(&ghash_async_alg); if (err) goto err_shash; return 0; err_shash: crypto_unregister_shash(&ghash_alg); err_out: return err; }
static int __init ghash_pclmulqdqni_mod_init(void) { int err; if (!cpu_has_pclmulqdq) { printk(KERN_INFO "Intel PCLMULQDQ-NI instructions are not" " detected.\n"); return -ENODEV; } err = crypto_register_shash(&ghash_alg); if (err) goto err_out; err = crypto_register_ahash(&ghash_async_alg); if (err) goto err_shash; return 0; err_shash: crypto_unregister_shash(&ghash_alg); err_out: return err; }
int cfs_crypto_adler32_register(void) { return crypto_register_shash(&alg); }
static int __init sha1_ce_mod_init(void) { return crypto_register_shash(&alg); }
static int __init ghash_mod_init(void) { return crypto_register_shash(&ghash_alg); }
/** * nx_register_algs - register algorithms with the crypto API * * Called from nx_probe() * * If all OF properties are in an acceptable state, the driver flags will * indicate that we're ready and we'll create our debugfs files and register * out crypto algorithms. */ static int nx_register_algs(void) { int rc = -1; if (nx_driver.of.flags != NX_OF_FLAG_MASK_READY) goto out; memset(&nx_driver.stats, 0, sizeof(struct nx_stats)); rc = NX_DEBUGFS_INIT(&nx_driver); if (rc) goto out; nx_driver.of.status = NX_OKAY; rc = crypto_register_alg(&nx_ecb_aes_alg); if (rc) goto out; rc = crypto_register_alg(&nx_cbc_aes_alg); if (rc) goto out_unreg_ecb; rc = crypto_register_alg(&nx_ctr_aes_alg); if (rc) goto out_unreg_cbc; rc = crypto_register_alg(&nx_ctr3686_aes_alg); if (rc) goto out_unreg_ctr; rc = crypto_register_alg(&nx_gcm_aes_alg); if (rc) goto out_unreg_ctr3686; rc = crypto_register_alg(&nx_gcm4106_aes_alg); if (rc) goto out_unreg_gcm; rc = crypto_register_alg(&nx_ccm_aes_alg); if (rc) goto out_unreg_gcm4106; rc = crypto_register_alg(&nx_ccm4309_aes_alg); if (rc) goto out_unreg_ccm; rc = crypto_register_shash(&nx_shash_sha256_alg); if (rc) goto out_unreg_ccm4309; rc = crypto_register_shash(&nx_shash_sha512_alg); if (rc) goto out_unreg_s256; rc = crypto_register_shash(&nx_shash_aes_xcbc_alg); if (rc) goto out_unreg_s512; goto out; out_unreg_s512: crypto_unregister_shash(&nx_shash_sha512_alg); out_unreg_s256: crypto_unregister_shash(&nx_shash_sha256_alg); out_unreg_ccm4309: crypto_unregister_alg(&nx_ccm4309_aes_alg); out_unreg_ccm: crypto_unregister_alg(&nx_ccm_aes_alg); out_unreg_gcm4106: crypto_unregister_alg(&nx_gcm4106_aes_alg); out_unreg_gcm: crypto_unregister_alg(&nx_gcm_aes_alg); out_unreg_ctr3686: crypto_unregister_alg(&nx_ctr3686_aes_alg); out_unreg_ctr: crypto_unregister_alg(&nx_ctr_aes_alg); out_unreg_cbc: crypto_unregister_alg(&nx_cbc_aes_alg); out_unreg_ecb: crypto_unregister_alg(&nx_ecb_aes_alg); out: return rc; }
static int __init rmd320_mod_init(void) { return crypto_register_shash(&alg); }
static int register_sha1_ni(void) { if (boot_cpu_has(X86_FEATURE_SHA_NI)) return crypto_register_shash(&sha1_ni_alg); return 0; }
static int register_sha1_avx2(void) { if (avx2_usable()) return crypto_register_shash(&sha1_avx2_alg); return 0; }
static int register_sha1_ssse3(void) { if (boot_cpu_has(X86_FEATURE_SSSE3)) return crypto_register_shash(&sha1_ssse3_alg); return 0; }
static int __init crc32c_mod_init(void) { return crypto_register_shash(&alg); }