int arch_cpu_init_dm(void)
{
int ret;
ret = riscv_cpu_probe();
if (ret)
return ret;
/* Enable FPU */
if (supports_extension('d') || supports_extension('f')) {
csr_set(MODE_PREFIX(status), MSTATUS_FS);
csr_write(fcsr, 0);
}
if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
/*
* Enable perf counters for cycle, time,
* and instret counters only
*/
csr_write(mcounteren, GENMASK(2, 0));
/* Disable paging */
if (supports_extension('s'))
csr_write(satp, 0);
}
return 0;
}
int watchdog_init(void)
{
/* Set overflow time*/
cnt_write(0);
/* Power on reset */
csr_write(WDT_WD|WDT_RST_P|WDT_ENABLE);
return 0;
}
int __cpuinit arch_cpu_irq_setup(void)
{
extern unsigned long _handle_exception[];
/* Setup final exception handler */
csr_write(stvec, (virtual_addr_t)&_handle_exception);
return VMM_OK;
}
void arch_vcpu_switch(struct vmm_vcpu *tvcpu,
struct vmm_vcpu *vcpu,
arch_regs_t *regs)
{
struct riscv_priv *priv;
if (tvcpu) {
memcpy(riscv_regs(tvcpu), regs, sizeof(*regs));
if (tvcpu->is_normal) {
priv = riscv_priv(tvcpu);
priv->hideleg = csr_read(CSR_HIDELEG);
priv->hedeleg = csr_read(CSR_HEDELEG);
priv->bsstatus = csr_read(CSR_BSSTATUS);
priv->bsie = csr_read(CSR_BSIE);
priv->bstvec = csr_read(CSR_BSTVEC);
priv->bsscratch = csr_read(CSR_BSSCRATCH);
priv->bsepc = csr_read(CSR_BSEPC);
priv->bscause = csr_read(CSR_BSCAUSE);
priv->bstval = csr_read(CSR_BSTVAL);
priv->bsip = csr_read(CSR_BSIP);
priv->bsatp = csr_read(CSR_BSATP);
}
}
memcpy(regs, riscv_regs(vcpu), sizeof(*regs));
if (vcpu->is_normal) {
priv = riscv_priv(vcpu);
csr_write(CSR_HIDELEG, priv->hideleg);
csr_write(CSR_HEDELEG, priv->hedeleg);
csr_write(CSR_BSSTATUS, priv->bsstatus);
csr_write(CSR_BSIE, priv->bsie);
csr_write(CSR_BSTVEC, priv->bstvec);
csr_write(CSR_BSSCRATCH, priv->bsscratch);
csr_write(CSR_BSEPC, priv->bsepc);
csr_write(CSR_BSCAUSE, priv->bscause);
csr_write(CSR_BSTVAL, priv->bstval);
csr_write(CSR_BSIP, priv->bsip);
csr_write(CSR_BSATP, priv->bsatp);
cpu_mmu_stage2_change_pgtbl(vcpu->guest->id,
riscv_guest_priv(vcpu->guest)->pgtbl);
}
}
int watchdog_disable(void)
{
csr_write(csr_read() & ~WDT_ENABLE);
return 0;
}
