/** * Shutdown and free resources required by packet output. */ void cvmx_pko_shutdown(void) { union cvmx_pko_mem_queue_ptrs config; int queue; cvmx_pko_disable(); for (queue = 0; queue < CVMX_PKO_MAX_OUTPUT_QUEUES; queue++) { config.u64 = 0; config.s.tail = 1; config.s.index = 0; config.s.port = CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID; config.s.queue = queue & 0x7f; config.s.qos_mask = 0; config.s.buf_ptr = 0; if (!OCTEON_IS_MODEL(OCTEON_CN3XXX)) { union cvmx_pko_reg_queue_ptrs1 config1; config1.u64 = 0; config1.s.qid7 = queue >> 7; cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64); } cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64); cvmx_cmd_queue_shutdown(CVMX_CMD_QUEUE_PKO(queue)); } __cvmx_pko_reset(); }
/** * Shutdown the DFA block. DFA must be idle when * this function is called. * * @return Zero on success, negative on failure */ int cvmx_hfa_shutdown(void) { if (cvmx_cmd_queue_length(CVMX_CMD_QUEUE_DFA)) { cvmx_dprintf("ERROR: cvmx_hfa_shutdown: DFA not idle.\n"); return -1; } cvmx_cmd_queue_shutdown(CVMX_CMD_QUEUE_DFA); return 0; }
/** * Shutdown the ZIP block for a queue. ZIP must be idle when * this function is called. * * @param queue Zip instruction queue of the command * * @return Zero on success, negative on failure */ int cvmx_zip_queue_shutdown(int queue) { cvmx_zip_cmd_ctl_t zip_cmd_ctl; if (cvmx_cmd_queue_length(CVMX_CMD_QUEUE_ZIP_QUE(queue))) { cvmx_dprintf("ERROR: cvmx_zip_shutdown: ZIP not idle.\n"); return -1; } zip_cmd_ctl.u64 = cvmx_read_csr(CVMX_ZIP_CMD_CTL); zip_cmd_ctl.s.reset = 1; cvmx_write_csr(CVMX_ZIP_CMD_CTL, zip_cmd_ctl.u64); cvmx_wait(100); cvmx_cmd_queue_shutdown(CVMX_CMD_QUEUE_ZIP_QUE(queue)); return 0; }
/** * Shutdown the RAID block. RAID must be idle when * this function is called. * * @return Zero on success, negative on failure */ int cvmx_raid_shutdown(void) { cvmx_rad_reg_ctl_t rad_reg_ctl; if (cvmx_cmd_queue_length(CVMX_CMD_QUEUE_RAID)) { cvmx_dprintf("ERROR: cvmx_raid_shutdown: RAID not idle.\n"); return -1; } rad_reg_ctl.u64 = cvmx_read_csr(CVMX_RAD_REG_CTL); rad_reg_ctl.s.reset = 1; cvmx_write_csr(CVMX_RAD_REG_CTL, rad_reg_ctl.u64); cvmx_wait(100); cvmx_cmd_queue_shutdown(CVMX_CMD_QUEUE_RAID); cvmx_write_csr(CVMX_RAD_REG_CMD_BUF, 0); return 0; }