static void end_fw_load(struct i2c_client *client) { /* AUTO_INC_DIS=0 */ cx25840_write(client, 0x000, 0x00); /* DL_ENABLE=0 */ cx25840_write(client, 0x803, 0x03); }
static void start_fw_load(struct i2c_client *client) { /* DL_ADDR_LB=0 DL_ADDR_HB=0 */ cx25840_write(client, 0x800, 0x00); cx25840_write(client, 0x801, 0x00); // DL_MAP=3 DL_AUTO_INC=0 DL_ENABLE=1 cx25840_write(client, 0x803, 0x0b); /* AUTO_INC_DIS=1 */ cx25840_write(client, 0x000, 0x20); }
static void set_volume(struct i2c_client *client, int volume) { struct cx25840_state *state = i2c_get_clientdata(client); int vol; if (state->unmute_volume >= 0) { state->unmute_volume = volume; return; } /* Convert the volume to msp3400 values (0-127) */ vol = volume >> 9; /* now scale it up to cx25840 values * -114dB to -96dB maps to 0 * this should be 19, but in my testing that was 4dB too loud */ if (vol <= 23) { vol = 0; } else { vol -= 23; } /* PATH1_VOLUME */ cx25840_write(client, 0x8d4, 228 - (vol * 2)); }
void cx25840_audio_set_path(struct i2c_client *client) { struct cx25840_state *state = i2c_get_clientdata(client); /* stop microcontroller */ cx25840_and_or(client, 0x803, ~0x10, 0); /* Mute everything to prevent the PFFT! */ cx25840_write(client, 0x8d3, 0x1f); if (state->aud_input == CX25840_AUDIO_SERIAL) { /* Set Path1 to Serial Audio Input */ cx25840_write4(client, 0x8d0, 0x12100101); /* The microcontroller should not be started for the * non-tuner inputs: autodetection is specific for * TV audio. */ } else { /* Set Path1 to Analog Demod Main Channel */ cx25840_write4(client, 0x8d0, 0x7038061f); /* When the microcontroller detects the * audio format, it will unmute the lines */ cx25840_and_or(client, 0x803, ~0x10, 0x10); } set_audclk_freq(client, state->audclk_freq); }
static void set_volume(struct i2c_client *client, int volume) { /* First convert the volume to msp3400 values (0-127) */ int vol = volume >> 9; /* now scale it up to cx25840 values * -114dB to -96dB maps to 0 * this should be 19, but in my testing that was 4dB too loud */ if (vol <= 23) { vol = 0; } else { vol -= 23; } /* PATH1_VOLUME */ cx25840_write(client, 0x8d4, 228 - (vol * 2)); }
void cx25840_audio_set_path(struct i2c_client *client) { struct cx25840_state *state = to_state(i2c_get_clientdata(client)); if (!is_cx2583x(state)) { /* assert soft reset */ cx25840_and_or(client, 0x810, ~0x1, 0x01); /* stop microcontroller */ cx25840_and_or(client, 0x803, ~0x10, 0); /* Mute everything to prevent the PFFT! */ cx25840_write(client, 0x8d3, 0x1f); if (state->aud_input == CX25840_AUDIO_SERIAL) { /* Set Path1 to Serial Audio Input */ cx25840_write4(client, 0x8d0, 0x01011012); /* The microcontroller should not be started for the * non-tuner inputs: autodetection is specific for * TV audio. */ } else { /* Set Path1 to Analog Demod Main Channel */ cx25840_write4(client, 0x8d0, 0x1f063870); } } set_audclk_freq(client, state->audclk_freq); if (!is_cx2583x(state)) { if (state->aud_input != CX25840_AUDIO_SERIAL) { /* When the microcontroller detects the * audio format, it will unmute the lines */ cx25840_and_or(client, 0x803, ~0x10, 0x10); } /* deassert soft reset */ cx25840_and_or(client, 0x810, ~0x1, 0x00); /* Ensure the controller is running when we exit */ if (is_cx2388x(state) || is_cx231xx(state)) cx25840_and_or(client, 0x803, ~0x10, 0x10); } }
int cx25840_s_clock_freq(struct v4l2_subdev *sd, u32 freq) { struct i2c_client *client = v4l2_get_subdevdata(sd); struct cx25840_state *state = to_state(sd); int retval; if (!state->is_cx25836) cx25840_and_or(client, 0x810, ~0x1, 1); if (state->aud_input != CX25840_AUDIO_SERIAL) { cx25840_and_or(client, 0x803, ~0x10, 0); cx25840_write(client, 0x8d3, 0x1f); } retval = set_audclk_freq(client, freq); if (state->aud_input != CX25840_AUDIO_SERIAL) cx25840_and_or(client, 0x803, ~0x10, 0x10); if (!state->is_cx25836) cx25840_and_or(client, 0x810, ~0x1, 0); return retval; }
static void set_mute(struct i2c_client *client, int mute) { struct cx25840_state *state = i2c_get_clientdata(client); if (state->aud_input != CX25840_AUDIO_SERIAL) { /* Must turn off microcontroller in order to mute sound. * Not sure if this is the best method, but it does work. * If the microcontroller is running, then it will undo any * changes to the mute register. */ if (mute) { /* disable microcontroller */ cx25840_and_or(client, 0x803, ~0x10, 0x00); cx25840_write(client, 0x8d3, 0x1f); } else { /* enable microcontroller */ cx25840_and_or(client, 0x803, ~0x10, 0x10); } } else { /* SRC1_MUTE_EN */ cx25840_and_or(client, 0x8d3, ~0x2, mute ? 0x02 : 0x00); } }
int cx25840_audio(struct i2c_client *client, unsigned int cmd, void *arg) { struct cx25840_state *state = i2c_get_clientdata(client); struct v4l2_control *ctrl = arg; int retval; switch (cmd) { case VIDIOC_INT_AUDIO_CLOCK_FREQ: if (!state->is_cx25836) cx25840_and_or(client, 0x810, ~0x1, 1); if (state->aud_input != CX25840_AUDIO_SERIAL) { cx25840_and_or(client, 0x803, ~0x10, 0); cx25840_write(client, 0x8d3, 0x1f); } retval = set_audclk_freq(client, *(u32 *)arg); if (state->aud_input != CX25840_AUDIO_SERIAL) { cx25840_and_or(client, 0x803, ~0x10, 0x10); } if (!state->is_cx25836) cx25840_and_or(client, 0x810, ~0x1, 0); return retval; case VIDIOC_G_CTRL: switch (ctrl->id) { case V4L2_CID_AUDIO_VOLUME: ctrl->value = get_volume(client); break; case V4L2_CID_AUDIO_BASS: ctrl->value = get_bass(client); break; case V4L2_CID_AUDIO_TREBLE: ctrl->value = get_treble(client); break; case V4L2_CID_AUDIO_BALANCE: ctrl->value = get_balance(client); break; case V4L2_CID_AUDIO_MUTE: ctrl->value = get_mute(client); break; default: return -EINVAL; } break; case VIDIOC_S_CTRL: switch (ctrl->id) { case V4L2_CID_AUDIO_VOLUME: set_volume(client, ctrl->value); break; case V4L2_CID_AUDIO_BASS: set_bass(client, ctrl->value); break; case V4L2_CID_AUDIO_TREBLE: set_treble(client, ctrl->value); break; case V4L2_CID_AUDIO_BALANCE: set_balance(client, ctrl->value); break; case V4L2_CID_AUDIO_MUTE: set_mute(client, ctrl->value); break; default: return -EINVAL; } break; default: return -EINVAL; } return 0; }
static int set_audclk_freq(struct i2c_client *client, u32 freq) { struct cx25840_state *state = i2c_get_clientdata(client); if (freq != 32000 && freq != 44100 && freq != 48000) return -EINVAL; /* common for all inputs and rates */ /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x10 */ cx25840_write(client, 0x127, 0x50); if (state->aud_input != CX25840_AUDIO_SERIAL) { switch (freq) { case 32000: /* VID_PLL and AUX_PLL */ cx25840_write4(client, 0x108, 0x0f040610); /* AUX_PLL_FRAC */ cx25840_write4(client, 0x110, 0xee39bb01); if (state->is_cx25836) break; /* src3/4/6_ctl = 0x0801f77f */ cx25840_write4(client, 0x900, 0x7ff70108); cx25840_write4(client, 0x904, 0x7ff70108); cx25840_write4(client, 0x90c, 0x7ff70108); break; case 44100: /* VID_PLL and AUX_PLL */ cx25840_write4(client, 0x108, 0x0f040910); /* AUX_PLL_FRAC */ cx25840_write4(client, 0x110, 0xd66bec00); if (state->is_cx25836) break; /* src3/4/6_ctl = 0x08016d59 */ cx25840_write4(client, 0x900, 0x596d0108); cx25840_write4(client, 0x904, 0x596d0108); cx25840_write4(client, 0x90c, 0x596d0108); break; case 48000: /* VID_PLL and AUX_PLL */ cx25840_write4(client, 0x108, 0x0f040a10); /* AUX_PLL_FRAC */ cx25840_write4(client, 0x110, 0xe5d69800); if (state->is_cx25836) break; /* src3/4/6_ctl = 0x08014faa */ cx25840_write4(client, 0x900, 0xaa4f0108); cx25840_write4(client, 0x904, 0xaa4f0108); cx25840_write4(client, 0x90c, 0xaa4f0108); break; } } else { switch (freq) { case 32000: /* VID_PLL and AUX_PLL */ cx25840_write4(client, 0x108, 0x0f04081e); /* AUX_PLL_FRAC */ cx25840_write4(client, 0x110, 0x69082a01); if (state->is_cx25836) break; /* src1_ctl = 0x08010000 */ cx25840_write4(client, 0x8f8, 0x00000108); /* src3/4/6_ctl = 0x08020000 */ cx25840_write4(client, 0x900, 0x00000208); cx25840_write4(client, 0x904, 0x00000208); cx25840_write4(client, 0x90c, 0x00000208); /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x14 */ cx25840_write(client, 0x127, 0x54); break; case 44100: /* VID_PLL and AUX_PLL */ cx25840_write4(client, 0x108, 0x0f040918); /* AUX_PLL_FRAC */ cx25840_write4(client, 0x110, 0xd66bec00); if (state->is_cx25836) break; /* src1_ctl = 0x08010000 */ cx25840_write4(client, 0x8f8, 0xcd600108); /* src3/4/6_ctl = 0x08020000 */ cx25840_write4(client, 0x900, 0x85730108); cx25840_write4(client, 0x904, 0x85730108); cx25840_write4(client, 0x90c, 0x85730108); break; case 48000: /* VID_PLL and AUX_PLL */ cx25840_write4(client, 0x108, 0x0f040a18); /* AUX_PLL_FRAC */ cx25840_write4(client, 0x110, 0xe5d69800); if (state->is_cx25836) break; /* src1_ctl = 0x08010000 */ cx25840_write4(client, 0x8f8, 0x00800108); /* src3/4/6_ctl = 0x08020000 */ cx25840_write4(client, 0x900, 0x55550108); cx25840_write4(client, 0x904, 0x55550108); cx25840_write4(client, 0x90c, 0x55550108); break; } } state->audclk_freq = freq; return 0; }
static int set_audclk_freq(struct i2c_client *client, u32 freq) { struct cx25840_state *state = to_state(i2c_get_clientdata(client)); if (freq != 32000 && freq != 44100 && freq != 48000) return -EINVAL; /* common for all inputs and rates */ /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x10 */ if (!state->is_cx23885 && !state->is_cx231xx) cx25840_write(client, 0x127, 0x50); if (state->aud_input != CX25840_AUDIO_SERIAL) { switch (freq) { case 32000: if (state->is_cx23885) { /* We don't have register values * so avoid destroying registers. */ break; } if (!state->is_cx231xx) { /* VID_PLL and AUX_PLL */ cx25840_write4(client, 0x108, 0x1006040f); /* AUX_PLL_FRAC */ cx25840_write4(client, 0x110, 0x01bb39ee); } if (state->is_cx25836) break; /* src3/4/6_ctl = 0x0801f77f */ cx25840_write4(client, 0x900, 0x0801f77f); cx25840_write4(client, 0x904, 0x0801f77f); cx25840_write4(client, 0x90c, 0x0801f77f); break; case 44100: if (state->is_cx23885) { /* We don't have register values * so avoid destroying registers. */ break; } if (!state->is_cx231xx) { /* VID_PLL and AUX_PLL */ cx25840_write4(client, 0x108, 0x1009040f); /* AUX_PLL_FRAC */ cx25840_write4(client, 0x110, 0x00ec6bd6); } if (state->is_cx25836) break; /* src3/4/6_ctl = 0x08016d59 */ cx25840_write4(client, 0x900, 0x08016d59); cx25840_write4(client, 0x904, 0x08016d59); cx25840_write4(client, 0x90c, 0x08016d59); break; case 48000: if (state->is_cx23885) { /* We don't have register values * so avoid destroying registers. */ break; } if (!state->is_cx231xx) { /* VID_PLL and AUX_PLL */ cx25840_write4(client, 0x108, 0x100a040f); /* AUX_PLL_FRAC */ cx25840_write4(client, 0x110, 0x0098d6e5); } if (state->is_cx25836) break; /* src3/4/6_ctl = 0x08014faa */ cx25840_write4(client, 0x900, 0x08014faa); cx25840_write4(client, 0x904, 0x08014faa); cx25840_write4(client, 0x90c, 0x08014faa); break; } } else { switch (freq) { case 32000: if (state->is_cx23885) { /* We don't have register values * so avoid destroying registers. */ break; } if (!state->is_cx231xx) { /* VID_PLL and AUX_PLL */ cx25840_write4(client, 0x108, 0x1e08040f); /* AUX_PLL_FRAC */ cx25840_write4(client, 0x110, 0x012a0869); } if (state->is_cx25836) break; /* src1_ctl = 0x08010000 */ cx25840_write4(client, 0x8f8, 0x08010000); /* src3/4/6_ctl = 0x08020000 */ cx25840_write4(client, 0x900, 0x08020000); cx25840_write4(client, 0x904, 0x08020000); cx25840_write4(client, 0x90c, 0x08020000); /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x14 */ cx25840_write(client, 0x127, 0x54); break; case 44100: if (state->is_cx23885) { /* We don't have register values * so avoid destroying registers. */ break; } if (!state->is_cx231xx) { /* VID_PLL and AUX_PLL */ cx25840_write4(client, 0x108, 0x1809040f); /* AUX_PLL_FRAC */ cx25840_write4(client, 0x110, 0x00ec6bd6); } if (state->is_cx25836) break; /* src1_ctl = 0x08010000 */ cx25840_write4(client, 0x8f8, 0x080160cd); /* src3/4/6_ctl = 0x08020000 */ cx25840_write4(client, 0x900, 0x08017385); cx25840_write4(client, 0x904, 0x08017385); cx25840_write4(client, 0x90c, 0x08017385); break; case 48000: if (!state->is_cx23885 && !state->is_cx231xx) { /* VID_PLL and AUX_PLL */ cx25840_write4(client, 0x108, 0x180a040f); /* AUX_PLL_FRAC */ cx25840_write4(client, 0x110, 0x0098d6e5); } if (state->is_cx25836) break; if (!state->is_cx23885 && !state->is_cx231xx) { /* src1_ctl */ cx25840_write4(client, 0x8f8, 0x08018000); /* src3/4/6_ctl */ cx25840_write4(client, 0x900, 0x08015555); cx25840_write4(client, 0x904, 0x08015555); cx25840_write4(client, 0x90c, 0x08015555); } else { cx25840_write4(client, 0x8f8, 0x0801867c); cx25840_write4(client, 0x900, 0x08014faa); cx25840_write4(client, 0x904, 0x08014faa); cx25840_write4(client, 0x90c, 0x08014faa); } break; } } state->audclk_freq = freq; return 0; }
static int cx25840_set_audclk_freq(struct i2c_client *client, u32 freq) { struct cx25840_state *state = to_state(i2c_get_clientdata(client)); if (state->aud_input != CX25840_AUDIO_SERIAL) { switch (freq) { case 32000: /* * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 * AUX_PLL Integer = 0x06, AUX PLL Post Divider = 0x10 */ cx25840_write4(client, 0x108, 0x1006040f); /* * VID_PLL Fraction (register 0x10c) = 0x2be2fe * 28636360 * 0xf.15f17f0/4 = 108 MHz * 432 MHz pre-postdivide */ /* * AUX_PLL Fraction = 0x1bb39ee * 28636363 * 0x6.dd9cf70/0x10 = 32000 * 384 * 196.6 MHz pre-postdivide * FIXME < 200 MHz is out of specified valid range * FIXME 28636363 ref_freq doesn't match VID PLL ref */ cx25840_write4(client, 0x110, 0x01bb39ee); /* * SA_MCLK_SEL = 1 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider */ cx25840_write(client, 0x127, 0x50); if (is_cx2583x(state)) break; /* src3/4/6_ctl */ /* 0x1.f77f = (4 * 28636360/8 * 2/455) / 32000 */ cx25840_write4(client, 0x900, 0x0801f77f); cx25840_write4(client, 0x904, 0x0801f77f); cx25840_write4(client, 0x90c, 0x0801f77f); break; case 44100: /* * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 * AUX_PLL Integer = 0x09, AUX PLL Post Divider = 0x10 */ cx25840_write4(client, 0x108, 0x1009040f); /* * VID_PLL Fraction (register 0x10c) = 0x2be2fe * 28636360 * 0xf.15f17f0/4 = 108 MHz * 432 MHz pre-postdivide */ /* * AUX_PLL Fraction = 0x0ec6bd6 * 28636363 * 0x9.7635eb0/0x10 = 44100 * 384 * 271 MHz pre-postdivide * FIXME 28636363 ref_freq doesn't match VID PLL ref */ cx25840_write4(client, 0x110, 0x00ec6bd6); /* * SA_MCLK_SEL = 1 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider */ cx25840_write(client, 0x127, 0x50); if (is_cx2583x(state)) break; /* src3/4/6_ctl */ /* 0x1.6d59 = (4 * 28636360/8 * 2/455) / 44100 */ cx25840_write4(client, 0x900, 0x08016d59); cx25840_write4(client, 0x904, 0x08016d59); cx25840_write4(client, 0x90c, 0x08016d59); break; case 48000: /* * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 * AUX_PLL Integer = 0x0a, AUX PLL Post Divider = 0x10 */ cx25840_write4(client, 0x108, 0x100a040f); /* * VID_PLL Fraction (register 0x10c) = 0x2be2fe * 28636360 * 0xf.15f17f0/4 = 108 MHz * 432 MHz pre-postdivide */ /* * AUX_PLL Fraction = 0x098d6e5 * 28636363 * 0xa.4c6b728/0x10 = 48000 * 384 * 295 MHz pre-postdivide * FIXME 28636363 ref_freq doesn't match VID PLL ref */ cx25840_write4(client, 0x110, 0x0098d6e5); /* * SA_MCLK_SEL = 1 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider */ cx25840_write(client, 0x127, 0x50); if (is_cx2583x(state)) break; /* src3/4/6_ctl */ /* 0x1.4faa = (4 * 28636360/8 * 2/455) / 48000 */ cx25840_write4(client, 0x900, 0x08014faa); cx25840_write4(client, 0x904, 0x08014faa); cx25840_write4(client, 0x90c, 0x08014faa); break; } } else { switch (freq) { case 32000: /* * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 * AUX_PLL Integer = 0x08, AUX PLL Post Divider = 0x1e */ cx25840_write4(client, 0x108, 0x1e08040f); /* * VID_PLL Fraction (register 0x10c) = 0x2be2fe * 28636360 * 0xf.15f17f0/4 = 108 MHz * 432 MHz pre-postdivide */ /* * AUX_PLL Fraction = 0x12a0869 * 28636363 * 0x8.9504348/0x1e = 32000 * 256 * 246 MHz pre-postdivide * FIXME 28636363 ref_freq doesn't match VID PLL ref */ cx25840_write4(client, 0x110, 0x012a0869); /* * SA_MCLK_SEL = 1 * SA_MCLK_DIV = 0x14 = 256/384 * AUX_PLL post dvivider */ cx25840_write(client, 0x127, 0x54); if (is_cx2583x(state)) break; /* src1_ctl */ /* 0x1.0000 = 32000/32000 */ cx25840_write4(client, 0x8f8, 0x08010000); /* src3/4/6_ctl */ /* 0x2.0000 = 2 * (32000/32000) */ cx25840_write4(client, 0x900, 0x08020000); cx25840_write4(client, 0x904, 0x08020000); cx25840_write4(client, 0x90c, 0x08020000); break; case 44100: /* * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 * AUX_PLL Integer = 0x09, AUX PLL Post Divider = 0x18 */ cx25840_write4(client, 0x108, 0x1809040f); /* * VID_PLL Fraction (register 0x10c) = 0x2be2fe * 28636360 * 0xf.15f17f0/4 = 108 MHz * 432 MHz pre-postdivide */ /* * AUX_PLL Fraction = 0x0ec6bd6 * 28636363 * 0x9.7635eb0/0x18 = 44100 * 256 * 271 MHz pre-postdivide * FIXME 28636363 ref_freq doesn't match VID PLL ref */ cx25840_write4(client, 0x110, 0x00ec6bd6); /* * SA_MCLK_SEL = 1 * SA_MCLK_DIV = 0x10 = 256/384 * AUX_PLL post dvivider */ cx25840_write(client, 0x127, 0x50); if (is_cx2583x(state)) break; /* src1_ctl */ /* 0x1.60cd = 44100/32000 */ cx25840_write4(client, 0x8f8, 0x080160cd); /* src3/4/6_ctl */ /* 0x1.7385 = 2 * (32000/44100) */ cx25840_write4(client, 0x900, 0x08017385); cx25840_write4(client, 0x904, 0x08017385); cx25840_write4(client, 0x90c, 0x08017385); break; case 48000: /* * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 * AUX_PLL Integer = 0x0a, AUX PLL Post Divider = 0x18 */ cx25840_write4(client, 0x108, 0x180a040f); /* * VID_PLL Fraction (register 0x10c) = 0x2be2fe * 28636360 * 0xf.15f17f0/4 = 108 MHz * 432 MHz pre-postdivide */ /* * AUX_PLL Fraction = 0x098d6e5 * 28636363 * 0xa.4c6b728/0x18 = 48000 * 256 * 295 MHz pre-postdivide * FIXME 28636363 ref_freq doesn't match VID PLL ref */ cx25840_write4(client, 0x110, 0x0098d6e5); /* * SA_MCLK_SEL = 1 * SA_MCLK_DIV = 0x10 = 256/384 * AUX_PLL post dvivider */ cx25840_write(client, 0x127, 0x50); if (is_cx2583x(state)) break; /* src1_ctl */ /* 0x1.8000 = 48000/32000 */ cx25840_write4(client, 0x8f8, 0x08018000); /* src3/4/6_ctl */ /* 0x1.5555 = 2 * (32000/48000) */ cx25840_write4(client, 0x900, 0x08015555); cx25840_write4(client, 0x904, 0x08015555); cx25840_write4(client, 0x90c, 0x08015555); break; } } state->audclk_freq = freq; return 0; }
int cx25840_loadfw(struct i2c_client *client) { struct cx25840_state *state = to_state(i2c_get_clientdata(client)); const struct firmware *fw = NULL; u8 buffer[FWSEND]; const u8 *ptr; const char *fwname = get_fw_name(client); int size, retval; int MAX_BUF_SIZE = FWSEND; u32 gpio_oe = 0, gpio_da = 0; if (is_cx2388x(state)) { /* Preserve the GPIO OE and output bits */ gpio_oe = cx25840_read(client, 0x160); gpio_da = cx25840_read(client, 0x164); } if (is_cx231xx(state) && MAX_BUF_SIZE > 16) { v4l_err(client, " Firmware download size changed to 16 bytes max length\n"); MAX_BUF_SIZE = 16; /* cx231xx cannot accept more than 16 bytes at a time */ } if (request_firmware(&fw, fwname, FWDEV(client)) != 0) { v4l_err(client, "unable to open firmware %s\n", fwname); return -EINVAL; } start_fw_load(client); buffer[0] = 0x08; buffer[1] = 0x02; size = fw->size; ptr = fw->data; while (size > 0) { int len = min(MAX_BUF_SIZE - 2, size); memcpy(buffer + 2, ptr, len); retval = fw_write(client, buffer, len + 2); if (retval < 0) { release_firmware(fw); return retval; } size -= len; ptr += len; } end_fw_load(client); size = fw->size; release_firmware(fw); if (is_cx2388x(state)) { /* Restore GPIO configuration after f/w load */ cx25840_write(client, 0x160, gpio_oe); cx25840_write(client, 0x164, gpio_da); } return check_fw_load(client, size); }