void analogout_init(dac_t *obj, PinName pin)
{
MBED_ASSERT(obj);
if (g_sys_init == 0) {
system_init();
g_sys_init = 1;
}
struct dac_config config_dac;
struct dac_chan_config config_dac_chan;
uint32_t dacperipheral;
uint32_t ch_index;
dacperipheral = pinmap_find_peripheral(pin, PinMap_DAC);
MBED_ASSERT(dacperipheral != NC);
obj->pin = pin;
obj->dac = dacperipheral;
if (pin == PA02) {
ch_index = 0;
} else if (pin == PA05) {
ch_index = 1;
} else { /*Only 2 pins for DAC*/
return 0;
}
obj->channel = ch_index;
dac_get_config_defaults(&config_dac);
dac_init(&(obj->dac_instance), (Dac *)dacperipheral, &config_dac);
dac_chan_get_config_defaults(&config_dac_chan);
dac_chan_set_config(&(obj->dac_instance), ch_index, &config_dac_chan);
dac_chan_enable(&(obj->dac_instance), ch_index);
dac_enable(&(obj->dac_instance));
}
/**
* \brief Initialize ADC and DAC used to simulate a temperature sensor
*
* DACB is used by the simulation plant to output a temperature reading of the
* oven plate. It is set up to output a voltage on pin B2 which is marked as
* ADC2 on header J2.
*
* ADCA is used in the control step and graphical interface to show the current
* temperature of the oven plate. It is set up to read a voltage on pin A4 which
* is marked as ADC4 on header J2.
*
* ADC2 and ADC4 should be connected together, so that the ADC samples the DAC
* directly.
*/
void main_init_adc_dac(void)
{
struct adc_config adc_conf;
struct adc_channel_config adcch_conf;
struct dac_config dac_conf;
/* Set up the DAC for the simulation to output "real" temperature */
dac_read_configuration(&DACB, &dac_conf);
dac_set_conversion_parameters(&dac_conf, DAC_REF_BANDGAP,
DAC_ADJ_RIGHT);
dac_set_active_channel(&dac_conf, DAC_CH0, 0);
dac_write_configuration(&DACB, &dac_conf);
dac_enable(&DACB);
/* Set up the ADC for the controller to read "real" temperature */
adc_read_configuration(&ADCA, &adc_conf);
adcch_read_configuration(&ADCA, ADC_CH0, &adcch_conf);
adc_set_conversion_parameters(&adc_conf, ADC_SIGN_ON, ADC_RES_12,
ADC_REF_BANDGAP);
adc_set_clock_rate(&adc_conf, 20000UL);
adc_set_conversion_trigger(&adc_conf, ADC_TRIG_MANUAL, 1, 0);
adc_write_configuration(&ADCA, &adc_conf);
adcch_set_input(&adcch_conf, ADCCH_POS_PIN4, ADCCH_NEG_NONE, 1);
adcch_write_configuration(&ADCA, ADC_CH0, &adcch_conf);
adc_enable(&ADCA);
adc_start_conversion(&ADCA, ADC_CH0);
/* Enable pull-down, so an open circuit can be detected */
ioport_set_pin_dir(J2_PIN4, IOPORT_DIR_INPUT);
ioport_set_pin_mode(J2_PIN4, IOPORT_MODE_PULLDOWN);
}
int main(void)
{
system_init();
//! [setup_init]
configure_dac();
configure_dac_channel();
//! [setup_init]
//! [setup_enable]
dac_enable(&dac_instance);
//! [setup_enable]
//! [main]
//! [main_output_var]
uint16_t i = 0;
//! [main_output_var]
//! [main_loop]
while (1) {
//! [main_loop]
//! [main_write]
dac_chan_write(&dac_instance, DAC_CHANNEL_0, i);
//! [main_write]
//! [main_inc_val]
if (++i == 0x3FF) {
i = 0;
}
//! [main_inc_val]
}
//! [main]
}
void analogout_init(dac_t *obj, PinName pin)
{
MBED_ASSERT(obj);
if (g_sys_init == 0) {
system_init();
g_sys_init = 1;
}
struct dac_config config_dac;
struct dac_chan_config config_dac_chan;
uint32_t pos_input;
pos_input = pinmap_find_peripheral(pin, PinMap_DAC);
MBED_ASSERT(pos_input != NC);
obj->dac = DAC_0;
dac_get_config_defaults(&config_dac);
dac_init(&dac_instance, (Dac *)DAC_0, &config_dac);
dac_chan_get_config_defaults(&config_dac_chan);
dac_chan_set_config(&dac_instance, DAC_CHANNEL_0, &config_dac_chan);
dac_chan_enable(&dac_instance, DAC_CHANNEL_0);
dac_enable(&dac_instance);
}
static void dac_setup(void)
{
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO5);
dac_disable(CHANNEL_2);
dac_disable_waveform_generation(CHANNEL_2);
dac_enable(CHANNEL_2);
dac_set_trigger_source(DAC_CR_TSEL2_SW);
}
static void dac_setup(void)
{
gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO5);
dac_disable(CHANNEL_2);
dac_disable_waveform_generation(CHANNEL_2);
dac_enable(CHANNEL_2);
dac_set_trigger_source(DAC_CR_TSEL2_SW);
}
void funcgen_plat_output(int channel, bool enable) {
switch (channel) {
case 1: if (enable) {
dac_enable(CHANNEL_2);
} else {
dac_disable(CHANNEL_2);
}
break;
case 0:
default:
if (enable) {
dac_enable(CHANNEL_1);
} else {
dac_disable(CHANNEL_1);
}
break;
}
}
static int cvbs_set_enable(struct rk_display_device *device, int enable)
{
TVEDBG("%s enable %d\n", __func__, enable);
if (rk3036_tve->enable != enable) {
rk3036_tve->enable = enable;
if (rk3036_tve->suspend)
return 0;
if (enable == 0) {
dac_enable(false);
cvbsformat = -1;
tve_switch_fb(rk3036_tve->mode, 0);
} else if (enable == 1) {
tve_switch_fb(rk3036_tve->mode, 1);
dac_enable(true);
}
}
return 0;
}
/**
* \brief Configure the DAC for calibration
*/
static void configure_dac(void)
{
struct dac_config conf;
dac_read_configuration(&DACB, &conf);
dac_set_conversion_parameters(&conf, DAC_REF_AVCC, DAC_ADJ_RIGHT);
dac_set_active_channel(&conf, DAC_CH0 | DAC_CH1, 0);
dac_write_configuration(&DACB, &conf);
dac_enable(&DACB);
}
/*--------------------------------------------------------------------*/
static void dac_setup(void)
{
/* Enable the DAC clock on APB1 */
rcc_periph_clock_enable(RCC_DAC);
/* Setup the DAC channel 1, with timer 2 as trigger source.
* Assume the DAC has woken up by the time the first transfer occurs */
dac_trigger_enable(CHANNEL_1);
dac_set_trigger_source(DAC_CR_TSEL1_T2);
dac_dma_enable(CHANNEL_1);
dac_enable(CHANNEL_1);
}
static int
cvbs_set_mode(struct rk_display_device *device, struct fb_videomode *mode)
{
int i;
for (i = 0; i < ARRAY_SIZE(rk3036_cvbs_mode); i++) {
if (fb_mode_is_equal(&rk3036_cvbs_mode[i], mode)) {
if (rk3036_tve->mode != &rk3036_cvbs_mode[i]) {
rk3036_tve->mode =
(struct fb_videomode *)&rk3036_cvbs_mode[i];
if (rk3036_tve->enable && !rk3036_tve->suspend)
dac_enable(false);
tve_switch_fb(rk3036_tve->mode, 1);
dac_enable(true);
}
return 0;
}
}
TVEDBG("%s\n", __func__);
return -1;
}
void dac_init(void)
{
rcc_clock_setup_hse_3v3(&hse_8mhz_3v3[CLOCK_3V3_120MHZ]); //nastaveni globalnich hodin
rcc_periph_clock_enable(RCC_GPIOA); //pusteni hodin pro port A
rcc_periph_clock_enable(RCC_DAC); //pusteni hodin pro DAC
gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO4); //pin4 portu A nako analogovy bez pullu/pulldown
dac_disable(CHANNEL_1); //zakazani kanalu 1 DAC
dac_disable_waveform_generation(CHANNEL_1); //bastaveni generovani signalu na kanalu 1 DAC
dac_enable(CHANNEL_1); //Povoleni DAC na kanalu 1
dac_set_trigger_source(DAC_CR_TSEL1_SW); //Triger kanalu 1 nastaven na softwarovy
}
static int
tve_fb_event_notify(struct notifier_block *self,
unsigned long action, void *data)
{
struct fb_event *event = data;
int blank_mode = *((int *)event->data);
if (action == FB_EARLY_EVENT_BLANK) {
switch (blank_mode) {
case FB_BLANK_UNBLANK:
break;
default:
TVEDBG("suspend tve\n");
if (!rk3036_tve->suspend) {
rk3036_tve->suspend = 1;
if (rk3036_tve->enable) {
tve_switch_fb(rk3036_tve->mode, 0);
dac_enable(false);
}
}
break;
}
} else if (action == FB_EVENT_BLANK) {
switch (blank_mode) {
case FB_BLANK_UNBLANK:
TVEDBG("resume tve\n");
if (rk3036_tve->suspend) {
rk3036_tve->suspend = 0;
if (rk3036_tve->enable) {
tve_switch_fb(rk3036_tve->mode, 1);
dac_enable(true);
}
}
break;
default:
break;
}
}
return NOTIFY_OK;
}
/*--------------------------------------------------------------------*/
void dac_setup(void)
{
/* Enable the DAC clock on APB1 */
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_DACEN);
/* Set port PA4 for DAC1 output to 'alternate function'. Output driver mode is irrelevant. */
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO4);
/* Setup the DAC channel 1, with timer 2 as trigger source. Assume the DAC has
woken up by the time the first transfer occurs */
dac_trigger_enable(CHANNEL_1);
dac_set_trigger_source(DAC_CR_TSEL1_T2);
dac_dma_enable(CHANNEL_1);
dac_enable(CHANNEL_1);
}
//! [setup]
void configure_dac(void)
{
//! [setup_config]
struct dac_config config_dac;
//! [setup_config]
//! [setup_config_defaults]
dac_get_config_defaults(&config_dac);
//! [setup_config_defaults]
//! [setup_set_config]
dac_init(&dac_instance, DAC, &config_dac);
//! [setup_set_config]
//! [setup_enable]
dac_enable(&dac_instance);
//! [setup_enable]
}
static void dac_setup(void)
{
/* Enable DAC clock. */
rcc_enable_clock(RCC_DAC);
/* Enable GPIOA clock. */
rcc_enable_clock(RCC_GPIOA);
/* Setup PA4 and PA5 for DAC use. */
gpio_config_analog(GPIO_PA(4, 5));
/* Enable DAC channel1 and channel2. */
dac_enable(DAC_DUAL);
/* Wait tWAKEUP. */
delay_us(DAC_T_WAKEUP);
}
/**
* \brief Initialize the DAC for unit test
*
* Initializes the DAC module used for sending the analog values
* to the AC during test.
*/
static void test_dac_init(void)
{
/* Structures for DAC configuration */
struct dac_config config;
struct dac_chan_config chan_config;
/* Configure the DAC module */
dac_get_config_defaults(&config);
dac_init(&dac_inst, DAC, &config);
/* Configure the DAC channel */
dac_chan_get_config_defaults(&chan_config);
dac_chan_set_config(&dac_inst, DAC_CHANNEL_0, &chan_config);
dac_chan_enable(&dac_inst, DAC_CHANNEL_0);
dac_enable(&dac_inst);
}
/**
* \brief Initialize the DAC for unit test
*
* Initializes the DAC module used for sending the analog values
* to the ADC during test.
*/
static void test_dac_init(void)
{
/* Structures for DAC configuration */
struct dac_config config;
struct dac_chan_config chan_config;
/* Configure the DAC module */
dac_get_config_defaults(&config);
config.reference = DAC_REFERENCE_INT1V;
config.clock_source = GCLK_GENERATOR_3;
dac_init(&dac_inst, DAC, &config);
dac_enable(&dac_inst);
/* Configure the DAC channel */
dac_chan_get_config_defaults(&chan_config);
dac_chan_set_config(&dac_inst, DAC_CHANNEL_0, &chan_config);
dac_chan_enable(&dac_inst, DAC_CHANNEL_0);
}
void funcgen_plat_dac_setup(int channel) {
/* Setup the DAC channel 1, with timer 2 as trigger source.
* Assume the DAC has woken up by the time the first transfer occurs */
int chan;
switch (channel) {
case 1: dac_set_trigger_source(DAC_CR_TSEL2_T7);
chan = CHANNEL_2;
break;
default:
case 0:
dac_set_trigger_source(DAC_CR_TSEL1_T6);
chan = CHANNEL_1;
break;
}
dac_trigger_enable(chan);
dac_dma_enable(chan);
dac_enable(chan);
}
/**
* \brief Initializes the DAC
*/
static void main_dac_init(void)
{
/* DAC module configuration structure */
struct dac_config dac_conf;
/* Create configuration:
* - AVCC as reference
* - right adjusted channel value
* - both DAC channels active on :
* - DAC0 (PA2 pin) for ADC V+
* - DAC1 (PA3 pin) for ADC V-
* - manually triggered conversions on both channels
*/
dac_read_configuration(&DACA, &dac_conf);
dac_set_conversion_parameters(&dac_conf, DAC_REF_AVCC, DAC_ADJ_RIGHT);
dac_set_active_channel(&dac_conf, DAC_CH0 | DAC_CH1, 0);
dac_set_conversion_trigger(&dac_conf, 0, 0);
dac_write_configuration(&DACA, &dac_conf);
dac_enable(&DACA);
}
void comms_init(void)
{
cdcRxChar = false;
// Start the internal UARTS
gps_uart_init();
ntx2b_uart_init();
ext_uart_init();
// Start the DAC
dac_enable(&MY_DAC);
dac_init();
// Initialise the NTX2B Modulation
ntx2b_mod_enable(RTTY300);
}
/**
* \brief Run all Class B tests
*
* Destructively test ADC and DAC; modules must be reinitialized for application
* use. Then test the SRAM, CPU registers and CRC of Flash (if enabled).
*/
void oven_classb_run_tests(void)
{
oven_ui_set_status_leds(S_ORANGE); /* Tests started */
/* Test the DAC and ADC used in this application */
dac_enable(&DACB);
adc_enable(&ADCA);
classb_analog_io_test(&DACB, &ADCA);
/* Disable interrupts globally. Normally one would disable
* this also for the analog test, but to emulate an error
* we allow interrupts during the analog test.
*/
cli();
for (uint8_t i = 0; i < CLASSB_NSECS; ++i) {
classb_sram_test();
}
/* Test the register file */
classb_register_test();
/* Test CRC Checksum */
/* Uncomment the code below and set a breakpoint on it, then press
* F10/Step over to read the calculated checksum. Insert the value in
* classb_precalculated_flash_crc at the top of this file and recompile
* to get a working CRC check.
*/
/* checksum_test_flash = CLASSB_CRC32_Flash_HW (CRC_APP, 0, 0,
* &classb_precalculated_flash_crc);
*/
sei();
/* Update status LED according to test results */
if (classb_error == CLASSB_ERROR_NONE) {
oven_ui_set_status_leds(S_GREEN);
} else {
oven_ui_set_status_leds(S_RED);
}
}
int main(void)
{
uint32_t msize;
uint32_t rsize;
#ifdef DAC_USE_VREF
vref_setup();
#endif /* DAC_USE_VREF */
dac_setup();
dac_enable();
serial_setup();
msize = 0;
while (1)
{
rsize = serial_get_rsize();
if (rsize > (sizeof(pload_msg) - msize)) rsize = sizeof(pload_msg) - msize;
if (rsize == 0) continue ;
/* stop the generator if active */
if (pload_flags & PLOAD_FLAG_IS_STARTED)
{
#if 0 /* DEBUG */
SERIAL_WRITE_STRING("stopping\r\n");
#endif /* DEBUG */
pload_flags &= ~PLOAD_FLAG_IS_STARTED;
pit_stop(1);
}
serial_read((uint8_t*)&pload_msg + msize, rsize);
msize += rsize;
if (msize != sizeof(pload_msg)) continue ;
/* new message */
msize = 0;
if (pload_msg.op != PLOAD_MSG_OP_SET_STEPS) continue ;
/* start the generator */
if ((pload_flags & PLOAD_FLAG_IS_STARTED) == 0)
{
#if 0 /* DEBUG */
SERIAL_WRITE_STRING("starting\r\n");
#endif /* DEBUG */
pload_step_index = 0;
pload_tick_count = (uint32_t)pload_msg.u.steps.arg1[0];
pload_repeat_index = 0;
pload_current = (int32_t)pload_msg.u.steps.arg0[0];
dac_set(ma_to_dac((uint32_t)pload_current));
#if 0 /* DEBUG */
SERIAL_WRITE_STRING("dac_set:");
serial_write(uint32_to_string((uint32_t)pload_current), 8);
SERIAL_WRITE_STRING("\r\n");
#endif /* DEBUG */
pload_flags |= PLOAD_FLAG_IS_STARTED;
pit_start(1, F_BUS / PLOAD_CLOCK_FREQ);
}
}
return 0;
}
/**
* \internal
* \brief Test single ended conversion in 8-bit mode using the DAC
*
* This tests output three different values on the two DAC channels:
* - 0 (output analog value is greater than 0, as the DAC cannot go that low)
* - 1/2 * \ref DAC_MAX Half of the maximum value of the DAC
* - \ref DAC_MAX The maximum value (VREF) of the DAC.
*
* These values are then measured using the ADC on the pins that are connected
* to the DAC channel, using all available ADC channels and the results are
* compared and checked to see if they are within the acceptable range of
* values that passes the test.
*
* \param test Current test case.
*/
static void run_single_ended_8bit_conversion_test(
const struct test_case *test)
{
// Number of MUX inputs that are to be read
const uint8_t num_inputs = 4;
/* Connection between DAC outputs and ADC MUX inputs
* input 0, 2, 4, 6 is connected to DACA0
* input 1, 3, 5, 7 is connected to DACA1.
*/
const uint8_t channelgroup[2][4] = {{0, 2, 4, 6}, {1, 3, 5, 7}};
uint8_t dac_channel;
uint8_t adc_channel;
uint8_t mux_index;
uint16_t results[4];
struct dac_config dac_conf;
struct adc_config adc_conf;
// Configure ADC
adc_read_configuration(&ADCA, &adc_conf);
adc_set_conversion_parameters(&adc_conf, ADC_SIGN_OFF, ADC_RES_8,
ADC_REF_BANDGAP);
adc_set_clock_rate(&adc_conf, 2000UL);
adc_set_conversion_trigger(&adc_conf, ADC_TRIG_MANUAL, 1, 0);
adc_write_configuration(&ADCA, &adc_conf);
// Configure DAC
dac_read_configuration(&DACA, &dac_conf);
dac_set_conversion_parameters(&dac_conf, DAC_REF_BANDGAP, DAC_ADJ_RIGHT);
dac_set_active_channel(&dac_conf, DAC_CH0 | DAC_CH1, 0);
dac_set_conversion_trigger(&dac_conf, 0, 0);
dac_set_conversion_interval(&dac_conf, 10);
dac_set_refresh_interval(&dac_conf, 20);
dac_write_configuration(&DACA, &dac_conf);
dac_enable(&DACA);
// Set outputs as zero
dac_wait_for_channel_ready(&DACA, DAC_CH0 | DAC_CH1);
dac_set_channel_value(&DACA, DAC_CH0, DAC_MIN);
dac_set_channel_value(&DACA, DAC_CH1, DAC_MIN);
for(dac_channel = 0; dac_channel < 2; dac_channel++) {
/* Read all ADC pins connected to active DAC output.
* All channels are converted NUM_SAMPLES times and the
* final value used for the assert is an average.
*/
for (adc_channel = 0; adc_channel < NUM_CHANNELS;
adc_channel++) {
single_ended_unsigned_average(&ADCA, 1 << adc_channel,
(uint8_t *)&channelgroup[dac_channel],
num_inputs, results);
for (mux_index = 0; mux_index < num_inputs;
mux_index++) {
verify_unsigned_result(test,
ADC_ZERO,
results[mux_index],
dac_channel,
adc_channel,
channelgroup[dac_channel]
[mux_index],
ADC_UNSIGNED_8BIT_MAX, false);
}
}
}
// Set outputs as 1/2 * MAX_VALUE
dac_wait_for_channel_ready(&DACA, DAC_CH0 | DAC_CH1);
dac_set_channel_value(&DACA, DAC_CH0, DAC_MAX / 2);
dac_set_channel_value(&DACA, DAC_CH1, DAC_MAX / 2);
for(dac_channel = 0; dac_channel < 2; dac_channel++) {
/* Read all ADC pins connected to active DAC output.
* All channels are converted NUM_SAMPLES times and the
* final value used for the assert is an average.
*/
for (adc_channel = 0; adc_channel < NUM_CHANNELS;
adc_channel++) {
single_ended_unsigned_average(&ADCA, 1 << adc_channel,
(uint8_t *)&channelgroup[dac_channel],
num_inputs, results);
for (mux_index = 0; mux_index < num_inputs;
mux_index++) {
verify_unsigned_result(test,
ADC_UNSIGNED_8BIT_MAX / 2,
results[mux_index],
dac_channel,
adc_channel,
channelgroup[dac_channel]
[mux_index],
ADC_UNSIGNED_8BIT_MAX, false);
}
}
}
// Set outputs as MAX_VALUE
dac_wait_for_channel_ready(&DACA, DAC_CH0 | DAC_CH1);
dac_set_channel_value(&DACA, DAC_CH0, DAC_MAX);
dac_set_channel_value(&DACA, DAC_CH1, DAC_MAX);
for(dac_channel = 0; dac_channel < 2; dac_channel++) {
/* Read all ADC pins connected to active DAC output.
* All channels are converted NUM_SAMPLES times and the
* final value used for the assert is an average.
*/
for (adc_channel = 0; adc_channel < NUM_CHANNELS;
adc_channel++) {
single_ended_unsigned_average(&ADCA, 1 << adc_channel,
(uint8_t *)&channelgroup[dac_channel],
num_inputs, results);
for (mux_index = 0; mux_index < num_inputs;
mux_index++) {
verify_unsigned_result(test,
ADC_UNSIGNED_8BIT_MAX,
results[mux_index],
dac_channel,
adc_channel,
channelgroup[dac_channel]
[mux_index],
ADC_UNSIGNED_8BIT_MAX, false);
}
}
}
}
int main(void)
{
struct dac_config conf;
uint8_t i = 0;
board_init();
sysclk_init();
// Initialize the dac configuration.
dac_read_configuration(&SPEAKER_DAC, &conf);
/* Create configuration:
* - 1V from bandgap as reference, left adjusted channel value
* - one active DAC channel, no internal output
* - conversions triggered by event channel 0
* - 1 us conversion intervals
*/
dac_set_conversion_parameters(&conf, DAC_REF_BANDGAP, DAC_ADJ_LEFT);
dac_set_active_channel(&conf, SPEAKER_DAC_CHANNEL, 0);
dac_set_conversion_trigger(&conf, SPEAKER_DAC_CHANNEL, 0);
#if XMEGA_DAC_VERSION_1
dac_set_conversion_interval(&conf, 1);
#endif
dac_write_configuration(&SPEAKER_DAC, &conf);
dac_enable(&SPEAKER_DAC);
#if XMEGA_E
// Configure timer/counter to generate events at sample rate.
sysclk_enable_module(SYSCLK_PORT_C, SYSCLK_TC4);
TCC4.PER = (sysclk_get_per_hz() / RATE_OF_CONVERSION) - 1;
// Configure event channel 0 to generate events upon T/C overflow.
sysclk_enable_module(SYSCLK_PORT_GEN, SYSCLK_EVSYS);
EVSYS.CH0MUX = EVSYS_CHMUX_TCC4_OVF_gc;
// Start the timer/counter.
TCC4.CTRLA = TC45_CLKSEL_DIV1_gc;
#else
// Configure timer/counter to generate events at sample rate.
sysclk_enable_module(SYSCLK_PORT_C, SYSCLK_TC0);
TCC0.PER = (sysclk_get_per_hz() / RATE_OF_CONVERSION) - 1;
// Configure event channel 0 to generate events upon T/C overflow.
sysclk_enable_module(SYSCLK_PORT_GEN, SYSCLK_EVSYS);
EVSYS.CH0MUX = EVSYS_CHMUX_TCC0_OVF_gc;
// Start the timer/counter.
TCC0.CTRLA = TC_CLKSEL_DIV1_gc;
#endif
/* Write samples to the DAC channel every time it is ready for new
* data, i.e., when it is done converting. Conversions are triggered by
* the timer/counter.
*/
do {
dac_wait_for_channel_ready(&SPEAKER_DAC, SPEAKER_DAC_CHANNEL);
dac_set_channel_value(&SPEAKER_DAC, SPEAKER_DAC_CHANNEL, sine[i]);
i++;
i %= NR_OF_SAMPLES;
} while (1);
}
/**
* \internal
* \brief Test differential conversion in 12-bit mode using the DAC
*
* This tests output three different values on the two DAC channels:
* - 1/2 * \ref DAC_MAX on both outputs to get a differential zero
* - \ref DAC_MAX on positive and \ref DAC_MIN on negative to get max positive
* result
* - \ref DAC_MIN on positive and \ref DAC_MAX on negative to get max negative
* result
*
* These values are then measured using the ADC on the pins that are connected
* to the DAC channel, and the results are compared and checked to see if they
* are within the acceptable range of values that passes the test.
*
* \param test Current test case.
*/
static void run_differential_12bit_conversion_test(
const struct test_case *test)
{
// Number of MUX inputs that are to be read
const uint8_t num_inputs = 4;
/* Connection between DAC outputs and ADC MUX inputs
* input 0, 2, 4, 6 is connected to DACA0
* input 1, 3, 5, 7 is connected to DACA1.
*/
const uint8_t channel_pos[] = {0, 2, 4, 6};
const uint8_t channel_neg[] = {1, 3, 5, 7};
uint8_t adc_channel;
uint8_t mux_index;
int16_t results[4];
struct dac_config dac_conf;
struct adc_config adc_conf;
// Configure ADC
adc_read_configuration(&ADCA, &adc_conf);
adc_set_conversion_parameters(&adc_conf, ADC_SIGN_ON, ADC_RES_12,
ADC_REF_BANDGAP);
adc_set_clock_rate(&adc_conf, 2000UL);
adc_set_conversion_trigger(&adc_conf, ADC_TRIG_MANUAL, 1, 0);
adc_write_configuration(&ADCA, &adc_conf);
// Configure DAC
dac_read_configuration(&DACA, &dac_conf);
dac_set_conversion_parameters(&dac_conf, DAC_REF_BANDGAP,
DAC_ADJ_RIGHT);
dac_set_active_channel(&dac_conf, DAC_CH0 | DAC_CH1, 0);
dac_set_conversion_trigger(&dac_conf, 0, 0);
dac_set_conversion_interval(&dac_conf, 10);
dac_set_refresh_interval(&dac_conf, 20);
dac_write_configuration(&DACA, &dac_conf);
dac_enable(&DACA);
// Set outputs to same (1/2 * MAX_VALUE) to get zero
dac_wait_for_channel_ready(&DACA, DAC_CH0 | DAC_CH1);
dac_set_channel_value(&DACA, DAC_CH0, DAC_MAX / 2);
dac_set_channel_value(&DACA, DAC_CH1, DAC_MAX / 2);
/* Read all ADC pins connected to active DAC output.
* All channels are converted NUM_SAMPLES times and the
* final value used for the assert is an average.
*/
for (adc_channel = 0; adc_channel < NUM_CHANNELS; adc_channel++) {
differential_signed_average(&ADCA, 1 << adc_channel,
channel_pos, channel_neg, num_inputs, results,
1);
for (mux_index = 0; mux_index < num_inputs; mux_index++) {
verify_signed_result(test, ADC_ZERO,
results[mux_index], adc_channel,
channel_pos[mux_index],
channel_neg[mux_index],
ADC_SIGNED_12BIT_MIN,
ADC_SIGNED_12BIT_MAX, 1, true);
}
}
// Set output to max positive range for positive result
dac_wait_for_channel_ready(&DACA, DAC_CH0 | DAC_CH1);
dac_set_channel_value(&DACA, DAC_CH0, DAC_MAX);
dac_set_channel_value(&DACA, DAC_CH1, DAC_MIN);
/* Read all ADC pins connected to active DAC output.
* All channels are converted NUM_SAMPLES times and the
* final value used for the assert is an average.
*/
for (adc_channel = 0; adc_channel < NUM_CHANNELS; adc_channel++) {
differential_signed_average(&ADCA, 1 << adc_channel,
channel_pos, channel_neg, num_inputs, results,
1);
for (mux_index = 0; mux_index < num_inputs; mux_index++) {
verify_signed_result(test, ADC_SIGNED_12BIT_MAX,
results[mux_index], adc_channel,
channel_pos[mux_index],
channel_neg[mux_index],
ADC_SIGNED_12BIT_MIN,
ADC_SIGNED_12BIT_MAX, 1, true);
}
}
// Set output to max negative range for negative result
dac_wait_for_channel_ready(&DACA, DAC_CH0 | DAC_CH1);
dac_set_channel_value(&DACA, DAC_CH0, DAC_MIN);
dac_set_channel_value(&DACA, DAC_CH1, DAC_MAX);
/* Read all ADC pins connected to active DAC output.
* All channels are converted NUM_SAMPLES times and the
* final value used for the assert is an average.
*/
for (adc_channel = 0; adc_channel < NUM_CHANNELS; adc_channel++) {
differential_signed_average(&ADCA, 1 << adc_channel,
channel_pos, channel_neg, num_inputs, results,
1);
for (mux_index = 0; mux_index < num_inputs; mux_index++) {
verify_signed_result(test, ADC_SIGNED_12BIT_MIN,
results[mux_index], adc_channel,
channel_pos[mux_index],
channel_neg[mux_index],
ADC_SIGNED_12BIT_MIN,
ADC_SIGNED_12BIT_MAX, 1, true);
}
}
}
//! [setup_dac]
void configure_dac(void)
{
//! [setup_dac_config]
struct dac_config config_dac;
//! [setup_dac_config]
//! [setup_dac_config_default]
dac_get_config_defaults(&config_dac);
//! [setup_dac_config_default]
//! [setup_dac_start_on_event]
#if (SAML21)
dac_instance.start_on_event[DAC_CHANNEL_0] = true;
#else
dac_instance.start_on_event = true;
#endif
//! [setup_dac_start_on_event]
//! [setup_dac_instance]
dac_init(&dac_instance, DAC, &config_dac);
//! [setup_dac_instance]
//! [setup_dac_on_event_start_conversion]
struct dac_events events =
#if (SAML21)
{ .on_event_chan0_start_conversion = true };
#else
{ .on_event_start_conversion = true };
#endif
//! [setup_dac_on_event_start_conversion]
//! [enable_dac_event]
dac_enable_events(&dac_instance, &events);
//! [enable_dac_event]
}
//! [setup_dac]
//! [setup_dac_channel]
void configure_dac_channel(void)
{
//! [setup_dac_chan_config]
struct dac_chan_config config_dac_chan;
//! [setup_dac_chan_config]
//! [setup_dac_chan_config_default]
dac_chan_get_config_defaults(&config_dac_chan);
//! [setup_dac_chan_config_default]
//! [set_dac_chan_config]
dac_chan_set_config(&dac_instance, DAC_CHANNEL_0,
&config_dac_chan);
//! [set_dac_chan_config]
//! [enable_dac_channel]
dac_chan_enable(&dac_instance, DAC_CHANNEL_0);
//! [enable_dac_channel]
}
//! [setup_dac_channel]
int main(void)
{
//! [data_length_var]
uint32_t i;
//! [data_length_var]
system_init();
//! [setup_init]
//! [init_rtc]
configure_rtc_count();
//! [init_rtc]
//! [set_rtc_period]
rtc_count_set_period(&rtc_instance, 1);
//! [set_rtc_period]
//! [init_dac]
configure_dac();
//! [init_dac]
//! [init_dac_chan]
configure_dac_channel();
//! [init_dac_chan]
//! [enable_dac]
dac_enable(&dac_instance);
//! [enable_dac]
//! [init_event_resource]
configure_event_resource();
//! [init_event_resource]
//! [register_dac_callback]
dac_register_callback(&dac_instance, DAC_CHANNEL_0,
dac_callback,DAC_CALLBACK_TRANSFER_COMPLETE);
//! [register_dac_callback]
//! [enable_dac_callback]
dac_chan_enable_callback(&dac_instance, DAC_CHANNEL_0,
DAC_CALLBACK_TRANSFER_COMPLETE);
//! [enable_dac_callback]
//! [setup_dac_data]
for (i = 0;i < DATA_LENGTH;i++) {
dac_data[i] = 0xfff * i;
}
//! [setup_dac_data]
//! [setup_init]
//! [main_start]
//! [main_write]
dac_chan_write_buffer_job(&dac_instance, DAC_CHANNEL_0,
dac_data, DATA_LENGTH);
//! [main_write]
//! [main_check_transfer_done]
while (!transfer_is_done) {
/* Wait for transfer done */
}
//! [main_check_transfer_done]
//! [main_loop]
while (1) {
}
//! [main_loop]
//! [main_start]
}
/**
* \internal
* \brief Test differential conversion with gain in 12-bit mode using the DAC
*
* This test outputs a gain compensated level on DAC output that should result
* in a value of half maximum positive value on the ADC.
*
* These values are then measured using the ADC on the pins that are connected
* to the DAC channel, and the results are compared and checked to see if they
* are within the acceptable range of values that passes the test.
*
* \param test Current test case.
*/
static void run_differential_12bit_with_gain_conversion_test(
const struct test_case *test)
{
// Number of MUX inputs that are to be read
const uint8_t num_inputs = 2;
/* Connection between DAC outputs and ADC MUX inputs.
* Only the high nibble on PORTA is possible for gain.
* input 4, 6 is connected to DACA0
* input 5, 7 is connected to DACA1.
*/
const uint8_t channel_pos[] = {4, 6};
const uint8_t channel_neg[] = {5, 7};
/*
* Go through gain level up to 8, since any higher gives too much
* propagated error for sensible unit test limits.
*/
const uint8_t gain[] = {1, 2, 4, 8};
uint8_t gain_index;
uint8_t adc_channel;
uint8_t mux_index;
int16_t results[2];
struct dac_config dac_conf;
struct adc_config adc_conf;
// Configure ADC
adc_read_configuration(&ADCA, &adc_conf);
adc_set_conversion_parameters(&adc_conf, ADC_SIGN_ON, ADC_RES_12,
ADC_REF_BANDGAP);
adc_set_clock_rate(&adc_conf, 2000UL);
adc_set_conversion_trigger(&adc_conf, ADC_TRIG_MANUAL, 1, 0);
adc_write_configuration(&ADCA, &adc_conf);
// Configure DAC
dac_read_configuration(&DACA, &dac_conf);
dac_set_conversion_parameters(&dac_conf, DAC_REF_BANDGAP,
DAC_ADJ_RIGHT);
dac_set_active_channel(&dac_conf, DAC_CH0 | DAC_CH1, 0);
dac_set_conversion_trigger(&dac_conf, 0, 0);
dac_set_conversion_interval(&dac_conf, 10);
dac_set_refresh_interval(&dac_conf, 20);
dac_write_configuration(&DACA, &dac_conf);
dac_enable(&DACA);
// Set negative output to zero
dac_wait_for_channel_ready(&DACA, DAC_CH1);
dac_set_channel_value(&DACA, DAC_CH1, DAC_MIN);
for (gain_index = 0; gain_index < sizeof(gain); gain_index++) {
// Set positive output to half positive range adjusted to gain
dac_wait_for_channel_ready(&DACA, DAC_CH0);
dac_set_channel_value(&DACA, DAC_CH0, DAC_MAX /
(gain[gain_index] * 2));
/* Read all ADC pins connected to active DAC output.
* All channels are converted NUM_SAMPLES times and the
* final value used for the assert is an average.
*/
for (adc_channel = 0; adc_channel < NUM_CHANNELS;
adc_channel++) {
differential_signed_average(&ADCA, 1 << adc_channel,
channel_pos, channel_neg, num_inputs,
results, gain[gain_index]);
for (mux_index = 0; mux_index < num_inputs;
mux_index++) {
verify_signed_result(test,
ADC_SIGNED_12BIT_MAX / 2,
results[mux_index],
adc_channel,
channel_pos[mux_index],
channel_neg[mux_index],
ADC_SIGNED_12BIT_MIN,
ADC_SIGNED_12BIT_MAX,
gain[gain_index], true);
}
}
}
}
/**
* \brief Configures the DAC in event triggered mode.
*
* Configures the DAC to use the module's default configuration, with output
* channel mode configured for event triggered conversions.
*
* \param dev_inst Pointer to the DAC module software instance to initialize
*/
static void configure_dac(struct dac_module *dac_module)
{
struct dac_config config;
struct dac_chan_config channel_config;
/* Get the DAC default configuration */
dac_get_config_defaults(&config);
/* Switch to GCLK generator 0 */
config.clock_source = GCLK_GENERATOR_0;
dac_init(dac_module, DAC, &config);
/* Get the default DAC channel config */
dac_chan_get_config_defaults(&channel_config);
/* Set the channel configuration, and enable it */
dac_chan_set_config(dac_module, DAC_CHANNEL_0, &channel_config);
dac_chan_enable(dac_module, DAC_CHANNEL_0);
/* Enable event triggered conversions */
struct dac_events events = { .on_event_start_conversion = true };
dac_enable_events(dac_module, &events);
dac_enable(dac_module);
}
/**
* \brief Configures the TC to generate output events at the sample frequency.
*
* Configures the TC in Frequency Generation mode, with an event output once
* each time the audio sample frequency period expires.
*
* \param dev_inst Pointer to the TC module software instance to initialize
*/
static void configure_tc(struct tc_module *tc_module)
{
struct tc_config config;
tc_get_config_defaults(&config);
config.clock_source = GCLK_GENERATOR_0;
config.wave_generation = TC_WAVE_GENERATION_MATCH_FREQ;
tc_init(tc_module, TC3, &config);
/* Enable periodic event output generation */
struct tc_events events = { .generate_event_on_overflow = true };
tc_enable_events(tc_module, &events);
/* Set the timer top value to alter the overflow frequency */
tc_set_top_value(tc_module,
system_gclk_gen_get_hz(GCLK_GENERATOR_0) / sample_rate);
tc_enable(tc_module);
}
/**
* \brief Configures the event system to link the sample timer to the DAC.
*
* Configures the event system, linking the TC module used for the audio sample
* rate timing to the DAC, so that a new conversion is triggered each time the
* DAC receives an event from the timer.
*/
static void configure_events(struct events_resource *event)
{
struct events_config config;
events_get_config_defaults(&config);
config.generator = EVSYS_ID_GEN_TC3_OVF;
config.path = EVENTS_PATH_ASYNCHRONOUS;
events_allocate(event, &config);
events_attach_user(event, EVSYS_ID_USER_DAC_START);
}
/**
* \brief Main application routine
*/
int main(void)
{
struct dac_module dac_module;
struct tc_module tc_module;
struct events_resource event;
/* Initialize all the system clocks, pm, gclk... */
system_init();
/* Enable the internal bandgap to use as reference to the DAC */
system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_BANDGAP);
/* Module configuration */
configure_tc(&tc_module);
configure_dac(&dac_module);
configure_events(&event);
/* Start the sample trigger timer */
tc_start_counter(&tc_module);
while (true) {
while (port_pin_get_input_level(SW0_PIN) == SW0_INACTIVE) {
/* Wait for the button to be pressed */
}
port_pin_toggle_output_level(LED0_PIN);
for (uint32_t i = 0; i < number_of_samples; i++) {
dac_chan_write(&dac_module, DAC_CHANNEL_0, wav_samples[i]);
while (!(DAC->INTFLAG.reg & DAC_INTFLAG_EMPTY)) {
/* Wait for data buffer to be empty */
}
}
while (port_pin_get_input_level(SW0_PIN) == SW0_ACTIVE) {
/* Wait for the button to be depressed */
}
}
}
int rk3036_tve_init(vidinfo_t *panel)
{
int val = 0;
int node = 0;
#if defined(CONFIG_RKCHIP_RK3036)
tve_s.reg_phy_base = 0x10118000 + 0x200;
tve_s.soctype = SOC_RK3036;
// printf("%s start soc is 3036\n", __func__);
#elif defined(CONFIG_RKCHIP_RK3128)
tve_s.reg_phy_base = 0x1010e000 + 0x200;
tve_s.soctype = SOC_RK312X;
tve_s.saturation = 0;
if (gd->fdt_blob)
{
node = fdt_node_offset_by_compatible(gd->fdt_blob,
0, "rockchip,rk312x-tve");
if (node < 0) {
printf("can't find dts node for rk312x-tve\n");
return -ENODEV;
}
if (!fdt_device_is_available(gd->fdt_blob, node)) {
printf("rk312x-tve is disabled\n");
return -EPERM;
}
tve_s.test_mode = fdtdec_get_int(gd->fdt_blob, node, "test_mode", 0);
tve_s.saturation = fdtdec_get_int(gd->fdt_blob, node, "saturation", 0);
}
printf("test_mode=%d,saturation=0x%x\n", tve_s.test_mode, tve_s.saturation);
// printf("%s start soc is 3128\n", __func__);
#endif
rk3036_tve_init_panel(panel);
if(g_tve_pos < 0)
{
g_tve_pos = TVOUT_DEAULT;
printf("%s:use default config g_tve_pos = %d \n", __func__,g_tve_pos);
}
else
{
printf("%s:use baseparamer config g_tve_pos = %d \n", __func__,g_tve_pos);
}
if(g_tve_pos < 0)
{
g_tve_pos = TVOUT_DEAULT;
printf("%s:use default config g_tve_pos = %d \n", __func__,g_tve_pos);
}
else
{
printf("%s:use baseparamer config g_tve_pos = %d \n", __func__,g_tve_pos);
}
dac_enable(0);
tve_set_mode(g_tve_pos);
dac_enable(1);
// rk3036_tve_show_reg();
}
