static void dce110_stream_encoder_set_mst_bandwidth( struct stream_encoder *enc, struct fixed31_32 avg_time_slots_per_mtp) { struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); uint32_t x = dal_fixed31_32_floor( avg_time_slots_per_mtp); uint32_t y = dal_fixed31_32_ceil( dal_fixed31_32_shl( dal_fixed31_32_sub_int( avg_time_slots_per_mtp, x), 26)); { REG_SET_2(DP_MSE_RATE_CNTL, 0, DP_MSE_RATE_X, x, DP_MSE_RATE_Y, y); } /* wait for update to be completed on the link */ /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */ /* is reset to 0 (not pending) */ REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, 0, 10, DP_MST_UPDATE_MAX_RETRY); }
void dce80_stream_encoder_set_mst_bandwidth( struct stream_encoder *enc, struct fixed31_32 avg_time_slots_per_mtp) { struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); struct dc_context *ctx = enc110->base.ctx; uint32_t addr; uint32_t field; uint32_t value; uint32_t retries = 0; uint32_t x = dal_fixed31_32_floor( avg_time_slots_per_mtp); uint32_t y = dal_fixed31_32_ceil( dal_fixed31_32_shl( dal_fixed31_32_sub_int( avg_time_slots_per_mtp, x), 26)); { addr = LINK_REG(DP_MSE_RATE_CNTL); value = dm_read_reg(ctx, addr); set_reg_field_value( value, x, DP_MSE_RATE_CNTL, DP_MSE_RATE_X); set_reg_field_value( value, y, DP_MSE_RATE_CNTL, DP_MSE_RATE_Y); dm_write_reg(ctx, addr, value); } /* wait for update to be completed on the link */ /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */ /* is reset to 0 (not pending) */ { addr = LINK_REG(DP_MSE_RATE_UPDATE); do { value = dm_read_reg(ctx, addr); field = get_reg_field_value( value, DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING); if (!(field & DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK)) break; udelay(10); ++retries; } while (retries < DP_MST_UPDATE_MAX_RETRY); } }