static void construct(
	struct i2c_hw_engine_dce110 *hw_engine,
	const struct i2c_hw_engine_dce110_create_arg *arg)
{
	uint32_t xtal_ref_div = 0;

	dal_i2c_hw_engine_construct(&hw_engine->base, arg->ctx);

	hw_engine->base.base.base.funcs = &engine_funcs;
	hw_engine->base.base.funcs = &i2c_engine_funcs;
	hw_engine->base.funcs = &i2c_hw_engine_funcs;
	hw_engine->base.default_speed = arg->default_speed;

	hw_engine->regs = arg->regs;
	hw_engine->i2c_shift = arg->i2c_shift;
	hw_engine->i2c_mask = arg->i2c_mask;

	hw_engine->engine_id = arg->engine_id;

	hw_engine->buffer_used_bytes = 0;
	hw_engine->transaction_count = 0;
	hw_engine->engine_keep_power_up_count = 1;


	REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, &xtal_ref_div);

	if (xtal_ref_div == 0) {
		DC_LOG_WARNING("Invalid base timer divider [%s]\n",
				__func__);
		xtal_ref_div = 2;
	}

	/*Calculating Reference Clock by divding original frequency by
	 * XTAL_REF_DIV.
	 * At upper level, uint32_t reference_frequency =
	 *  dal_i2caux_get_reference_clock(as) >> 1
	 *  which already divided by 2. So we need x2 to get original
	 *  reference clock from ppll_info
	 */
	hw_engine->reference_frequency =
		(arg->reference_frequency * 2) / xtal_ref_div;
}
static bool construct(
	struct i2c_hw_engine_dce110 *engine_dce110,
	const struct i2c_hw_engine_dce110_create_arg *arg)
{
	uint32_t xtal_ref_div = 0;
	uint32_t value = 0;

	/*ddc_setup_offset of dce80 and dce110 have the same register name
	 * but different offset. Do not need different array*/
	if (arg->engine_id >= sizeof(ddc_setup_offset) / sizeof(int32_t))
		return false;
	if (arg->engine_id >= sizeof(ddc_speed_offset) / sizeof(int32_t))
		return false;
	if (!arg->reference_frequency)
		return false;

	if (!dal_i2c_hw_engine_construct(&engine_dce110->base, arg->ctx))
		return false;

	engine_dce110->base.base.base.funcs = &engine_funcs;
	engine_dce110->base.base.funcs = &i2c_engine_funcs;
	engine_dce110->base.funcs = &i2c_hw_engine_funcs;
	engine_dce110->base.default_speed = arg->default_speed;

	engine_dce110->engine_id = arg->engine_id;

	engine_dce110->buffer_used_bytes = 0;
	engine_dce110->transaction_count = 0;
	engine_dce110->engine_keep_power_up_count = 1;

	/*values which are not included by arg*/
	engine_dce110->addr.DC_I2C_DDCX_SETUP =
		mmDC_I2C_DDC1_SETUP + ddc_setup_offset[arg->engine_id];
	engine_dce110->addr.DC_I2C_DDCX_SPEED =
		mmDC_I2C_DDC1_SPEED + ddc_speed_offset[arg->engine_id];


	value = dal_read_reg(
		engine_dce110->base.base.base.ctx,
		mmMICROSECOND_TIME_BASE_DIV);

	xtal_ref_div = get_reg_field_value(
			value,
			MICROSECOND_TIME_BASE_DIV,
			XTAL_REF_DIV);

	if (xtal_ref_div == 0) {
		dal_logger_write(
				engine_dce110->base.base.base.ctx->logger,
				LOG_MAJOR_WARNING,
				LOG_MINOR_COMPONENT_I2C_AUX,
				"Invalid base timer divider\n",
				__func__);
		xtal_ref_div = 2;
	}

	/*Calculating Reference Clock by divding original frequency by
	 * XTAL_REF_DIV.
	 * At upper level, uint32_t reference_frequency =
	 *  dal_i2caux_get_reference_clock(as) >> 1
	 *  which already divided by 2. So we need x2 to get original
	 *  reference clock from ppll_info
	 */
	engine_dce110->reference_frequency =
		(arg->reference_frequency * 2) / xtal_ref_div;


	return true;
}